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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Diff between revs 34 and 36

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Rev 34 Rev 36
Line 53... Line 53...
 
 
#define CMD_REG         0
#define CMD_REG         0
#define CMD_DATA        1
#define CMD_DATA        1
#define CMD_HALT        (1<<10)
#define CMD_HALT        (1<<10)
#define CMD_STALL       (1<<9)
#define CMD_STALL       (1<<9)
#define CMD_STEP        (1<<8)
 
#define CMD_INT         (1<<7)
#define CMD_INT         (1<<7)
#define CMD_RESET       (1<<6)
#define CMD_RESET       (1<<6)
 
#define CMD_STEP        ((1<<8)|CMD_HALT)
 
 
#define KEY_ESCAPE      27
#define KEY_ESCAPE      27
#define KEY_RETURN      10
#define KEY_RETURN      10
 
#define CTRL(X)         ((X)&0x01f)
 
 
// No particular "parameters" need definition or redefinition here.
// No particular "parameters" need definition or redefinition here.
class   ZIPPY_TB : public TESTB<Vzipsystem> {
class   ZIPPY_TB : public TESTB<Vzipsystem> {
public:
public:
        unsigned long   m_mem_size;
        unsigned long   m_mem_size;
Line 71... Line 72...
        FILE            *dbg_fp;
        FILE            *dbg_fp;
        bool            dbg_flag, bomb;
        bool            dbg_flag, bomb;
        int             m_cursor;
        int             m_cursor;
 
 
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
                // dbg_fp = fopen("dbg.txt", "w");
                if (true) {
 
                        dbg_fp = fopen("dbg.txt", "w");
 
                        dbg_flag = true;
 
                } else {
                dbg_fp = NULL;
                dbg_fp = NULL;
                dbg_flag = false;
                dbg_flag = false;
 
                }
                bomb = false;
                bomb = false;
                m_cursor = 0;
                m_cursor = 0;
        }
        }
 
 
        void    reset(void) {
        void    reset(void) {
Line 177... Line 182...
 
 
        void    show_state(void) {
        void    show_state(void) {
                int     ln= 0;
                int     ln= 0;
 
 
                mvprintw(ln,0, "Peripherals-SS"); ln++;
                mvprintw(ln,0, "Peripherals-SS"); ln++;
 
                printw(" %s",
 
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
 
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
 
                        );
 
                /*
 
                printw(" %s%s%s",
 
                        (m_core->v__DOT__thecpu__DOT__ill_err)?"IL":"  ",
 
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":"  ",
 
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ",
 
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ",
 
                        );
 
                */
 
 
                /*
                /*
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
                        mvprintw(ln, 17, "%s%s",
                        mvprintw(ln, 17, "%s%s",
                                ((m_core->v__DOT__sys_cyc)
                                ((m_core->v__DOT__sys_cyc)
                                &&(m_core->v__DOT__sys_we)
                                &&(m_core->v__DOT__sys_we)
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
                                (m_core->v__DOT__trap_int)?"I":" ");
                                (m_core->v__DOT__trap_int)?"I":" ");
                */
                */
                showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
                showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
                showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
                showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
                showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
                showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
                showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
 
 
                ln++;
                ln++;
                showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
                showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
                showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
                showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
Line 235... Line 253...
                showreg(ln,40, "sR10", 10, (m_cursor==22));
                showreg(ln,40, "sR10", 10, (m_cursor==22));
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
 
 
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
                mvprintw(ln,40, "sCC :%s%s%s%s%s%s%s%s",
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
                        (m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
                        (m_cursor==26)?">":" ",
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
                        (m_core->v__DOT__thecpu__DOT__trap)?"TP":"  ",
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
                        (m_core->v__DOT__thecpu__DOT__break_en)?"BK":"  ",
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
                        (m_core->v__DOT__thecpu__DOT__step)?"ST":"  ",
 
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SL":"  ",
 
                        (m_core->v__DOT__thecpu__DOT__gie)?"IE":"  ",
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
                showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
                showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
Line 283... Line 303...
                showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
                showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
 
 
                attroff(A_BOLD);
                attroff(A_BOLD);
                ln+=1;
                ln+=1;
 
 
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d",
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting);
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting,
 
                        m_core->v__DOT__thecpu__DOT__pf__DOT__w_cv,
 
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
 
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr&0x0ffff);
                ln++;
                ln++;
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
                        (m_core->v__DOT__wb_data)); ln++;
                        (m_core->v__DOT__wb_data)); ln++;
 
 
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                        (m_core->v__DOT__thecpu__DOT__mem_cyc)?"CYC":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
                        (m_core->v__DOT__thecpu__DOT__mem_stb)?"STB":"   ",
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
 
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
 
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
                        (m_core->v__DOT__thecpu__DOT__mem_data),
                        (m_core->v__DOT__thecpu__DOT__mem_data),
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
                        (m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
 
 
                mvprintw(ln, 0, "SYSBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
 
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
                        (m_core->o_wb_cyc)?"CYC":"   ",
                        (m_core->o_wb_cyc)?"CYC":"   ",
                        (m_core->o_wb_stb)?"STB":"   ",
                        (m_core->o_wb_stb)?"STB":"   ",
                        (m_core->o_wb_we )?"WE":"  ",
                        (m_core->o_wb_we )?"WE":"  ",
                        (m_core->o_wb_addr),
                        (m_core->o_wb_addr),
                        (m_core->o_wb_data),
                        (m_core->o_wb_data),
Line 327... Line 353...
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        m_core->v__DOT__thecpu__DOT__pf_valid,
                        m_core->v__DOT__thecpu__DOT__pf_valid,
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
                        m_core->v__DOT__thecpu__DOT__gie,
                        m_core->v__DOT__thecpu__DOT__gie,
                        0,
                        0,
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
                        m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
 
 
                showins(ln, "Dc",
                showins(ln, "Dc",
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
Line 452... Line 478...
                        if (v & 0x000080)
                        if (v & 0x000080)
                                printw("PIC Enabled ");
                                printw("PIC Enabled ");
                } ln++;
                } ln++;
                showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
                showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
                showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
                showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
                showval(ln,40, "CACH", cmd_read(32+ 2), (m_cursor==2));
                // showval(ln,40, "CACH", cmd_read(32+ 2), (m_cursor==2));
                showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
                showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
                ln++;
                ln++;
                showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
                showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
                showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
                showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
                showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
                showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
Line 497... Line 523...
                dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++;
                dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++;
 
 
                dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
                dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
                dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
                dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
 
 
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s",
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
                        (m_cursor==26)?">":" ",
                        (m_cursor==26)?">":" ",
                        (cc & 0x100)?"TP":"  ",
                        (cc & 0x200)?"TP":"  ",
 
                        (cc & 0x080)?"BK":"  ",
                        (cc & 0x040)?"ST":"  ",
                        (cc & 0x040)?"ST":"  ",
                        (cc & 0x020)?"IE":"  ",
                        (cc & 0x020)?"IE":"  ",
                        (cc & 0x010)?"SL":"  ",
                        (cc & 0x010)?"SL":"  ",
                        (cc&8)?"V":" ",
                        (cc&8)?"V":" ",
                        (cc&4)?"N":" ",
                        (cc&4)?"N":" ",
Line 534... Line 561...
 
 
                dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40));
                dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40));
                dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
                dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
                cc = cmd_read(30);
                cc = cmd_read(30);
                mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
                mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
                        (m_cursor == 42)?">":" ",
                        (m_cursor == 42)?'>':' ',
                        (cc&0x100)?"TP":"  ",
                        (cc&0x100)?"TP":"  ",
                        (cc&0x040)?"ST":"  ",
                        (cc&0x040)?"ST":"  ",
                        (cc&0x020)?"IE":"  ",
                        (cc&0x020)?"IE":"  ",
                        (cc&0x010)?"SL":"  ",
                        (cc&0x010)?"SL":"  ",
                        (cc&8)?"V":" ",
                        (cc&8)?"V":" ",
Line 590... Line 617...
                */
                */
 
 
                int stb = m_core->o_wb_stb;
                int stb = m_core->o_wb_stb;
                if ((m_core->o_wb_addr & (-1<<20))!=1)
                if ((m_core->o_wb_addr & (-1<<20))!=1)
                        stb = 0;
                        stb = 0;
                m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
 
                        m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
 
                        m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
 
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
                        m_core->i_wb_ack = 1;
                        m_core->i_wb_ack = 1;
 
 
                if ((dbg_flag)&&(dbg_fp)) {
                if ((dbg_flag)&&(dbg_fp)) {
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n",
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
                                (m_core->i_dbg_cyc)?"CYC":"   ",
                                (m_core->i_dbg_cyc)?"CYC":"   ",
                                (m_core->i_dbg_stb)?"STB":
                                (m_core->i_dbg_stb)?"STB":
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
                                ((m_core->i_dbg_we)?"WE":"  "),
                                ((m_core->i_dbg_we)?"WE":"  "),
                                (m_core->i_dbg_addr),0,
                                (m_core->i_dbg_addr),0,
Line 612... Line 636...
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
                                (m_core->v__DOT__thecpu__DOT__mem_cyc)?"MCYC ":"",
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
 
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
Line 670... Line 695...
                                m_core->v__DOT__thecpu__DOT__alu_wr,
                                m_core->v__DOT__thecpu__DOT__alu_wr,
                                m_core->v__DOT__thecpu__DOT__alu_valid,
                                m_core->v__DOT__thecpu__DOT__alu_valid,
                                m_core->v__DOT__thecpu__DOT__mem_valid,
                                m_core->v__DOT__thecpu__DOT__mem_valid,
                                m_core->v__DOT__thecpu__DOT__w_iflags,
                                m_core->v__DOT__thecpu__DOT__w_iflags,
                                m_core->v__DOT__thecpu__DOT__w_uflags);
                                m_core->v__DOT__thecpu__DOT__w_uflags);
                        fprintf(dbg_fp, "\tbrk=%d,%d\n",
                        fprintf(dbg_fp, "\tbrk=%s %d,%d\n",
 
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
                                m_core->v__DOT__thecpu__DOT__break_en,
                                m_core->v__DOT__thecpu__DOT__break_en,
                                m_core->v__DOT__thecpu__DOT__op_break);
                                m_core->v__DOT__thecpu__DOT__op_break);
 
                } else if ((dbg_fp)&&
 
                                ((m_core->v__DOT__thecpu__DOT__op_break)
 
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
 
                        fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
 
                        fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d\n",
 
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
 
                                m_core->v__DOT__thecpu__DOT__break_en,
 
                                m_core->v__DOT__thecpu__DOT__dcd_break,
 
                                m_core->v__DOT__thecpu__DOT__op_break);
                }
                }
 
 
                if (dbg_fp) {
                if (dbg_fp) {
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
                                fprintf(dbg_fp, "\tClear Pipeline\n");
                                fprintf(dbg_fp, "\tClear Pipeline\n");
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
                                fprintf(dbg_fp, "\tNew PC\n");
                                fprintf(dbg_fp, "\tNew PC\n");
                }
                }
 
 
 
                if (dbg_fp)
 
                        fprintf(dbg_fp, "-----------  TICK ----------\n");
 
                if (false) {
 
                        m_core->i_clk = 1;
 
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
 
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
 
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
 
                        eval();
 
                        m_core->i_clk = 0;
 
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
 
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
 
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
 
                        eval();
 
                        m_tickcount++;
 
                } else {
 
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
 
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
 
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
                TESTB<Vzipsystem>::tick();
                TESTB<Vzipsystem>::tick();
 
                }
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
                                (gie)?"User":"Supervisor",
                                (gie)?"User":"Supervisor",
                                (gie)?"Supervisor":"User",
                                (gie)?"Supervisor":"User",
                                m_core->v__DOT__thecpu__DOT__ipc,
                                m_core->v__DOT__thecpu__DOT__ipc,
Line 714... Line 768...
        }
        }
 
 
        bool    test_failure(void) {
        bool    test_failure(void) {
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
                        &&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
                        &&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
                                == 0x2f0f7fff));
                                == 0x2f0f7fff)
 
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
        }
        }
 
 
        void    wb_write(unsigned a, unsigned int v) {
        void    wb_write(unsigned a, unsigned int v) {
 
                int     errcount = 0;
                mvprintw(0,35, "%40s", "");
                mvprintw(0,35, "%40s", "");
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
                m_core->i_dbg_cyc = 1;
                m_core->i_dbg_cyc = 1;
                m_core->i_dbg_stb = 1;
                m_core->i_dbg_stb = 1;
                m_core->i_dbg_we  = 1;
                m_core->i_dbg_we  = 1;
                m_core->i_dbg_addr = a & 1;
                m_core->i_dbg_addr = a & 1;
                m_core->i_dbg_data = v;
                m_core->i_dbg_data = v;
 
 
                tick();
                tick();
                while(m_core->o_dbg_stall)
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
                        tick();
                        tick();
 
 
                m_core->i_dbg_stb = 0;
                m_core->i_dbg_stb = 0;
                while(!m_core->o_dbg_ack)
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
                        tick();
                        tick();
 
 
                // Release the bus
                // Release the bus
                m_core->i_dbg_cyc = 0;
                m_core->i_dbg_cyc = 0;
                m_core->i_dbg_stb = 0;
                m_core->i_dbg_stb = 0;
                tick();
                tick();
                mvprintw(0,35, "%40s", "");
                mvprintw(0,35, "%40s", "");
                mvprintw(0,40, "wb_write -- complete");
                mvprintw(0,40, "wb_write -- complete");
 
 
 
 
 
                if (errcount >= 100)
 
                        bomb = true;
        }
        }
 
 
        unsigned long   wb_read(unsigned a) {
        unsigned long   wb_read(unsigned a) {
                unsigned int    v;
                unsigned int    v;
 
                int     errcount = 0;
                mvprintw(0,35, "%40s", "");
                mvprintw(0,35, "%40s", "");
                mvprintw(0,40, "wb_read(0x%08x)", a);
                mvprintw(0,40, "wb_read(0x%08x)", a);
                m_core->i_dbg_cyc = 1;
                m_core->i_dbg_cyc = 1;
                m_core->i_dbg_stb = 1;
                m_core->i_dbg_stb = 1;
                m_core->i_dbg_we  = 0;
                m_core->i_dbg_we  = 0;
                m_core->i_dbg_addr = a & 1;
                m_core->i_dbg_addr = a & 1;
 
 
                tick();
                tick();
                while(m_core->o_dbg_stall)
                while((errcount++<100)&&(m_core->o_dbg_stall))
                        tick();
                        tick();
 
 
                m_core->i_dbg_stb = 0;
                m_core->i_dbg_stb = 0;
                while(!m_core->o_dbg_ack)
                while((errcount++<100)&&(!m_core->o_dbg_ack))
                        tick();
                        tick();
                v = m_core->o_dbg_data;
                v = m_core->o_dbg_data;
 
 
                // Release the bus
                // Release the bus
                m_core->i_dbg_cyc = 0;
                m_core->i_dbg_cyc = 0;
Line 768... Line 829...
                tick();
                tick();
 
 
                mvprintw(0,35, "%40s", "");
                mvprintw(0,35, "%40s", "");
                mvprintw(0,40, "wb_read = 0x%08x", v);
                mvprintw(0,40, "wb_read = 0x%08x", v);
 
 
 
                if (errcount >= 100)
 
                        bomb = true;
                return v;
                return v;
        }
        }
 
 
        void    cursor_up(void) {
        void    cursor_up(void) {
                if (m_cursor > 3)
                if (m_cursor > 3)
Line 822... Line 885...
                        done = true;
                        done = true;
                        break;
                        break;
                case KEY_LEFT: case KEY_BACKSPACE:
                case KEY_LEFT: case KEY_BACKSPACE:
                        if (pos > 0) pos--;
                        if (pos > 0) pos--;
                        break;
                        break;
 
                case CTRL('L'): redrawwin(stdscr); break;
                case KEY_CLEAR:
                case KEY_CLEAR:
                        pos = 0;
                        pos = 0;
                        break;
                        break;
                case '0': case ' ': str[pos++] = '0'; break;
                case '0': case ' ': str[pos++] = '0'; break;
                case '1': str[pos++] = '1'; break;
                case '1': str[pos++] = '1'; break;
Line 887... Line 951...
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
                                }
                                }
                                break;
                                break;
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
                        case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
                        case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break;
                        case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break;
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
Line 929... Line 993...
}
}
 
 
int     main(int argc, char **argv) {
int     main(int argc, char **argv) {
        Verilated::commandArgs(argc, argv);
        Verilated::commandArgs(argc, argv);
        ZIPPY_TB        *tb = new ZIPPY_TB();
        ZIPPY_TB        *tb = new ZIPPY_TB();
        bool            autorun = false, exit_on_done = false;
        bool            autorun = false, exit_on_done = false, autostep=false;
 
 
        // mem[0x00000] = 0xbe000010; // Halt instruction
        // mem[0x00000] = 0xbe000010; // Halt instruction
        unsigned int mptr = 0;
        unsigned int mptr = 0;
 
 
        if (argc <= 1) {
        if (argc <= 1) {
Line 951... Line 1015...
                                        break;
                                        break;
                                case 'h':
                                case 'h':
                                        usage();
                                        usage();
                                        exit(0);
                                        exit(0);
                                        break;
                                        break;
 
                                case 's':
 
                                        autostep = true;
 
                                        break;
                                default:
                                default:
                                        usage();
                                        usage();
                                        exit(-1);
                                        exit(-1);
                                        break;
                                        break;
                                }
                                }
Line 992... Line 1059...
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
                        */
                        */
 
 
                        done = (tb->test_success())||(tb->test_failure());
                        done = (tb->test_success())||(tb->test_failure());
                }
                }
 
        } else if (autostep) {
 
                bool    done = false;
 
 
 
                printf("Running in non-interactive mode, via step commands\n");
 
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET);
 
                while(!done) {
 
                        tb->wb_write(CMD_REG, CMD_STEP);
 
                        done = (tb->test_success())||(tb->test_failure());
 
                }
        } else { // Interactive
        } else { // Interactive
                initscr();
                initscr();
                raw();
                raw();
                noecho();
                noecho();
                keypad(stdscr, true);
                keypad(stdscr, true);
Line 1032... Line 1108...
                                break;
                                break;
                        case 'q': case 'Q':
                        case 'q': case 'Q':
                                done = true;
                                done = true;
                                break;
                                break;
                        case 'r': case 'R':
                        case 'r': case 'R':
 
                                if (manual)
 
                                        tb->reset();
 
                                else
                                tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
                                tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
                                halted = true;
                                halted = true;
                                erase();
                                erase();
                                break;
                                break;
                        case 's': case 'S':
                        case 's': case 'S':
Line 1060... Line 1139...
                                break;
                                break;
                        case    KEY_UP:         tb->cursor_up();        break;
                        case    KEY_UP:         tb->cursor_up();        break;
                        case    KEY_DOWN:       tb->cursor_down();      break;
                        case    KEY_DOWN:       tb->cursor_down();      break;
                        case    KEY_LEFT:       tb->cursor_left();      break;
                        case    KEY_LEFT:       tb->cursor_left();      break;
                        case    KEY_RIGHT:      tb->cursor_right();     break;
                        case    KEY_RIGHT:      tb->cursor_right();     break;
 
                        case CTRL('L'): redrawwin(stdscr); break;
                        case ERR: case KEY_CLEAR:
                        case ERR: case KEY_CLEAR:
                        default:
                        default:
                                if (!manual)
                                if (!manual)
                                        tb->tick();
                                        tb->tick();
                        }
                        }
Line 1111... Line 1191...
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
        if (tb->m_core->v__DOT__mtc_data != 0)
        if (tb->m_core->v__DOT__mtc_data != 0)
                printf("Instructions / Clock: %.2f\n",
                printf("Instructions / Clock: %.2f\n",
                        (double)tb->m_core->v__DOT__mic_data
                        (double)tb->m_core->v__DOT__mic_data
                        / (double)tb->m_core->v__DOT__mtc_data);
                        / (double)tb->m_core->v__DOT__mtc_data);
        if (tb->test_success())
 
 
        int     rcode = 0;
 
        if (tb->bomb) {
 
                printf("TEST BOMBED\n");
 
                rcode = -1;
 
        } else if (tb->test_success()) {
                printf("SUCCESS!\n");
                printf("SUCCESS!\n");
        else if (tb->test_failure())
        } else if (tb->test_failure()) {
 
                rcode = -2;
                printf("TEST FAILED!\n");
                printf("TEST FAILED!\n");
        else
        } else
                printf("User quit\n");
                printf("User quit\n");
        exit(0);
        exit(rcode);
}
}
 
 
 
 
 No newline at end of file
 No newline at end of file

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