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[/] [zipcpu/] [trunk/] [doc/] [src/] [spec.tex] - Diff between revs 202 and 209

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        choice. Although it does not have many of the commonly used
        choice. Although it does not have many of the commonly used
        instructions, PUSH, POP, JSR, and RET among them, the simplified
        instructions, PUSH, POP, JSR, and RET among them, the simplified
        instruction set has demonstrated an amazing versatility. I will contend
        instruction set has demonstrated an amazing versatility. I will contend
        therefore and for anyone who will listen, that this instruction set
        therefore and for anyone who will listen, that this instruction set
        offers a full and complete capability for whatever a user might wish
        offers a full and complete capability for whatever a user might wish
        to do with two exceptions: bytewise character access and accelerated
        to do with the only exception being accelerated floating-point support.
        floating-point support.
 
\item The burst load/store approach using the wishbone pipelining mode is
\item The burst load/store approach using the wishbone pipelining mode is
        novel, and can be used to greatly increase the speed of the processor.
        novel, and can be used to greatly increase the speed of the processor.
\item The novel approach to interrupts greatly facilitates the development of
\item The novel approach to interrupts greatly facilitates the development of
        interrupt handlers from within high level languages.
        interrupt handlers from within high level languages.
 
 
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        language scripting in order to save their context upon any interrupt.
        language scripting in order to save their context upon any interrupt.
 
 
        At the same time, if most modern systems handle interrupt vectoring in
        At the same time, if most modern systems handle interrupt vectoring in
        software anyway, why maintain complicated hardware support for it?
        software anyway, why maintain complicated hardware support for it?
 
 
\item My goal of a high rate of instructions per clock may not be the proper
 
        measure of this CPU. For example, if instructions are being read from a
 
        SPI flash device, such as is common among FPGA implementations, these
 
        same instructions may suffer stalls of between 64 and 128 cycles per
 
        instruction just to read the instruction from the flash. Executing the
 
        instruction in a single clock cycle is no longer the appropriate
 
        measure. At the same time, it should be possible to use the DMA
 
        peripheral to copy instructions from the FLASH to a temporary memory
 
        location, after which they may be executed at a single instruction
 
        cycle per access again.
 
 
 
\item Both GCC and binutils back ends exist for the ZipCPU.
\item Both GCC and binutils back ends exist for the ZipCPU.
\item As of this version of the CPU, a newlib veresion of the C--library
\item As of this version of the CPU, a newlib veresion of the C--library
        now exists.
        now exists.
\end{itemize}
\end{itemize}
 
 

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