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% \graphicspath{{../gfx}}
% \graphicspath{{../gfx}}
\project{Zip CPU}
\project{Zip CPU}
\title{Specification}
\title{Specification}
\author{Dan Gisselquist, Ph.D.}
\author{Dan Gisselquist, Ph.D.}
\email{dgisselq (at) opencores.org}
\email{dgisselq (at) opencores.org}
\revision{Rev.~0.7}
\revision{Rev.~0.8}
\definecolor{webred}{rgb}{0.5,0,0}
\definecolor{webred}{rgb}{0.5,0,0}
\definecolor{webgreen}{rgb}{0,0.4,0}
\definecolor{webgreen}{rgb}{0,0.4,0}
\usepackage[dvips,ps2pdf,colorlinks=true,
\usepackage[dvips,ps2pdf,colorlinks=true,
        anchorcolor=black,pdfpagelabels,hypertexnames,
        anchorcolor=black,pdfpagelabels,hypertexnames,
        pdfauthor={Dan Gisselquist},
        pdfauthor={Dan Gisselquist},
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You should have received a copy of the GNU General Public License along
You should have received a copy of the GNU General Public License along
with this program.  If not, see \hbox{<http://www.gnu.org/licenses/>} for a
with this program.  If not, see \hbox{<http://www.gnu.org/licenses/>} for a
copy.
copy.
\end{license}
\end{license}
\begin{revisionhistory}
\begin{revisionhistory}
 
0.8 & 1/28/2016 & Gisselquist & Reduced complexity early branching \\\hline
0.7 & 12/22/2015 & Gisselquist & New Instruction Set Architecture \\\hline
0.7 & 12/22/2015 & Gisselquist & New Instruction Set Architecture \\\hline
0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline
0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline
0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline
0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline
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        & Absolute value, depends upon derived NEG.\\\hline
        & Absolute value, depends upon derived NEG.\\\hline
\parbox[t]{1.4in}{\tt ADD Ra,Rx\\ADDC Rb,Ry}
\parbox[t]{1.4in}{\tt ADD Ra,Rx\\ADDC Rb,Ry}
        & \parbox[t]{1.5in}{\tt Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry}
        & \parbox[t]{1.5in}{\tt Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry}
        & Add with carry \\\hline
        & Add with carry \\\hline
{\tt BRA.Cond +/-\$Addr}
{\tt BRA.Cond +/-\$Addr}
        & \hbox{\tt MOV.cond \$Addr+PC,PC}
        & \hbox{\tt ADD.cond \$Addr+PC,PC}
        & Branch or jump on condition.  Works for 13--bit
        & Branch or jump on condition.  Works for 18--bit
                signed address offsets.\\\hline
                signed address offsets.\\\hline
{\tt BRA.Cond +/-\$Addr}
{\tt BRA.Cond +/-\$Addr}
        & \parbox[t]{1.5in}{\tt LDI \$Addr,Rx \\ ADD.cond Rx,PC}
        & \parbox[t]{1.5in}{\tt LDI \$Addr,Rx \\ ADD.cond Rx,PC}
        & Branch/jump on condition.  Works for 23 bit address offsets, but
        & Branch/jump on condition.  Works for 23 bit address offsets, but
        costs a register and an extra instruction.  With LDIHI and LDILO
        costs a register and an extra instruction.  With LDIHI and LDILO
        this can be made to work anywhere in the 32-bit address space, but yet
        this can be made to work anywhere in the 32-bit address space, but yet
        cost an additional instruction still. \\\hline
        cost an additional instruction still. \\\hline
{\tt BNC PC+\$Addr}
{\tt BNC PC+\$Addr}
        & \parbox[t]{1.5in}{\tt Test \$Carry,CC \\ MOV.Z PC+\$Addr,PC}
        & \parbox[t]{1.5in}{\tt Test \$Carry,CC \\ ADD.Z PC+\$Addr,PC}
        & Example of a branch on an unsupported
        & Example of a branch on an unsupported
                condition, in this case a branch on not carry \\\hline
                condition, in this case a branch on not carry \\\hline
{\tt BUSY } & {\tt MOV \$-1(PC),PC} & Execute an infinite loop \\\hline
{\tt BUSY } & {\tt ADD \$-1,PC} & Execute an infinite loop \\\hline
{\tt CLRF.NZ Rx }
{\tt CLRF.NZ Rx }
        & {\tt XOR.NZ Rx,Rx}
        & {\tt XOR.NZ Rx,Rx}
        & Clear Rx, and flags, if the Z-bit is not set \\\hline
        & Clear Rx, and flags, if the Z-bit is not set \\\hline
{\tt CLR Rx }
{\tt CLR Rx }
        & {\tt LDI \$0,Rx}
        & {\tt LDI \$0,Rx}
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        mode this is simply a wait until interrupt instruction. \\\hline
        mode this is simply a wait until interrupt instruction. \\\hline
{\tt INT } & {\tt LDI \$0,CC} & This is also known as a trap instruction\\\hline
{\tt INT } & {\tt LDI \$0,CC} & This is also known as a trap instruction\\\hline
{\tt IRET}
{\tt IRET}
        & {\tt OR \$GIE,CC}
        & {\tt OR \$GIE,CC}
        & Also known as an RTU instruction (Return to Userspace) \\\hline
        & Also known as an RTU instruction (Return to Userspace) \\\hline
{\tt JMP R6+\$Addr}
{\tt JMP R6+\$Offset}
        & {\tt MOV \$Addr(R6),PC}
        & {\tt MOV \$Offset(R6),PC}
        & \\\hline
        & \\\hline
{\tt LJMP \$Addr}
{\tt LJMP \$Addr}
        & \parbox[t]{1.5in}{\tt LOD (PC),PC \\ {\em Address }}
        & \parbox[t]{1.5in}{\tt LOD (PC),PC \\ {\em Address }}
        & Although this only works for an unconditional jump, and it only
        & Although this only works for an unconditional jump, and it only
        works in a Von Neumann architecture, this instruction combination makes
        works in a Von Neumann architecture, this instruction combination makes
        for a nice combination that can be adjusted by a linker at a later
        for a nice combination that can be adjusted by a linker at a later
        time.\\\hline
        time.\\\hline
{\tt JSR PC+\$Addr  }
{\tt JSR PC+\$Offset  }
        & \parbox[t]{1.5in}{\tt MOV \$1+PC,R0 \\ MOV \$addr+PC,PC}
        & \parbox[t]{1.5in}{\tt MOV \$1+PC,R0 \\ ADD \$Offset,PC}
        & This is similar to the jump and link instructions from other
        & This is similar to the jump and link instructions from other
        architectures, save only that it requires a specific link
        architectures, save only that it requires a specific link
        instruction, also known as the {\tt MOV} instruction on the
        instruction, also known as the {\tt MOV} instruction on the
        left.\\\hline
        left.\\\hline
\end{tabular}
\end{tabular}
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{\tt IA}.  Therefore, the pipeline needs to be cleared and reloaded.
{\tt IA}.  Therefore, the pipeline needs to be cleared and reloaded.
Given that there are five stages to the pipeline, that accounts
Given that there are five stages to the pipeline, that accounts
for the four stalls.  (Were the {\tt pipefetch} cache chosen, there would
for the four stalls.  (Were the {\tt pipefetch} cache chosen, there would
be another stall internal to the {\tt pipefetch} cache.)
be another stall internal to the {\tt pipefetch} cache.)
 
 
The Zip CPU handles {\tt MOV \$X(PC),PC}, {\tt ADD \$X,PC}, and
The Zip CPU handles the {\tt ADD \$X,PC} and
{\tt LDI \$X,PC} instructions specially, however.  These instructions, when
{\tt LDI \$X,PC} instructions specially, however.  These instructions, when
not conditioned on the flags, can execute with only a single stall cycle,
not conditioned on the flags, can execute with only a single stall cycle,
such as is shown in Fig.~\ref{fig:branch}.\footnote{Note that when using the
such as is shown in Fig.~\ref{fig:branch}.\footnote{Note that when using the
{\tt pipefetch} cache, this requires an additional stall cycle due to that
{\tt pipefetch} cache, this requires an additional stall cycle due to that
cache's implementation.}
cache's implementation.}

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