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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [busdelay.v] - Diff between revs 195 and 201

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// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
Line 47... Line 47...
// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
 
// You should have received a copy of the GNU General Public License along
 
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
 
// target there if the PDF file isn't present.)  If not, see
 
// <http://www.gnu.org/licenses/> for a copy.
 
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
 
//
module  busdelay(i_clk,
module  busdelay(i_clk,
                // The input bus
                // The input bus
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
                        o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
                        o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
                // The delayed bus
                // The delayed bus
                o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr, o_dly_data,
                o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr,o_dly_data,o_dly_sel,
                        i_dly_ack, i_dly_stall, i_dly_data, i_dly_err);
                        i_dly_ack, i_dly_stall, i_dly_data, i_dly_err);
        parameter       AW=32, DW=32, DELAY_STALL = 0;
        parameter       AW=32, DW=32, DELAY_STALL = 0;
        input   i_clk;
        input   i_clk;
        // Input/master bus
        // Input/master bus
        input                           i_wb_cyc, i_wb_stb, i_wb_we;
        input                           i_wb_cyc, i_wb_stb, i_wb_we;
        input           [(AW-1):0]       i_wb_addr;
        input           [(AW-1):0]       i_wb_addr;
        input           [(DW-1):0]       i_wb_data;
        input           [(DW-1):0]       i_wb_data;
 
        input           [(DW/8-1):0]     i_wb_sel;
        output  reg                     o_wb_ack;
        output  reg                     o_wb_ack;
        output  wire                    o_wb_stall;
        output  wire                    o_wb_stall;
        output  reg     [(DW-1):0]       o_wb_data;
        output  reg     [(DW-1):0]       o_wb_data;
        output  wire                    o_wb_err;
        output  wire                    o_wb_err;
        // Delayed bus
        // Delayed bus
        output  reg                     o_dly_cyc, o_dly_stb, o_dly_we;
        output  reg                     o_dly_cyc, o_dly_stb, o_dly_we;
        output  reg     [(AW-1):0]       o_dly_addr;
        output  reg     [(AW-1):0]       o_dly_addr;
        output  reg     [(DW-1):0]       o_dly_data;
        output  reg     [(DW-1):0]       o_dly_data;
 
        output  reg     [(DW/8-1):0]     o_dly_sel;
        input                           i_dly_ack;
        input                           i_dly_ack;
        input                           i_dly_stall;
        input                           i_dly_stall;
        input           [(DW-1):0]       i_dly_data;
        input           [(DW-1):0]       i_dly_data;
        input                           i_dly_err;
        input                           i_dly_err;
 
 
        generate
        generate
        if (DELAY_STALL != 0)
        if (DELAY_STALL != 0)
        begin
        begin
                reg     r_stb, r_we, r_rtn_stall, r_rtn_err;
                reg     r_stb, r_we, r_rtn_stall, r_rtn_err;
                reg     [(DW-1):0]       r_data;
 
                reg     [(AW-1):0]       r_addr;
                reg     [(AW-1):0]       r_addr;
 
                reg     [(DW-1):0]       r_data;
 
                reg     [(DW/8-1):0]     r_sel;
 
 
                initial o_dly_cyc  = 1'b0;
                initial o_dly_cyc  = 1'b0;
                initial r_rtn_stall= 1'b0;
                initial r_rtn_stall= 1'b0;
                initial r_stb      = 1'b0;
                initial r_stb      = 1'b0;
                always @(posedge i_clk)
                always @(posedge i_clk)
Line 98... Line 107...
                        if (!i_dly_stall)
                        if (!i_dly_stall)
                        begin
                        begin
                                r_we   <= i_wb_we;
                                r_we   <= i_wb_we;
                                r_addr <= i_wb_addr;
                                r_addr <= i_wb_addr;
                                r_data <= i_wb_data;
                                r_data <= i_wb_data;
 
                                r_sel  <= i_wb_sel;
 
 
                                if (r_stb)
                                if (r_stb)
                                begin
                                begin
                                        o_dly_we   <= r_we;
                                        o_dly_we   <= r_we;
                                        o_dly_addr <= r_addr;
                                        o_dly_addr <= r_addr;
                                        o_dly_data <= r_data;
                                        o_dly_data <= r_data;
 
                                        o_dly_sel  <= r_sel;
                                        o_dly_stb  <= 1'b1;
                                        o_dly_stb  <= 1'b1;
                                        r_rtn_stall <= 1'b0;
                                        r_rtn_stall <= 1'b0;
                                        r_stb <= 1'b0;
                                        r_stb <= 1'b0;
                                end else begin
                                end else begin
                                        o_dly_we   <= i_wb_we;
                                        o_dly_we   <= i_wb_we;
                                        o_dly_addr <= i_wb_addr;
                                        o_dly_addr <= i_wb_addr;
                                        o_dly_data <= i_wb_data;
                                        o_dly_data <= i_wb_data;
 
                                        o_dly_sel  <= i_wb_sel;
                                        o_dly_stb  <= i_wb_stb;
                                        o_dly_stb  <= i_wb_stb;
                                        r_stb <= 1'b0;
                                        r_stb <= 1'b0;
                                        r_rtn_stall <= 1'b0;
                                        r_rtn_stall <= 1'b0;
                                end
                                end
                        end else if ((!r_stb)&&(!o_wb_stall))
                        end else if ((!r_stb)&&(!o_wb_stall))
                        begin
                        begin
                                r_we   <= i_wb_we;
                                r_we   <= i_wb_we;
                                r_addr <= i_wb_addr;
                                r_addr <= i_wb_addr;
                                r_data <= i_wb_data;
                                r_data <= i_wb_data;
 
                                r_sel  <= i_wb_sel;
                                r_stb  <= i_wb_stb;
                                r_stb  <= i_wb_stb;
 
 
                                r_rtn_stall <= i_wb_stb;
                                r_rtn_stall <= i_wb_stb;
                        end
                        end
 
 
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                                o_dly_addr<= i_wb_addr;
                                o_dly_addr<= i_wb_addr;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (~o_wb_stall)
                        if (~o_wb_stall)
                                o_dly_data <= i_wb_data;
                                o_dly_data <= i_wb_data;
                always @(posedge i_clk)
                always @(posedge i_clk)
 
                        if (~o_wb_stall)
 
                                o_dly_sel <= i_wb_sel;
 
                always @(posedge i_clk)
                        o_wb_ack  <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc);
                        o_wb_ack  <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc);
                always @(posedge i_clk)
                always @(posedge i_clk)
                        o_wb_data <= i_dly_data;
                        o_wb_data <= i_dly_data;
 
 
                // Our only non-delayed line, yet still really delayed.  Perhaps
                // Our only non-delayed line, yet still really delayed.  Perhaps

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