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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [busdelay.v] - Diff between revs 15 and 34
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| Rev 15 |
Rev 34 |
| Line 88... |
Line 88... |
o_wb_data <= i_dly_data;
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o_wb_data <= i_dly_data;
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// Our only non-delayed line, yet still really delayed. Perhaps
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// Our only non-delayed line, yet still really delayed. Perhaps
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// there's a way to register this?
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// there's a way to register this?
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// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
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// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
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assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(~o_dly_stb));
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assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(o_dly_stb));
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endmodule
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endmodule
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