| Line 1... |
Line 1... |
///////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Filename: wbarbiter.v
|
// Filename: wbarbiter.v
|
//
|
//
|
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
//
|
//
|
| Line 32... |
Line 32... |
//
|
//
|
//
|
//
|
// Creator: Dan Gisselquist, Ph.D.
|
// Creator: Dan Gisselquist, Ph.D.
|
// Gisselquist Technology, LLC
|
// Gisselquist Technology, LLC
|
//
|
//
|
///////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2015, Gisselquist Technology, LLC
|
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
|
//
|
//
|
// This program is free software (firmware): you can redistribute it and/or
|
// This program is free software (firmware): you can redistribute it and/or
|
// modify it under the terms of the GNU General Public License as published
|
// modify it under the terms of the GNU General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// your option) any later version.
|
// your option) any later version.
|
| Line 46... |
Line 46... |
// This program is distributed in the hope that it will be useful, but WITHOUT
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// for more details.
|
// for more details.
|
//
|
//
|
|
// You should have received a copy of the GNU General Public License along
|
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
|
// target there if the PDF file isn't present.) If not, see
|
|
// <http://www.gnu.org/licenses/> for a copy.
|
|
//
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// http://www.gnu.org/licenses/gpl.html
|
// http://www.gnu.org/licenses/gpl.html
|
//
|
//
|
//
|
//
|
///////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
|
//
|
//
|
//
|
`define WBA_ALTERNATING
|
`define WBA_ALTERNATING
|
module wbarbiter(i_clk, i_rst,
|
module wbarbiter(i_clk, i_rst,
|
// Bus A
|
// Bus A
|
i_a_adr, i_a_dat, i_a_we, i_a_stb, i_a_cyc, o_a_ack, o_a_stall, o_a_err,
|
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err,
|
// Bus B
|
// Bus B
|
i_b_adr, i_b_dat, i_b_we, i_b_stb, i_b_cyc, o_b_ack, o_b_stall, o_b_err,
|
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err,
|
// Both buses
|
// Both buses
|
o_adr, o_dat, o_we, o_stb, o_cyc, i_ack, i_stall, i_err);
|
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err);
|
// 18 bits will address one GB, 4 bytes at a time.
|
// 18 bits will address one GB, 4 bytes at a time.
|
// 19 bits will allow the ability to address things other than just
|
// 19 bits will allow the ability to address things other than just
|
// the 1GB of memory we are expecting.
|
// the 1GB of memory we are expecting.
|
parameter DW=32, AW=19;
|
parameter DW=32, AW=19;
|
// Wishbone doesn't use an i_ce signal. While it could, they dislike
|
// Wishbone doesn't use an i_ce signal. While it could, they dislike
|
// what it would (might) do to the synchronous reset signal, i_rst.
|
// what it would (might) do to the synchronous reset signal, i_rst.
|
input i_clk, i_rst;
|
input i_clk, i_rst;
|
input [(AW-1):0] i_a_adr, i_b_adr;
|
input [(AW-1):0] i_a_adr, i_b_adr;
|
input [(DW-1):0] i_a_dat, i_b_dat;
|
input [(DW-1):0] i_a_dat, i_b_dat;
|
|
input [(DW/8-1):0] i_a_sel, i_b_sel;
|
input i_a_we, i_a_stb, i_a_cyc;
|
input i_a_we, i_a_stb, i_a_cyc;
|
input i_b_we, i_b_stb, i_b_cyc;
|
input i_b_we, i_b_stb, i_b_cyc;
|
output wire o_a_ack, o_b_ack, o_a_stall, o_b_stall,
|
output wire o_a_ack, o_b_ack, o_a_stall, o_b_stall,
|
o_a_err, o_b_err;
|
o_a_err, o_b_err;
|
output wire [(AW-1):0] o_adr;
|
output wire [(AW-1):0] o_adr;
|
output wire [(DW-1):0] o_dat;
|
output wire [(DW-1):0] o_dat;
|
|
output wire [(DW/8-1):0] o_sel;
|
output wire o_we, o_stb, o_cyc;
|
output wire o_we, o_stb, o_cyc;
|
input i_ack, i_stall, i_err;
|
input i_ack, i_stall, i_err;
|
|
|
// All the fancy stuff here is done with the three primary signals:
|
// All the fancy stuff here is done with the three primary signals:
|
// o_cyc
|
// o_cyc
|
| Line 157... |
Line 165... |
|
|
// Realistically, if neither master owns the bus, the output is a
|
// Realistically, if neither master owns the bus, the output is a
|
// don't care. Thus we trigger off whether or not 'A' owns the bus.
|
// don't care. Thus we trigger off whether or not 'A' owns the bus.
|
// If 'B' owns it all we care is that 'A' does not. Likewise, if
|
// If 'B' owns it all we care is that 'A' does not. Likewise, if
|
// neither owns the bus than the values on the various lines are
|
// neither owns the bus than the values on the various lines are
|
// irrelevant.
|
// irrelevant. (This allows us to get two outputs per Xilinx 6-LUT)
|
|
assign o_stb = (o_cyc) && ((w_a_owner) ? i_a_stb : i_b_stb);
|
|
assign o_we = (w_a_owner) ? i_a_we : i_b_we;
|
assign o_adr = (w_a_owner) ? i_a_adr : i_b_adr;
|
assign o_adr = (w_a_owner) ? i_a_adr : i_b_adr;
|
assign o_dat = (w_a_owner) ? i_a_dat : i_b_dat;
|
assign o_dat = (w_a_owner) ? i_a_dat : i_b_dat;
|
assign o_we = (w_a_owner) ? i_a_we : i_b_we;
|
assign o_sel = (w_a_owner) ? i_a_sel : i_b_sel;
|
assign o_stb = (o_cyc) && ((w_a_owner) ? i_a_stb : i_b_stb);
|
|
|
|
// We cannot allow the return acknowledgement to ever go high if
|
// We cannot allow the return acknowledgement to ever go high if
|
// the master in question does not own the bus. Hence we force it
|
// the master in question does not own the bus. Hence we force it
|
// low if the particular master doesn't own the bus.
|
// low if the particular master doesn't own the bus.
|
assign o_a_ack = (w_a_owner) ? i_ack : 1'b0;
|
assign o_a_ack = (w_a_owner) ? i_ack : 1'b0;
|
