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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [wbpriarbiter.v] - Diff between revs 36 and 56

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//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
module  wbpriarbiter(i_clk, i_rst,
module  wbpriarbiter(i_clk,
        // Bus A
        // Bus A
        i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err,
        i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err,
        // Bus B
        // Bus B
        i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err,
        i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err,
        // Both buses
        // Both buses
        o_cyc, o_stb, o_we, o_adr, o_dat, i_ack, i_stall, i_err);
        o_cyc, o_stb, o_we, o_adr, o_dat, i_ack, i_stall, i_err);
        parameter                       DW=32, AW=32;
        parameter                       DW=32, AW=32;
        // Wishbone doesn't use an i_ce signal.  While it could, they dislike
        //
        // what it would (might) do to the synchronous reset signal, i_rst.
        input                           i_clk;
        input                           i_clk, i_rst;
 
        // Bus A
        // Bus A
        input                           i_a_cyc, i_a_stb, i_a_we;
        input                           i_a_cyc, i_a_stb, i_a_we;
        input           [(AW-1):0]       i_a_adr;
        input           [(AW-1):0]       i_a_adr;
        input           [(DW-1):0]       i_a_dat;
        input           [(DW-1):0]       i_a_dat;
        output  wire                    o_a_ack, o_a_stall, o_a_err;
        output  wire                    o_a_ack, o_a_stall, o_a_err;

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