| Line 40... |
Line 40... |
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wire [63:0] w_rol_tmp;
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wire [63:0] w_rol_tmp;
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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wire [31:0] w_rol_result;
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wire [31:0] w_rol_result;
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assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
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assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
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wire [33:0] w_lsr_result, w_asr_result;
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wire signed [33:0] w_ia_input;
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assign w_ia_input = { i_a[31], i_a, 1'b0 };
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assign w_asr_result = (|i_b[31:5])? {(34){i_a[31]}}
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: ( w_ia_input >>> (i_b[4:0]) );// ASR
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assign w_lsr_result = (|i_b[31:5])? 34'h00
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: { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR
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wire z, n, v;
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wire z, n, v;
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reg c, pre_sign, set_ovfl;
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reg c, pre_sign, set_ovfl;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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| Line 66... |
Line 73... |
4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
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4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
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4'ha: { c, o_c } <= i_a + i_b; // Add
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4'ha: { c, o_c } <= i_a + i_b; // Add
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4'hb: o_c <= i_a | i_b; // Or
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4'hb: o_c <= i_a | i_b; // Or
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4'hc: o_c <= i_a ^ i_b; // Xor
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4'hc: o_c <= i_a ^ i_b; // Xor
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4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'he: { c, o_c } <= (|i_b[31:5])? {(33){i_a[31]}}:{ i_a[31],i_a}>> (i_b[4:0]);// ASR
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4'he: { o_c, c } <= w_asr_result[32:0];// ASR
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4'hf: { c, o_c } <= (|i_b[31:5])? 33'h00 : { 1'b0, i_a } >> (i_b[4:0]);// LSR
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4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR
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default: o_c <= i_b; // MOV, LDI
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default: o_c <= i_b; // MOV, LDI
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endcase
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endcase
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end
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end
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assign z = (o_c == 32'h0000);
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assign z = (o_c == 32'h0000);
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