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[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Diff between revs 193 and 201

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///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    cpuops.v
// Filename:    cpuops.v
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
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//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
 
// You should have received a copy of the GNU General Public License along
 
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
 
// target there if the PDF file isn't present.)  If not, see
 
// <http://www.gnu.org/licenses/> for a copy.
 
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
`include "cpudefs.v"
`include "cpudefs.v"
//
//
module  cpuops(i_clk,i_rst, i_ce, i_op, i_a, i_b, o_c, o_f, o_valid,
module  cpuops(i_clk,i_rst, i_ce, i_op, i_a, i_b, o_c, o_f, o_valid,
                        o_busy);
                        o_busy);
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        output  reg     [31:0]   o_c;
        output  reg     [31:0]   o_c;
        output  wire    [3:0]    o_f;
        output  wire    [3:0]    o_f;
        output  reg             o_valid;
        output  reg             o_valid;
        output  wire            o_busy;
        output  wire            o_busy;
 
 
        // Rotate-left pre-logic
 
        wire    [63:0]   w_rol_tmp;
 
        assign  w_rol_tmp = { i_a, i_a } << i_b[4:0];
 
        wire    [31:0]   w_rol_result;
 
        assign  w_rol_result = w_rol_tmp[63:32]; // Won't set flags
 
 
 
        // Shift register pre-logic
        // Shift register pre-logic
        wire    [32:0]           w_lsr_result, w_asr_result, w_lsl_result;
        wire    [32:0]           w_lsr_result, w_asr_result, w_lsl_result;
        wire    signed  [32:0]   w_pre_asr_input, w_pre_asr_shifted;
        wire    signed  [32:0]   w_pre_asr_input, w_pre_asr_shifted;
        assign  w_pre_asr_input = { i_a, 1'b0 };
        assign  w_pre_asr_input = { i_a, 1'b0 };
        assign  w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];
        assign  w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];
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        for(k=0; k<32; k=k+1)
        for(k=0; k<32; k=k+1)
        begin : bit_reversal_cpuop
        begin : bit_reversal_cpuop
                assign w_brev_result[k] = i_b[31-k];
                assign w_brev_result[k] = i_b[31-k];
        end endgenerate
        end endgenerate
 
 
        // Popcount pre-logic
 
        wire    [31:0]   w_popc_result;
 
        assign  w_popc_result[5:0]=
 
                 ({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
 
                +({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]})
 
                +({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]})
 
                +({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]})
 
                +({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]})
 
                +({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]})
 
                +({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]})
 
                +({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]});
 
        assign  w_popc_result[31:6] = 26'h00;
 
 
 
        // Prelogic for our flags registers
        // Prelogic for our flags registers
        wire    z, n, v;
        wire    z, n, v;
        reg     c, pre_sign, set_ovfl;
        reg     c, pre_sign, set_ovfl, keep_sgn_on_ovfl;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_ce) // 1 LUT
                if (i_ce) // 1 LUT
                        set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
                        set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
                                ||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
                                ||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
                                ||(i_op == 4'h6) // LSL
                                ||(i_op == 4'h6) // LSL
                                ||(i_op == 4'h5)); // LSR
                                ||(i_op == 4'h5)); // LSR
 
        always @(posedge i_clk)
 
                if (i_ce) // 1 LUT
 
                        keep_sgn_on_ovfl<=
 
                                (((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
 
                                ||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD
 
 
        wire    [63:0]   mpy_result; // Where we dump the multiply result
        wire    [63:0]   mpy_result; // Where we dump the multiply result
        reg     mpyhi;          // Return the high half of the multiply
        reg     mpyhi;          // Return the high half of the multiply
        wire    mpybusy;        // The multiply is busy if true
        wire    mpybusy;        // The multiply is busy if true
        wire    mpydone;        // True if we'll be valid on the next clock;
        wire    mpydone;        // True if we'll be valid on the next clock;
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        //      the Xilinx multiplexer fabric that follows. 
        //      the Xilinx multiplexer fabric that follows. 
        // Given that we wish to apply this multiplexer approach to 33-bits,
        // Given that we wish to apply this multiplexer approach to 33-bits,
        // this will cost a minimum of 132 6-LUTs.
        // this will cost a minimum of 132 6-LUTs.
 
 
        wire    this_is_a_multiply_op;
        wire    this_is_a_multiply_op;
        assign  this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'h8));
        assign  this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc));
 
 
        generate
        generate
        if (IMPLEMENT_MPY == 0)
        if (IMPLEMENT_MPY == 0)
        begin // No multiply support.
        begin // No multiply support.
                assign  mpy_result = 63'h00;
                assign  mpy_result = 63'h00;
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                4'b0011:   o_c   <= i_a | i_b;          // Or
                4'b0011:   o_c   <= i_a | i_b;          // Or
                4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
                4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
                4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
                4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
                4'b1000:   o_c   <= mpy_result[31:0]; // MPY
                4'b1000:   o_c   <= w_brev_result;      // BREV
                4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                4'b1010:   o_c   <= mpy_result[63:32]; // MPYHU
                4'b1010:   o_c   <= mpy_result[63:32]; // MPYHU
                4'b1011:   o_c   <= mpy_result[63:32]; // MPYHS
                4'b1011:   o_c   <= mpy_result[63:32]; // MPYHS
                4'b1100:   o_c   <= w_brev_result;      // BREV
                4'b1100:   o_c   <= mpy_result[31:0];    // MPY
                4'b1101:   o_c   <= w_popc_result;      // POPC
 
                4'b1110:   o_c   <= w_rol_result;       // ROL
 
                default:   o_c   <= i_b;                // MOV, LDI
                default:   o_c   <= i_b;                // MOV, LDI
                endcase
                endcase
        end else // if (mpydone)
        end else // if (mpydone)
                o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0];
                o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0];
 
 
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        assign  z = (o_c == 32'h0000);
        assign  z = (o_c == 32'h0000);
        assign  n = (o_c[31]);
        assign  n = (o_c[31]);
        assign  v = (set_ovfl)&&(pre_sign != o_c[31]);
        assign  v = (set_ovfl)&&(pre_sign != o_c[31]);
 
        wire    vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]);
 
 
        assign  o_f = { v, n, c, z };
        assign  o_f = { v, n^vx, c, z };
 
 
        initial o_valid = 1'b0;
        initial o_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        o_valid <= 1'b0;
                        o_valid <= 1'b0;

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