////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: cpuops.v
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// Filename: cpuops.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: This supports the instruction set reordering of operations
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// Purpose: This is the ZipCPU ALU function. It handles all of the
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// created by the second generation instruction set, as well as
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// instruction opcodes 0-13. (14-15 are divide opcodes).
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// the new operations of POPC (population count) and BREV (bit reversal).
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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// Copyright (C) 2015-2019, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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`default_nettype none
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//
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//
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`include "cpudefs.v"
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`include "cpudefs.v"
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//
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//
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module cpuops(i_clk,i_rst, i_ce, i_op, i_a, i_b, o_c, o_f, o_valid,
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module cpuops(i_clk,i_reset, i_stb, i_op, i_a, i_b, o_c, o_f, o_valid,
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o_busy);
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o_busy);
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parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
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parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
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input i_clk, i_rst, i_ce;
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parameter [0:0] OPT_SHIFTS = 1'b1;
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input [3:0] i_op;
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input wire i_clk, i_reset, i_stb;
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input [31:0] i_a, i_b;
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input wire [3:0] i_op;
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input wire [31:0] i_a, i_b;
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output reg [31:0] o_c;
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output reg [31:0] o_c;
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output wire [3:0] o_f;
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output wire [3:0] o_f;
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output reg o_valid;
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output reg o_valid;
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output wire o_busy;
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output wire o_busy;
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genvar k;
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// Shift register pre-logic
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// Shift register pre-logic
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wire [32:0] w_lsr_result, w_asr_result, w_lsl_result;
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wire [32:0] w_lsr_result, w_asr_result, w_lsl_result;
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generate if (OPT_SHIFTS)
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begin : IMPLEMENT_SHIFTS
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wire signed [32:0] w_pre_asr_input, w_pre_asr_shifted;
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wire signed [32:0] w_pre_asr_input, w_pre_asr_shifted;
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assign w_pre_asr_input = { i_a, 1'b0 };
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assign w_pre_asr_input = { i_a, 1'b0 };
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assign w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];
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assign w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];
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assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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: w_pre_asr_shifted;// ASR
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: w_pre_asr_shifted;// ASR
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assign w_lsr_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
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assign w_lsr_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
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:((i_b[5])?{32'h0,i_a[31]}
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:((i_b[5])?{32'h0,i_a[31]}
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: ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR
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: ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR
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assign w_lsl_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
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assign w_lsl_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
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:((i_b[5])?{i_a[0], 32'h0}
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:((i_b[5])?{i_a[0], 32'h0}
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: ({1'b0, i_a } << i_b[4:0])); // LSL
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: ({1'b0, i_a } << i_b[4:0])); // LSL
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end else begin : NO_SHIFTS
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assign w_asr_result = { i_a[31], i_a[31:0] };
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assign w_lsr_result = { 1'b0, i_a[31:0] };
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assign w_lsl_result = { i_a[31:0], 1'b0 };
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end endgenerate
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//
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// Bit reversal pre-logic
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// Bit reversal pre-logic
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wire [31:0] w_brev_result;
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wire [31:0] w_brev_result;
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genvar k;
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generate
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generate
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for(k=0; k<32; k=k+1)
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for(k=0; k<32; k=k+1)
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begin : bit_reversal_cpuop
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begin : bit_reversal_cpuop
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assign w_brev_result[k] = i_b[31-k];
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assign w_brev_result[k] = i_b[31-k];
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end endgenerate
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end endgenerate
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// Prelogic for our flags registers
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// Prelogic for our flags registers
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wire z, n, v;
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wire z, n, v;
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reg c, pre_sign, set_ovfl, keep_sgn_on_ovfl;
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reg c, pre_sign, set_ovfl, keep_sgn_on_ovfl;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce) // 1 LUT
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if (i_stb) // 1 LUT
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set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
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||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
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||(i_op == 4'h6) // LSL
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||(i_op == 4'h6) // LSL
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||(i_op == 4'h5)); // LSR
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||(i_op == 4'h5)); // LSR
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce) // 1 LUT
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if (i_stb) // 1 LUT
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keep_sgn_on_ovfl<=
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keep_sgn_on_ovfl<=
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(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD
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||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD
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wire [63:0] mpy_result; // Where we dump the multiply result
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wire [63:0] mpy_result; // Where we dump the multiply result
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reg mpyhi; // Return the high half of the multiply
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wire mpyhi; // Return the high half of the multiply
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wire mpybusy; // The multiply is busy if true
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wire mpybusy; // The multiply is busy if true
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wire mpydone; // True if we'll be valid on the next clock;
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wire mpydone; // True if we'll be valid on the next clock;
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// A 4-way multiplexer can be done in one 6-LUT.
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// A 4-way multiplexer can be done in one 6-LUT.
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// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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// the Xilinx multiplexer fabric that follows.
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// the Xilinx multiplexer fabric that follows.
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// Given that we wish to apply this multiplexer approach to 33-bits,
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// Given that we wish to apply this multiplexer approach to 33-bits,
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// this will cost a minimum of 132 6-LUTs.
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// this will cost a minimum of 132 6-LUTs.
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wire this_is_a_multiply_op;
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wire this_is_a_multiply_op;
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assign this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc));
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assign this_is_a_multiply_op = (i_stb)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc));
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generate
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//
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if (IMPLEMENT_MPY == 0)
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// Pull in the multiply logic from elsewhere
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begin // No multiply support.
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//
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assign mpy_result = 63'h00;
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`ifdef FORMAL
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end else if (IMPLEMENT_MPY == 1)
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`define MPYOP abs_mpy
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begin // Our single clock option (no extra clocks)
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wire signed [63:0] w_mpy_a_input, w_mpy_b_input;
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assign w_mpy_a_input = {{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
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assign w_mpy_b_input = {{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
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assign mpy_result = w_mpy_a_input * w_mpy_b_input;
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assign mpybusy = 1'b0;
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assign mpydone = 1'b0;
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always @(*) mpyhi = 1'b0; // Not needed
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end else if (IMPLEMENT_MPY == 2)
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begin // Our two clock option (ALU must pause for 1 clock)
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reg signed [63:0] r_mpy_a_input, r_mpy_b_input;
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always @(posedge i_clk)
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begin
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r_mpy_a_input <={{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
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r_mpy_b_input <={{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
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end
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assign mpy_result = r_mpy_a_input * r_mpy_b_input;
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assign mpybusy = 1'b0;
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reg mpypipe;
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initial mpypipe = 1'b0;
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always @(posedge i_clk)
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if (i_rst)
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mpypipe <= 1'b0;
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else
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mpypipe <= (this_is_a_multiply_op);
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assign mpydone = mpypipe; // this_is_a_multiply_op;
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always @(posedge i_clk)
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if (this_is_a_multiply_op)
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mpyhi = i_op[1];
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end else if (IMPLEMENT_MPY == 3)
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begin // Our three clock option (ALU pauses for 2 clocks)
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reg signed [63:0] r_smpy_result;
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reg [63:0] r_umpy_result;
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reg signed [31:0] r_mpy_a_input, r_mpy_b_input;
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reg [1:0] mpypipe;
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reg [1:0] r_sgn;
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initial mpypipe = 2'b0;
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always @(posedge i_clk)
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if (i_rst)
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mpypipe <= 2'b0;
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else
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mpypipe <= { mpypipe[0], this_is_a_multiply_op };
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// First clock
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always @(posedge i_clk)
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begin
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r_mpy_a_input <= i_a[31:0];
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r_mpy_b_input <= i_b[31:0];
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r_sgn <= { r_sgn[0], i_op[0] };
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end
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// Second clock
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`ifdef VERILATOR
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wire signed [63:0] s_mpy_a_input, s_mpy_b_input;
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wire [63:0] u_mpy_a_input, u_mpy_b_input;
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assign s_mpy_a_input = {{(32){r_mpy_a_input[31]}},r_mpy_a_input};
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assign s_mpy_b_input = {{(32){r_mpy_b_input[31]}},r_mpy_b_input};
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assign u_mpy_a_input = {32'h00,r_mpy_a_input};
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assign u_mpy_b_input = {32'h00,r_mpy_b_input};
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always @(posedge i_clk)
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r_smpy_result = s_mpy_a_input * s_mpy_b_input;
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always @(posedge i_clk)
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r_umpy_result = u_mpy_a_input * u_mpy_b_input;
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`else
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`else
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`define MPYOP mpyop
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wire [31:0] u_mpy_a_input, u_mpy_b_input;
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assign u_mpy_a_input = r_mpy_a_input;
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assign u_mpy_b_input = r_mpy_b_input;
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always @(posedge i_clk)
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r_smpy_result = r_mpy_a_input * r_mpy_b_input;
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always @(posedge i_clk)
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r_umpy_result = u_mpy_a_input * u_mpy_b_input;
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`endif
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`endif
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`MPYOP #(.IMPLEMENT_MPY(IMPLEMENT_MPY)) thempy(i_clk, i_reset, this_is_a_multiply_op, i_op[1:0],
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always @(posedge i_clk)
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i_a, i_b, mpydone, mpybusy, mpy_result, mpyhi);
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if (this_is_a_multiply_op)
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mpyhi = i_op[1];
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assign mpybusy = mpypipe[0];
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assign mpy_result = (r_sgn[1])?r_smpy_result:r_umpy_result;
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assign mpydone = mpypipe[1];
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// Results are then set on the third clock
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end else // if (IMPLEMENT_MPY <= 4)
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begin // The three clock option
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reg [63:0] r_mpy_result;
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reg [31:0] r_mpy_a_input, r_mpy_b_input;
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reg r_mpy_signed;
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reg [2:0] mpypipe;
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// First clock, latch in the inputs
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initial mpypipe = 3'b0;
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always @(posedge i_clk)
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begin
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// mpypipe indicates we have a multiply in the
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// pipeline. In this case, the multiply
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// pipeline is a two stage pipeline, so we need
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// two bits in the pipe.
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if (i_rst)
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mpypipe <= 3'h0;
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else begin
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mpypipe[0] <= this_is_a_multiply_op;
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mpypipe[1] <= mpypipe[0];
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mpypipe[2] <= mpypipe[1];
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end
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if (i_op[0]) // i.e. if signed multiply
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begin
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r_mpy_a_input <= {(~i_a[31]),i_a[30:0]};
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r_mpy_b_input <= {(~i_b[31]),i_b[30:0]};
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end else begin
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r_mpy_a_input <= i_a[31:0];
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r_mpy_b_input <= i_b[31:0];
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end
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// The signed bit really only matters in the
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// case of 64 bit multiply. We'll keep track
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// of it, though, and pretend in all other
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// cases.
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r_mpy_signed <= i_op[0];
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if (this_is_a_multiply_op)
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mpyhi = i_op[1];
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end
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assign mpybusy = |mpypipe[1:0];
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assign mpydone = mpypipe[2];
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// Second clock, do the multiplies, get the "partial
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// products". Here, we break our input up into two
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// halves,
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//
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// A = (2^16 ah + al)
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// B = (2^16 bh + bl)
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//
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// and use these to compute partial products.
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//
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// AB = (2^32 ah*bh + 2^16 (ah*bl + al*bh) + (al*bl)
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//
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// Since we're following the FOIL algorithm to get here,
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// we'll name these partial products according to FOIL.
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//
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// The trick is what happens if A or B is signed. In
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// those cases, the real value of A will not be given by
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// A = (2^16 ah + al)
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// but rather
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// A = (2^16 ah[31^] + al) - 2^31
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// (where we have flipped the sign bit of A)
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// and so ...
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//
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// AB= (2^16 ah + al - 2^31) * (2^16 bh + bl - 2^31)
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// = 2^32(ah*bh)
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// +2^16 (ah*bl+al*bh)
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// +(al*bl)
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// - 2^31 (2^16 bh+bl + 2^16 ah+al)
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// - 2^62
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// = 2^32(ah*bh)
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// +2^16 (ah*bl+al*bh)
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// +(al*bl)
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// - 2^31 (2^16 bh+bl + 2^16 ah+al + 2^31)
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//
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reg [31:0] pp_f, pp_l; // F and L from FOIL
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reg [32:0] pp_oi; // The O and I from FOIL
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reg [32:0] pp_s;
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always @(posedge i_clk)
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begin
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pp_f<=r_mpy_a_input[31:16]*r_mpy_b_input[31:16];
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pp_oi<=r_mpy_a_input[31:16]*r_mpy_b_input[15: 0]
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+ r_mpy_a_input[15: 0]*r_mpy_b_input[31:16];
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pp_l<=r_mpy_a_input[15: 0]*r_mpy_b_input[15: 0];
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// And a special one for the sign
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if (r_mpy_signed)
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pp_s <= 32'h8000_0000-(
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r_mpy_a_input[31:0]
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+ r_mpy_b_input[31:0]);
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else
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pp_s <= 33'h0;
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end
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// Third clock, add the results and produce a product
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always @(posedge i_clk)
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begin
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r_mpy_result[15:0] <= pp_l[15:0];
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r_mpy_result[63:16] <=
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{ 32'h00, pp_l[31:16] }
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+ { 15'h00, pp_oi }
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+ { pp_s, 15'h00 }
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+ { pp_f, 16'h00 };
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end
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assign mpy_result = r_mpy_result;
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// Fourth clock -- results are clocked into writeback
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end
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endgenerate // All possible multiply results have been determined
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//
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//
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// The master ALU case statement
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// The master ALU case statement
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//
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//
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_stb)
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begin
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begin
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pre_sign <= (i_a[31]);
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pre_sign <= (i_a[31]);
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c <= 1'b0;
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c <= 1'b0;
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casez(i_op)
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casez(i_op)
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4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
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4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
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4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
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4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b1000: o_c <= w_brev_result; // BREV
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4'b1000: o_c <= w_brev_result; // BREV
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'b1010: o_c <= mpy_result[63:32]; // MPYHU
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4'b1010: o_c <= mpy_result[63:32]; // MPYHU
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4'b1011: o_c <= mpy_result[63:32]; // MPYHS
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4'b1011: o_c <= mpy_result[63:32]; // MPYHS
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4'b1100: o_c <= mpy_result[31:0]; // MPY
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4'b1100: o_c <= mpy_result[31:0]; // MPY
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default: o_c <= i_b; // MOV, LDI
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default: o_c <= i_b; // MOV, LDI
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endcase
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endcase
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end else // if (mpydone)
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end else // if (mpydone)
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// set the output based upon the multiply result
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o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0];
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o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0];
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reg r_busy;
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reg r_busy;
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initial r_busy = 1'b0;
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initial r_busy = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_reset)
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r_busy <= 1'b0;
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r_busy <= 1'b0;
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else if (IMPLEMENT_MPY > 1)
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r_busy <= ((i_stb)&&(this_is_a_multiply_op))||mpybusy;
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else
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else
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r_busy <= ((IMPLEMENT_MPY > 1)
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r_busy <= 1'b0;
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&&(this_is_a_multiply_op))||mpybusy;
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assign o_busy = (r_busy); // ||((IMPLEMENT_MPY>1)&&(this_is_a_multiply_op));
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assign o_busy = (r_busy); // ||((IMPLEMENT_MPY>1)&&(this_is_a_multiply_op));
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|
|
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assign z = (o_c == 32'h0000);
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assign z = (o_c == 32'h0000);
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assign n = (o_c[31]);
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assign n = (o_c[31]);
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assign v = (set_ovfl)&&(pre_sign != o_c[31]);
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assign v = (set_ovfl)&&(pre_sign != o_c[31]);
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wire vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]);
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wire vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]);
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|
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assign o_f = { v, n^vx, c, z };
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assign o_f = { v, n^vx, c, z };
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|
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initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
|
if (i_reset)
|
o_valid <= 1'b0;
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o_valid <= 1'b0;
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else if (IMPLEMENT_MPY <= 1)
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else if (IMPLEMENT_MPY <= 1)
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o_valid <= (i_ce);
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o_valid <= (i_stb);
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else
|
else
|
o_valid <=((i_ce)&&(!this_is_a_multiply_op))||(mpydone);
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o_valid <=((i_stb)&&(!this_is_a_multiply_op))||(mpydone);
|
|
|
|
`ifdef FORMAL
|
|
initial assume(i_reset);
|
|
reg f_past_valid;
|
|
|
|
initial f_past_valid = 1'b0;
|
|
always @(posedge i_clk)
|
|
f_past_valid = 1'b1;
|
|
|
|
`define ASSERT assert
|
|
`ifdef CPUOPS
|
|
`define ASSUME assume
|
|
`else
|
|
`define ASSUME assert
|
|
`endif
|
|
|
|
// No request should be given us if/while we are busy
|
|
always @(posedge i_clk)
|
|
if (o_busy)
|
|
`ASSUME(!i_stb);
|
|
|
|
// Following any request other than a multiply request, we should
|
|
// respond in the next cycle
|
|
always @(posedge i_clk)
|
|
if ((f_past_valid)&&(!$past(o_busy))&&(!$past(this_is_a_multiply_op)))
|
|
`ASSERT(!o_busy);
|
|
|
|
// Valid and busy can never both be asserted
|
|
always @(posedge i_clk)
|
|
`ASSERT((!o_valid)||(!r_busy));
|
|
|
|
// Following any busy, we should always become valid
|
|
always @(posedge i_clk)
|
|
if ((f_past_valid)&&($past(o_busy))&&(!o_busy))
|
|
`ASSERT($past(i_reset) || o_valid);
|
|
|
|
// Check the shift values
|
|
always @(posedge i_clk)
|
|
if ((f_past_valid)&&($past(i_stb)))
|
|
begin
|
|
if (($past(|i_b[31:6]))||($past(i_b[5:0])>6'd32))
|
|
begin
|
|
assert(($past(i_op)!=4'h5)
|
|
||({o_c,c}=={(33){1'b0}}));
|
|
assert(($past(i_op)!=4'h6)
|
|
||({c,o_c}=={(33){1'b0}}));
|
|
assert(($past(i_op)!=4'h7)
|
|
||({o_c,c}=={(33){$past(i_a[31])}}));
|
|
end else if ($past(i_b[5:0]==6'd32))
|
|
begin
|
|
assert(($past(i_op)!=4'h5)
|
|
||(o_c=={(32){1'b0}}));
|
|
assert(($past(i_op)!=4'h6)
|
|
||(o_c=={(32){1'b0}}));
|
|
assert(($past(i_op)!=4'h7)
|
|
||(o_c=={(32){$past(i_a[31])}}));
|
|
end if ($past(i_b)==0)
|
|
begin
|
|
assert(($past(i_op)!=4'h5)
|
|
||({o_c,c}=={$past(i_a), 1'b0}));
|
|
assert(($past(i_op)!=4'h6)
|
|
||({c,o_c}=={1'b0, $past(i_a)}));
|
|
assert(($past(i_op)!=4'h7)
|
|
||({o_c,c}=={$past(i_a), 1'b0}));
|
|
end if ($past(i_b)==1)
|
|
begin
|
|
assert(($past(i_op)!=4'h5)
|
|
||({o_c,c}=={1'b0, $past(i_a)}));
|
|
assert(($past(i_op)!=4'h6)
|
|
||({c,o_c}=={$past(i_a),1'b0}));
|
|
assert(($past(i_op)!=4'h7)
|
|
||({o_c,c}=={$past(i_a[31]),$past(i_a)}));
|
|
end if ($past(i_b)==2)
|
|
begin
|
|
assert(($past(i_op)!=4'h5)
|
|
||({o_c,c}=={2'b0, $past(i_a[31:1])}));
|
|
assert(($past(i_op)!=4'h6)
|
|
||({c,o_c}=={$past(i_a[30:0]),2'b0}));
|
|
assert(($past(i_op)!=4'h7)
|
|
||({o_c,c}=={{(2){$past(i_a[31])}},$past(i_a[31:1])}));
|
|
end if ($past(i_b)==31)
|
|
begin
|
|
assert(($past(i_op)!=4'h5)
|
|
||({o_c,c}=={31'b0, $past(i_a[31:30])}));
|
|
assert(($past(i_op)!=4'h6)
|
|
||({c,o_c}=={$past(i_a[1:0]),31'b0}));
|
|
assert(($past(i_op)!=4'h7)
|
|
||({o_c,c}=={{(31){$past(i_a[31])}},$past(i_a[31:30])}));
|
|
end
|
|
end
|
|
`endif
|
endmodule
|
endmodule
|
|
//
|
|
// iCE40 NoMPY,w/Shift NoMPY,w/o Shift
|
|
// SB_CARRY 64 64
|
|
// SB_DFFE 3 3
|
|
// SB_DFFESR 1 1
|
|
// SB_DFFSR 33 33
|
|
// SB_LUT4 748 323
|
|
|
No newline at end of file
|
No newline at end of file
|
