| Line 48... |
Line 48... |
assign w_asr_result = (|i_b[31:5])? {(34){i_a[31]}}
|
assign w_asr_result = (|i_b[31:5])? {(34){i_a[31]}}
|
: ( w_ia_input >>> (i_b[4:0]) );// ASR
|
: ( w_ia_input >>> (i_b[4:0]) );// ASR
|
assign w_lsr_result = (|i_b[31:5])? 34'h00
|
assign w_lsr_result = (|i_b[31:5])? 34'h00
|
: { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR
|
: { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR
|
|
|
|
|
|
wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
|
|
wire signed [33:0] w_mpy_result;
|
|
assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
|
|
assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
|
|
assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
|
|
|
wire z, n, v;
|
wire z, n, v;
|
reg c, pre_sign, set_ovfl;
|
reg c, pre_sign, set_ovfl;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_ce)
|
if (i_ce)
|
set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
|
set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
|
| Line 65... |
Line 72... |
pre_sign <= (i_a[31]);
|
pre_sign <= (i_a[31]);
|
c <= 1'b0;
|
c <= 1'b0;
|
casez(i_op)
|
casez(i_op)
|
4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
|
4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
|
4'b?001: o_c <= i_a & i_b; // BTST/And
|
4'b?001: o_c <= i_a & i_b; // BTST/And
|
// 4'h4: o_c <= i_a[15:0] * i_b[15:0];
|
4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S
|
|
4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S
|
4'h5: o_c <= w_rol_result; // ROL
|
4'h5: o_c <= w_rol_result; // ROL
|
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
|
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
|
4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
|
4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
|
4'ha: { c, o_c } <= i_a + i_b; // Add
|
4'ha: { c, o_c } <= i_a + i_b; // Add
|
4'hb: o_c <= i_a | i_b; // Or
|
4'hb: o_c <= i_a | i_b; // Or
|
