///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: cpuops.v
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// Filename: cpuops.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Tecnology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module cpuops(i_clk, i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid);
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module cpuops(i_clk, i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
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o_illegal);
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parameter IMPLEMENT_MPY = 1;
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input i_clk, i_rst, i_ce;
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input i_clk, i_rst, i_ce;
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input [3:0] i_op;
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input [3:0] i_op;
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input [31:0] i_a, i_b;
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input [31:0] i_a, i_b;
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input i_valid;
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input i_valid;
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output reg [31:0] o_c;
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output reg [31:0] o_c;
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output wire [3:0] o_f;
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output wire [3:0] o_f;
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output reg o_valid;
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output reg o_valid;
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output wire o_illegal;
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wire [63:0] w_rol_tmp;
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wire [63:0] w_rol_tmp;
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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wire [31:0] w_rol_result;
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wire [31:0] w_rol_result;
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assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
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assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
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`ifndef NEW_NOT_OLD_CODE
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wire [33:0] w_lsr_result, w_asr_result;
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wire [33:0] w_lsr_result, w_asr_result;
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wire signed [33:0] w_ia_input;
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wire signed [33:0] w_ia_input;
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assign w_ia_input = { i_a[31], i_a, 1'b0 };
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assign w_ia_input = { i_a[31], i_a, 1'b0 };
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assign w_asr_result = (|i_b[31:5])? {(34){i_a[31]}}
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assign w_asr_result = (|i_b[31:5])? {(34){i_a[31]}}
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: ( w_ia_input >>> (i_b[4:0]) );// ASR
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: ( w_ia_input >>> (i_b[4:0]) );// ASR
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assign w_lsr_result = (|i_b[31:5])? 34'h00
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assign w_lsr_result = (|i_b[31:5])? 34'h00
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: { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR
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: { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR
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`else
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wire [32:0] w_lsr_result, w_asr_result;
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assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
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assign w_lsr_result = (|i_b[31:5])? 33'h00
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: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
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`endif
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wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
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wire signed [33:0] w_mpy_result;
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assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
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assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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wire z, n, v;
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wire z, n, v;
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reg c, pre_sign, set_ovfl;
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reg c, pre_sign, set_ovfl;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
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set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
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&&(i_a[31] != i_b[31]))
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&&(i_a[31] != i_b[31]))
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||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
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||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
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||(i_op == 4'hd) // LSL
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||(i_op == 4'hd) // LSL
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||(i_op == 4'hf)); // LSR
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||(i_op == 4'hf)); // LSR
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generate
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if (IMPLEMENT_MPY == 0)
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begin
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always @(posedge i_clk)
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if (i_ce)
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begin
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pre_sign <= (i_a[31]);
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c <= 1'b0;
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casez(i_op)
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4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
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4'b?001: o_c <= i_a & i_b; // BTST/And
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4'h5: o_c <= w_rol_result; // ROL
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4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
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4'ha: { c, o_c } <= i_a + i_b; // Add
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4'hb: o_c <= i_a | i_b; // Or
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4'hc: o_c <= i_a ^ i_b; // Xor
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4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'he: { o_c, c } <= w_asr_result[32:0];// ASR
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4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR
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default: o_c <= i_b; // MOV, LDI
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endcase
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end
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end else begin
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wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
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wire signed [33:0] w_mpy_result;
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assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
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assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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begin
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begin
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pre_sign <= (i_a[31]);
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pre_sign <= (i_a[31]);
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c <= 1'b0;
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c <= 1'b0;
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casez(i_op)
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casez(i_op)
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4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
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4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
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4'b?001: o_c <= i_a & i_b; // BTST/And
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4'b?001: o_c <= i_a & i_b; // BTST/And
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4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S
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4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S
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4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S
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4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S
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4'h5: o_c <= w_rol_result; // ROL
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4'h5: o_c <= w_rol_result; // ROL
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4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
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4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
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4'ha: { c, o_c } <= i_a + i_b; // Add
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4'ha: { c, o_c } <= i_a + i_b; // Add
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4'hb: o_c <= i_a | i_b; // Or
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4'hb: o_c <= i_a | i_b; // Or
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4'hc: o_c <= i_a ^ i_b; // Xor
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4'hc: o_c <= i_a ^ i_b; // Xor
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4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'he: { o_c, c } <= w_asr_result[32:0];// ASR
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4'he: { o_c, c } <= w_asr_result[32:0];// ASR
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4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR
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4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR
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default: o_c <= i_b; // MOV, LDI
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default: o_c <= i_b; // MOV, LDI
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endcase
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endcase
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end
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end
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end endgenerate
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generate
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if (IMPLEMENT_MPY == 0)
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begin
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reg r_illegal;
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always @(posedge i_clk)
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r_illegal <= (i_op == 4'h3)||(i_op == 4'h4);
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assign o_illegal = r_illegal;
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end else
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assign o_illegal = 1'b0;
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endgenerate
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assign z = (o_c == 32'h0000);
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assign z = (o_c == 32'h0000);
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assign n = (o_c[31]);
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assign n = (o_c[31]);
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assign v = (set_ovfl)&&(pre_sign != o_c[31]);
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assign v = (set_ovfl)&&(pre_sign != o_c[31]);
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assign o_f = { v, n, c, z };
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assign o_f = { v, n, c, z };
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initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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else if (i_ce)
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else
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o_valid <= i_valid;
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o_valid <= (i_ce)&&(i_valid);
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else if (~i_ce)
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o_valid <= 1'b0;
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endmodule
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endmodule
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