| Line 31... |
Line 31... |
//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
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module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
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o_illegal);
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o_illegal, o_busy);
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parameter IMPLEMENT_MPY = 1;
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parameter IMPLEMENT_MPY = 1;
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input i_clk, i_rst, i_ce;
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input i_clk, i_rst, i_ce;
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input [3:0] i_op;
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input [3:0] i_op;
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input [31:0] i_a, i_b;
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input [31:0] i_a, i_b;
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input i_valid;
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input i_valid;
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output reg [31:0] o_c;
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output reg [31:0] o_c;
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output wire [3:0] o_f;
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output wire [3:0] o_f;
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output reg o_valid;
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output reg o_valid;
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output wire o_illegal;
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output wire o_illegal;
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output wire o_busy;
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// Rotate-left pre-logic
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// Rotate-left pre-logic
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wire [63:0] w_rol_tmp;
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wire [63:0] w_rol_tmp;
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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wire [31:0] w_rol_result;
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wire [31:0] w_rol_result;
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| Line 119... |
Line 120... |
4'b1101: o_c <= w_popc_result; // POPC
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4'b1101: o_c <= w_popc_result; // POPC
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4'b1110: o_c <= w_rol_result; // ROL
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4'b1110: o_c <= w_rol_result; // ROL
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default: o_c <= i_b; // MOV, LDI
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default: o_c <= i_b; // MOV, LDI
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endcase
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endcase
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end
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end
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assign o_busy = 1'b0;
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reg r_illegal;
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always @(posedge i_clk)
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r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
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assign o_illegal = r_illegal;
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end else begin
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end else begin
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//
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//
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// Multiply pre-logic
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// Multiply pre-logic
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//
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//
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wire signed_mpy;
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wire [16:0] w_mpy_a_input, w_mpy_b_input;
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assign signed_mpy = i_op[0];
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wire [33:0] w_mpy_result;
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wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
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reg [31:0] r_mpy_result;
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wire signed [33:0] w_mpy_result;
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assign w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };
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assign w_mpy_a_input ={ ((i_a[15])&&(signed_mpy)), i_a[15:0] };
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assign w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };
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assign w_mpy_b_input ={ ((i_b[15])&&(signed_mpy)), i_b[15:0] };
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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always @(posedge i_clk)
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if (i_ce)
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r_mpy_result = w_mpy_result[31:0];
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//
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//
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// The master ALU case statement
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// The master ALU case statement
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//
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//
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always @(posedge i_clk)
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always @(posedge i_clk)
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Line 160... |
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'b1010:{c,o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU
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4'b1010: o_c <= r_mpy_result; // MPYU
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4'b1011:{c,o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYS
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4'b1011: o_c <= r_mpy_result; // MPYS
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4'b1100: o_c <= w_brev_result; // BREV
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4'b1100: o_c <= w_brev_result; // BREV
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4'b1101: o_c <= w_popc_result; // POPC
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4'b1101: o_c <= w_popc_result; // POPC
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4'b1110: o_c <= w_rol_result; // ROL
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4'b1110: o_c <= w_rol_result; // ROL
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default: o_c <= i_b; // MOV, LDI
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default: o_c <= i_b; // MOV, LDI
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endcase
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endcase
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end
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end else if (r_busy)
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end endgenerate
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o_c <= r_mpy_result;
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generate
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reg r_busy;
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if (IMPLEMENT_MPY == 0)
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initial r_busy = 1'b0;
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begin
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reg r_illegal;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
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r_busy <= (~i_rst)&&(i_ce)&&(i_valid)
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assign o_illegal = r_illegal;
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&&(i_op[3:1] == 3'h5);
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end else
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assign o_busy = r_busy;
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assign o_illegal = 1'b0;
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assign o_illegal = 1'b0;
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endgenerate
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end endgenerate
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assign z = (o_c == 32'h0000);
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assign z = (o_c == 32'h0000);
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assign n = (o_c[31]);
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assign n = (o_c[31]);
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assign v = (set_ovfl)&&(pre_sign != o_c[31]);
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assign v = (set_ovfl)&&(pre_sign != o_c[31]);
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| Line 183... |
Line 192... |
initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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else
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else
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o_valid <= (i_ce)&&(i_valid);
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o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)
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||(o_busy);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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