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[/] [zipcpu/] [trunk/] [rtl/] [core/] [div.v] - Diff between revs 81 and 88

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Rev 81 Rev 88
Line 55... Line 55...
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                begin
                begin
                        o_busy <= 1'b0;
                        o_busy <= 1'b0;
                        o_valid <= 1'b0;
 
                end else if (i_wr)
                end else if (i_wr)
                begin
                begin
                        o_busy <= 1'b1;
                        o_busy <= 1'b1;
 
                end else if ((o_busy)&&((r_bit == 6'h0)||(o_err)))
 
                        o_busy <= 1'b0;
 
                // else busy is zero and stays at zero
 
 
 
        always @(posedge i_clk)
 
                if ((i_rst)||(i_wr))
                        o_valid <= 1'b0;
                        o_valid <= 1'b0;
                end else if (o_busy)
                else if (o_busy)
                begin
                begin
                        if ((r_bit == 6'h0)||(o_err))
                        if ((r_bit == 6'h0)||(o_err))
                        begin
 
                                o_busy <= 1'b0;
 
                                o_valid <= (o_err)||(~r_sign);
                                o_valid <= (o_err)||(~r_sign);
                        end
 
                end else if (r_sign)
                end else if (r_sign)
                begin
                begin
                        // if (o_err), o_valid is already one.
                        // if (o_err), o_valid is already one.
                        //      if not, o_valid has not yet become one.
                        //      if not, o_valid has not yet become one.
                        o_valid <= (~o_err); // 1'b1;
                        o_valid <= (~o_err); // 1'b1;
                        // r_sign <= 1'b0;
                end else
                end else begin
 
                        o_busy <= 1'b0;
 
                        o_valid <= 1'b0;
                        o_valid <= 1'b0;
                end
 
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if((i_rst)||(o_valid))
                if((i_rst)||(o_valid))
                        o_err <= 1'b0;
                        o_err <= 1'b0;
                else if (o_busy)
                else if (o_busy)

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