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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [rtl/] [core/] [div.v] - Diff between revs 81 and 88
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| Rev 81 |
Rev 88 |
| Line 55... |
Line 55... |
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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o_busy <= 1'b0;
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o_busy <= 1'b0;
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o_valid <= 1'b0;
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end else if (i_wr)
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end else if (i_wr)
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begin
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begin
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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end else if ((o_busy)&&((r_bit == 6'h0)||(o_err)))
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o_busy <= 1'b0;
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// else busy is zero and stays at zero
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always @(posedge i_clk)
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if ((i_rst)||(i_wr))
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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end else if (o_busy)
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else if (o_busy)
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begin
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begin
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if ((r_bit == 6'h0)||(o_err))
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if ((r_bit == 6'h0)||(o_err))
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begin
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o_busy <= 1'b0;
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o_valid <= (o_err)||(~r_sign);
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o_valid <= (o_err)||(~r_sign);
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end
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end else if (r_sign)
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end else if (r_sign)
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begin
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begin
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// if (o_err), o_valid is already one.
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// if (o_err), o_valid is already one.
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// if not, o_valid has not yet become one.
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// if not, o_valid has not yet become one.
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o_valid <= (~o_err); // 1'b1;
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o_valid <= (~o_err); // 1'b1;
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// r_sign <= 1'b0;
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end else
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end else begin
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o_busy <= 1'b0;
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if((i_rst)||(o_valid))
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if((i_rst)||(o_valid))
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o_err <= 1'b0;
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o_err <= 1'b0;
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else if (o_busy)
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else if (o_busy)
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