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[/] [zipcpu/] [trunk/] [rtl/] [core/] [idecode.v] - Diff between revs 160 and 178

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Rev 160 Rev 178
Line 102... Line 102...
        wire            w_dcdA_pc, w_dcdA_cc;
        wire            w_dcdA_pc, w_dcdA_cc;
        wire            w_dcdB_pc, w_dcdB_cc;
        wire            w_dcdB_pc, w_dcdB_cc;
        wire    [3:0]    w_cond;
        wire    [3:0]    w_cond;
        wire            w_wF, w_dcdM, w_dcdDV, w_dcdFP;
        wire            w_wF, w_dcdM, w_dcdDV, w_dcdFP;
        wire            w_wR, w_rA, w_rB, w_wR_n;
        wire            w_wR, w_rA, w_rB, w_wR_n;
        wire            w_ljmp;
        wire            w_ljmp, w_ljmp_dly;
        wire    [31:0]   iword;
        wire    [31:0]   iword;
 
 
 
 
`ifdef  OPT_VLIW
`ifdef  OPT_VLIW
        reg     [16:0]   r_nxt_half;
        reg     [16:0]   r_nxt_half;
Line 146... Line 146...
        // 2 LUTs
        // 2 LUTs
        //
        //
        // If the result register is either CC or PC, and this would otherwise
        // If the result register is either CC or PC, and this would otherwise
        // be a floating point instruction with floating point opcode of 0,
        // be a floating point instruction with floating point opcode of 0,
        // then this is a NOOP.
        // then this is a NOOP.
        assign  w_noop   = (w_op[4:0] == 5'h18)&&(w_dcdR[3:1] == 3'h7);
        assign  w_noop   = (w_op[4:0] == 5'h18)&&(
 
                        ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7))
 
                        ||(IMPLEMENT_FPU==0));
 
 
        // 4 LUTs
        // 4 LUTs
        assign  w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
        assign  w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
                                iword[17:14] };
                                iword[17:14] };
 
 
Line 247... Line 249...
        // when the first instruction half is valid, but not asserted on either
        // when the first instruction half is valid, but not asserted on either
        // a 32-bit instruction or the second half of a 2x16-bit instruction.
        // a 32-bit instruction or the second half of a 2x16-bit instruction.
        reg     r_phase;
        reg     r_phase;
        initial r_phase = 1'b0;
        initial r_phase = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst) // When no instruction is in the pipe, phase is zero
                if ((i_rst) // When no instruction is in the pipe, phase is zero
 
                        ||(o_early_branch)||(w_ljmp_dly))
                        r_phase <= 1'b0;
                        r_phase <= 1'b0;
                else if (i_ce)
                else if ((i_ce)&&(i_pf_valid))
                        r_phase <= (o_phase)? 1'b0:(i_instruction[31]);
                        r_phase <= (o_phase)? 1'b0:(i_instruction[31]);
        // Phase is '1' on the first instruction of a two-part set
        // Phase is '1' on the first instruction of a two-part set
        // But, due to the delay in processing, it's '1' when our output is
        // But, due to the delay in processing, it's '1' when our output is
        // valid for that first part, but that'll be the same time we
        // valid for that first part, but that'll be the same time we
        // are processing the second part ... so it may look to us like a '1'
        // are processing the second part ... so it may look to us like a '1'
Line 274... Line 277...
`ifdef  OPT_VLIW
`ifdef  OPT_VLIW
                        o_illegal <= (i_illegal);
                        o_illegal <= (i_illegal);
`else
`else
                        o_illegal <= ((i_illegal) || (i_instruction[31]));
                        o_illegal <= ((i_illegal) || (i_instruction[31]));
`endif
`endif
                        if ((IMPLEMENT_MPY!=1)&&(w_op[4:1]==4'h5))
                        if ((IMPLEMENT_MPY==0)&&((w_op[4:1]==4'h5)||(w_op[4:0]==5'h08)))
                                o_illegal <= 1'b1;
                                o_illegal <= 1'b1;
 
 
                        if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
                        if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
                                o_illegal <= 1'b1;
                                o_illegal <= 1'b1;
                        else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7))
                        else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7))
Line 356... Line 359...
                        o_ALU  <=  (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); // 2 LUT
                        o_ALU  <=  (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); // 2 LUT
                        o_M    <=  w_dcdM;
                        o_M    <=  w_dcdM;
                        o_DV   <=  w_dcdDV;
                        o_DV   <=  w_dcdDV;
                        o_FP   <=  w_dcdFP;
                        o_FP   <=  w_dcdFP;
 
 
                        o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
                        o_break <= (w_op[4:0]==5'b11001)&&(
 
                                ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
 
                                ||(IMPLEMENT_FPU==0));
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
                        r_lock  <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
                        r_lock  <= (w_op[4:0]==5'b11010)&&(
 
                                ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
 
                                ||(IMPLEMENT_FPU==0));
`endif
`endif
`ifdef  OPT_VLIW
`ifdef  OPT_VLIW
                        r_nxt_half <= { iword[31], iword[13:5],
                        r_nxt_half <= { iword[31], iword[13:5],
                                ((iword[21])? iword[20:19] : 2'h0),
                                ((iword[21])? iword[20:19] : 2'h0),
                                iword[4:0] };
                                iword[4:0] };
Line 424... Line 431...
                                r_branch_pc <= i_pc
                                r_branch_pc <= i_pc
                                        + {{(AW-17){iword[17]}},iword[16:0]}
                                        + {{(AW-17){iword[17]}},iword[16:0]}
                                        + {{(AW-1){1'b0}},1'b1};
                                        + {{(AW-1){1'b0}},1'b1};
                        end
                        end
 
 
 
                assign  w_ljmp_dly         = r_ljmp;
                assign  o_early_branch     = r_early_branch;
                assign  o_early_branch     = r_early_branch;
                assign  o_branch_pc        = r_branch_pc;
                assign  o_branch_pc        = r_branch_pc;
        end else begin
        end else begin
 
                assign  w_ljmp_dly         = 1'b0;
                assign  o_early_branch = 1'b0;
                assign  o_early_branch = 1'b0;
                assign  o_branch_pc = {(AW){1'b0}};
                assign  o_branch_pc = {(AW){1'b0}};
                assign  o_ljmp = 1'b0;
                assign  o_ljmp = 1'b0;
        end endgenerate
        end endgenerate
 
 

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