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[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Diff between revs 2 and 3

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///////////////////////////////////////////////////////////////////////////
 
//
 
// Filename:    memops.v
 
//
 
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
 
//
 
// Purpose:     A memory unit to support a CPU.
 
//
 
//      In the interests of code simplicity, this memory operator is 
 
//      susceptible to unknown results should a new command be sent to it
 
//      before it completes the last one.  Unpredictable results might then
 
//      occurr.
 
//
 
// Creator:     Dan Gisselquist, Ph.D.
 
//              Gisselquist Tecnology, LLC
 
//
 
///////////////////////////////////////////////////////////////////////////
 
//
 
// Copyright (C) 2015, Gisselquist Technology, LLC
 
//
 
// This program is free software (firmware): you can redistribute it and/or
 
// modify it under the terms of  the GNU General Public License as published
 
// by the Free Software Foundation, either version 3 of the License, or (at
 
// your option) any later version.
 
//
 
// This program is distributed in the hope that it will be useful, but WITHOUT
 
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
 
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 
// for more details.
 
//
 
// License:     GPL, v3, as defined and found on www.gnu.org,
 
//              http://www.gnu.org/licenses/gpl.html
 
//
 
//
 
///////////////////////////////////////////////////////////////////////////
 
//
module  memops(i_clk, i_rst, i_stb,
module  memops(i_clk, i_rst, i_stb,
                i_op, i_addr, i_data, i_oreg,
                i_op, i_addr, i_data, i_oreg,
                        o_busy, o_valid, o_wreg, o_result,
                        o_busy, o_valid, o_wreg, o_result,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                i_wb_ack, i_wb_stall, i_wb_data);
                i_wb_ack, i_wb_stall, i_wb_data);
        input                   i_clk, i_rst;
        input                   i_clk, i_rst;
        input                   i_stb;
        input                   i_stb;
        // CPU interface
        // CPU interface
        input                   i_op;
        input                   i_op;
        input           [31:0]   i_addr;
        input           [31:0]   i_addr;
        input           [31:0]   i_data;
        input           [31:0]   i_data;
        input           [4:0]    i_oreg;
        input           [4:0]    i_oreg;
        // CPU outputs
        // CPU outputs
        output  wire            o_busy;
        output  wire            o_busy;
        output  reg             o_valid;
        output  reg             o_valid;
        output  reg     [4:0]    o_wreg;
        output  reg     [4:0]    o_wreg;
        output  reg     [31:0]   o_result;
        output  reg     [31:0]   o_result;
        // Wishbone outputs
        // Wishbone outputs
        output  reg             o_wb_cyc, o_wb_stb, o_wb_we;
        output  reg             o_wb_cyc, o_wb_stb, o_wb_we;
        output  reg     [31:0]   o_wb_addr, o_wb_data;
        output  reg     [31:0]   o_wb_addr, o_wb_data;
        // Wishbone inputs
        // Wishbone inputs
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        o_wb_cyc <= 1'b0;
                        o_wb_cyc <= 1'b0;
                else if (o_wb_cyc)
                else if (o_wb_cyc)
                begin
 
                        o_wb_stb <= (o_wb_stb)&&(i_wb_stall);
 
                        o_wb_cyc <= (~i_wb_ack);
                        o_wb_cyc <= (~i_wb_ack);
                end else if (i_stb) // New memory operation
                else if (i_stb) // New memory operation
                begin
 
                        // Grab the wishbone
                        // Grab the wishbone
                        o_wb_cyc  <= 1'b1;
                        o_wb_cyc  <= 1'b1;
                        o_wb_stb  <= 1'b1;
        always @(posedge i_clk)
 
                if (o_wb_cyc)
 
                        o_wb_stb <= (o_wb_stb)&&(i_wb_stall);
 
                else
 
                        o_wb_stb  <= i_stb; // Grab wishbone on new operation
 
        always @(posedge i_clk)
 
                if (i_stb)
 
                begin
                        o_wb_we   <= i_op;
                        o_wb_we   <= i_op;
                        o_wb_data <= i_data;
                        o_wb_data <= i_data;
                        o_wb_addr <= i_addr;
                        o_wb_addr <= i_addr;
                end
                end
 
 
        initial o_valid = 1'b0;
        initial o_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_valid <= (o_wb_cyc)&&(i_wb_ack)&&(~o_wb_we)&&(~i_rst);
                o_valid <= (o_wb_cyc)&&(i_wb_ack)&&(~o_wb_we);
        assign  o_busy = o_wb_cyc;
        assign  o_busy = o_wb_cyc;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_stb)&&(~o_wb_cyc))
                if (i_stb)
                        o_wreg    <= i_oreg;
                        o_wreg    <= i_oreg;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                if (i_wb_ack)
                        o_result <= i_wb_data;
                        o_result <= i_wb_data;
endmodule
endmodule
 
 

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