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//

//      This logic is driven by a couple realities:

//      1. It takes a clock to read from a block RAM address, and hence a clock

//              to read from the cache.

//      2. It takes another clock to check that the tag matches

//

//              Our goal will be to avoid this second check if at all possible.

//              Hence, we'll test on the clock of any given request whether

//              or not the request matches the last tag value, and on the next

//              clock whether it new tag value (if it has changed).  Hence,

//              for anything found within the cache, there will be a one

//              cycle delay on any branch.

//

//

//      Address Words are separated into three components:

//      [ Tag bits ] [ Cache line number ] [ Cache position w/in the line ]

//

//      On any read from the cache, only the second two components are required.

//      On any read from memory, the first two components will be fixed across

//      the bus, and the third component will be adjusted from zero to its

//      maximum value.

//

//

module  pfcache(i_clk, i_reset, i_new_pc, i_clear_cache,

`ifdef  FORMAL

                , f_pc_wb

`endif

                );

`ifdef  FORMAL

        parameter       LGCACHELEN = 4, ADDRESS_WIDTH=30,

                        LGLINES=2; // Log of the number of separate cache lines

`else

        parameter       LGCACHELEN = 12, ADDRESS_WIDTH=30,

                        LGLINES=6; // Log of the number of separate cache lines

`endif

        localparam      CACHELEN=(1<<LGCACHELEN); //Wrd Size of our cache memory

        input   wire                    i_clk, i_reset;

        //

        // The interface with the rest of the CPU

        input   wire                    i_new_pc;

        input   wire                    i_clear_cache;

        input   wire                    i_stall_n;

        input   wire    [(AW+1):0]       i_pc;

        output  wire    [(BUSW-1):0]     o_insn;

        output  wire    [(AW+1):0]       o_pc;

        output  wire                    o_valid;

        //

        // The wishbone bus interface

        // o_illegal will be true if this instruction was the result of a

        // bus error (This is also part of the CPU interface)

        //

`ifdef  NOT_YET_READY

        input   wire                    i_mmu_ack, i_mmu_we;

        input   wire    [(PAW-1):0]      i_mmu_paddr;

`endif

`ifdef  NOT_YET_READY

        // These wires will be used below as part of the cache invalidation

        // routine, should the MMU be used.  This allows us to snoop on the

        // physical side of the MMU bus, and invalidate any results should

        // we need to do so.

        wire                    mmu_inval;

        wire    [(PAW-CW-1):0]   mmu_mskaddr;

`endif

`ifdef  FORMAL

        output  wire    [AW-1:0] f_pc_wb;

        assign  f_pc_wb = i_pc[AW+1:2];

`endif

        wire                    w_v_from_pc, w_v_from_last;

        reg     [(AW+1):0]       lastpc;

        reg     [(CW-1):0]       wraddr;

        reg     [1:0]            delay;

        reg                     svmask, last_ack, needload, last_addr,

                                bus_abort;

        reg     [(LGLINES-1):0]  saddr;

        wire                    w_advance;

        assign  w_advance = (i_new_pc)||((r_v)&&(i_stall_n));

        /////////////////////////////////////////////////

        //

        // Read the instruction from the cache

        //

        /////////////////////////////////////////////////

        //

        //

        // We'll read two values from the cache, the first is the value if

        // i_pc contains the address we want, the second is the value we'd read

        // if lastpc (i.e. $past(i_pc)) was the address we wanted.

        initial r_pc = 0;

        initial r_lastpc = 0;

                // and the CPU wasn't stalled, then we want to use i_pc.

                // Likewise if the CPU gave us an i_new_pc request, then we'll

                // want to return the value associated with reading the cache

                // at i_pc.

                isrc <= w_advance;

                // Here we read both cache entries, at i_pc and lastpc.

                // We'll select from among these cache possibilities on the

                // next clock

                r_pc_cache <= cache[i_pc[(CW+1):2]];

                r_last_cache <= cache[lastpc[(CW+1):2]];

                //

                // Let's also register(delay) the r_pc and r_lastpc values

                // for the next clock, so we can accurately report the address

                // of the cache value we just looked up.

        // On our next clock, our result with either be the registered i_pc

        // value from the last clock (if isrc), otherwise r_lastpc

        // will be.  We just read it in the last clock, now we just need to

        // select between the two possibilities we just read.

        assign  o_insn= (isrc) ? r_pc_cache : r_last_cache;

        //

        // Read the tag value associated with this i_pc value

        //

        // Read the tag value associated with the lastpc value, from what

        // i_pc was when we could not tell if this value was in our cache or

        // not, or perhaps from when we determined that i was not in the cache.

        // Select from between these two values on the next clock

        assign  tagval = (isrc)?tagvalipc : tagvallst;

        //

        // Use the tag value to determine if our output instruction will be

        // valid.

        //

        /////////////////////////////////////////////////

        //

        //

        assign  w_v_from_pc = ((i_pc[(AW+1):LS+2] == lasttag)

                                &&(tagval == i_pc[(AW+1):CW+2])

                                &&(valid_mask[i_pc[(CW+1):LS+2]]));

        assign  w_v_from_last = ((tagval == lastpc[(AW+1):CW+2])

                                &&(valid_mask[lastpc[(CW+1):LS+2]]));

                // Delay at least two clocks before declaring that

                // we have an invalid result.  This will give us time

                // to check the tag value of what's in the cache.

                // i_pc clock, then we are sourcing it from the

                // lastpc clock (one clock later).  If r_v still

                // isn't valid, we may need to make a bus request.

                // Apply our timer and timeout.

                // Delay is two once the bus starts, in case the

                // bus transaction needs to be restarted upon completion

                // This might happen if, after we start loading the

                // cache, we discover a branch.  The cache load will

                // still complete, but the branches address needs to be

                // the onen we jump to.  This may mean we need to load

                // the cache twice.

        end else begin

                // After sourcing our output from i_pc, if it wasn't

                // accepted, source the instruction from the lastpc valid

                // determination instead

                rvsrc <= 1'b0;

                if (o_illegal)

                        delay <= 2'h2;

        initial r_new_request = 0;

        initial r_v_from_pc = 0;

        initial r_v_from_last = 0;

                                        &&(!o_illegal);

                r_v_from_last <= (w_v_from_last)&&(!w_invalidate_result);

                r_prior_illegal <= (o_wb_cyc)&&(i_wb_err);

        end

        // Now use rvsrc to determine which of the two valid flags we'll be

        // using: r_v_from_pc (the i_pc address), or r_v_from_last (the lastpc

        // address)

        assign  r_v = ((rvsrc)?(r_v_from_pc):(r_v_from_last))&&(!r_new_request);

        assign  o_valid = (((rvsrc)?(r_v_from_pc):(r_v_from_last))

                        ||(o_illegal))

                        &&(!i_new_pc)&&(!r_prior_illegal);

        //

        // If the instruction isn't in our cache, then we need to load

        // a new cache line from memory.

        //

        /////////////////////////////////////////////////

        //

        //

                needload <= (delay==0)&&(!w_v_from_last)

                        // Prevent us from reloading an illegal address

                        // (i.e. one that produced a bus error) over and over

                        // and over again

                        &&((!illegal_valid)

                                ||(lastpc[(AW+1):LS+2] != illegal_cache));

        // Working from the rule that you want to keep complex logic out of

        // a state machine if possible, we calculate a "last_stb" value one

        // clock ahead of time.  Hence, any time a request is accepted, if

        // last_stb is also true we'll know we need to drop the strobe line,

        // having finished requesting a complete cache  line.

        else if ((o_wb_addr[(LS-1):1] == {(LS-1){1'b1}})

                        &&((!i_wb_stall)|(o_wb_addr[0])))

                last_addr <= 1'b1;

        //

        // "last_ack" is almost identical to last_addr, save that this

        // will be true on the same clock as the last acknowledgment from the

        // bus.  The state machine logic will use this to determine when to

        // get off the bus and end the wishbone bus cycle.

        initial last_ack = 1'b0;

        always @(posedge i_clk)

                last_ack <= (o_wb_cyc)&&(

                                (wraddr[(LS-1):1]=={(LS-1){1'b1}})

                                &&((wraddr[0])||(i_wb_ack)));

        initial bus_abort = 1'b0;

        always @(posedge i_clk)

        if (!o_wb_cyc)

                bus_abort <= 1'b0;

        else if ((i_clear_cache)||(i_new_pc))

                bus_abort <= 1'b1;

        //

        // Here's the difficult piece of state machine logic--the part that

        // determines o_wb_cyc and o_wb_stb.  We've already moved most of the

        // complicated logic off of this statemachine, calculating it one cycle

        // early.  As a result, this is a fairly easy piece of logic.

        // is active, and needs to be incremented any time an address is

        // accepted--WITH THE EXCEPTION OF THE LAST ADDRESS.  We need to keep

        // this steady for that last address, unless the last address returns

        // a bus error.  In that case, the whole cache line will be marked as

        // invalid--but we'll need the value of this register to know how

        // to do that propertly.

        initial o_wb_addr = {(AW){1'b0}};

        always @(posedge i_clk)

        if ((o_wb_stb)&&(!i_wb_stall)&&(!last_addr))

                o_wb_addr[(LS-1):0] <= o_wb_addr[(LS-1):0]+1'b1;

        else if (!o_wb_cyc)

                o_wb_addr <= { lastpc[(AW+1):LS+2], {(LS){1'b0}} };

        // Since it is impossible to initialize an array, our cache will start

        // up cache uninitialized.  We'll also never get a valid ack without

        // cyc being active, although we might get one on the clock after

        // cyc was active--so we need to test and gate on whether o_wb_cyc

        // is true.

        //

        // wraddr will advance forward on every clock cycle where ack is true,

        // hence we don't need to check i_wb_ack here.  This will work because

        // multiple writes to the same address, ending with a valid write,

        // will always yield the valid write's value only after our bus cycle

        // is over.

`ifdef  NOT_YET_READY

                //

                // MMU code

                //

                if (mmu_inval)

                        valid_mask[mmu_mskadr] <= 1'b0;

`endif

        // MMU code

        //

        //

`ifdef  NOT_YET_READY

        parameter       [0:0]     USE_MMU = 1'b1;

        generate if (USE_MMU)

        begin

                reg     [(PAW-CW-1):0]   ptag    [0:((1<<(LGLINES))-1)];

                reg                     mmu_pre_inval, r_mmu_inval;

                reg     [(PAW-CW-1):0]   mmu_pre_tag, mmu_pre_padr;

                reg     [(CW-LS-1):0]    r_mmu_mskadr;

                initial mmu_pre_inval   = 0;

                initial mmu_pre_tag     = 0;

                initial mmu_pre_padr    = 0;

                initial mmu_pre2_inval  = 0;

                initial mmu_pre2_mskadr = 0;

                always @(posedge i_clk)

                if ((o_wb_cyc)&&(!last_addr)&&(i_mmu_ack))

                        ptag[i_mmu_paddr[(CW-1):LS]] <= i_mmu_paddr[(PAW-1):CW];

                always @(posedge i_clk)

                if (i_reset)

                begin