OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [pfcache.v] - Diff between revs 88 and 118

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 88 Rev 118
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    pfcache.v
// Filename:    pfcache.v
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
// Purpose:     Keeping our CPU fed with instructions, at one per clock and
// Purpose:     Keeping our CPU fed with instructions, at one per clock and
//              with no stalls.  An unusual feature of this cache is the
//              with no stalls.  An unusual feature of this cache is the
//      requirement that the entire cache may be cleared (if necessary).
//      requirement that the entire cache may be cleared (if necessary).
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
//
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
module  pfcache(i_clk, i_rst, i_new_pc, i_clear_cache,
module  pfcache(i_clk, i_rst, i_new_pc, i_clear_cache,
                        // i_early_branch, i_from_addr,
                        // i_early_branch, i_from_addr,
                        i_stall_n, i_pc, o_i, o_pc, o_v,
                        i_stall_n, i_pc, o_i, o_pc, o_v,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
                        o_illegal);
                        o_illegal);
        parameter       LGCACHELEN = 8, ADDRESS_WIDTH=24,
        parameter       LGCACHELEN = 8, ADDRESS_WIDTH=24,
                        CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH,
                        CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH,
                        CW=LGCACHELEN, PW=LGCACHELEN-5;
                        CW=LGCACHELEN, PW=LGCACHELEN-5;
        input                           i_clk, i_rst, i_new_pc;
        input                           i_clk, i_rst, i_new_pc;
        input                           i_clear_cache;
        input                           i_clear_cache;
        input                           i_stall_n;
        input                           i_stall_n;
        input           [(AW-1):0]       i_pc;
        input           [(AW-1):0]       i_pc;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(AW-1):0]       o_pc;
        output  reg     [(AW-1):0]       o_pc;
        output  wire                    o_v;
        output  wire                    o_v;
        //
        //
        output  reg             o_wb_cyc, o_wb_stb;
        output  reg             o_wb_cyc, o_wb_stb;
        output  wire            o_wb_we;
        output  wire            o_wb_we;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  wire    [(BUSW-1):0]     o_wb_data;
        output  wire    [(BUSW-1):0]     o_wb_data;
        //
        //
        input                           i_wb_ack, i_wb_stall, i_wb_err;
        input                           i_wb_ack, i_wb_stall, i_wb_err;
        input           [(BUSW-1):0]     i_wb_data;
        input           [(BUSW-1):0]     i_wb_data;
        //
        //
        output  reg                     o_illegal;
        output  reg                     o_illegal;
 
 
        // Fixed bus outputs: we read from the bus only, never write.
        // Fixed bus outputs: we read from the bus only, never write.
        // Thus the output data is ... irrelevant and don't care.  We set it
        // Thus the output data is ... irrelevant and don't care.  We set it
        // to zero just to set it to something.
        // to zero just to set it to something.
        assign  o_wb_we = 1'b0;
        assign  o_wb_we = 1'b0;
        assign  o_wb_data = 0;
        assign  o_wb_data = 0;
 
 
        reg                     r_v;
        reg                     r_v;
        (* ram_style = "distributed" *)
        (* ram_style = "distributed" *)
        reg     [(BUSW-1):0]     cache   [0:((1<<CW)-1)];
        reg     [(BUSW-1):0]     cache   [0:((1<<CW)-1)];
        reg     [(AW-CW-1):0]    tags    [0:((1<<(CW-PW))-1)];
        reg     [(AW-CW-1):0]    tags    [0:((1<<(CW-PW))-1)];
        reg     [((1<<(CW-PW))-1):0]     vmask;
        reg     [((1<<(CW-PW))-1):0]     vmask;
 
 
        reg     [(AW-1):0]       lastpc;
        reg     [(AW-1):0]       lastpc;
        reg     [(CW-1):0]       rdaddr;
        reg     [(CW-1):0]       rdaddr;
        reg     [(AW-1):CW]     tagval;
        reg     [(AW-1):CW]     tagval;
        wire    [(AW-1):PW]     lasttag;
        wire    [(AW-1):PW]     lasttag;
        reg     [(AW-1):PW]     illegal_cache;
        reg     [(AW-1):PW]     illegal_cache;
 
 
        initial o_i = 32'h76_00_00_00;  // A NOOP instruction
        initial o_i = 32'h76_00_00_00;  // A NOOP instruction
        initial o_pc = 0;
        initial o_pc = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (~r_v)
                if (~r_v)
                begin
                begin
                        o_i <= cache[lastpc[(CW-1):0]];
                        o_i <= cache[lastpc[(CW-1):0]];
                        o_pc <= lastpc;
                        o_pc <= lastpc;
                end else if ((i_stall_n)||(i_new_pc))
                end else if ((i_stall_n)||(i_new_pc))
                begin
                begin
                        o_i <= cache[i_pc[(CW-1):0]];
                        o_i <= cache[i_pc[(CW-1):0]];
                        o_pc <= i_pc;
                        o_pc <= i_pc;
                end
                end
 
 
        initial tagval = 0;
        initial tagval = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if((o_wb_cyc)&&(rdaddr[(PW-1):0]=={(PW){1'b1}})
                // It may be possible to recover a clock once the cache line
                                &&(i_wb_ack)&&(~i_wb_err))
                // has been filled, but our prior attempt to do so has lead
                        // Our tag value changes any time we finish reading a
                // to a race condition, so we keep this logic simple.
                        // new cache line
                if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
                        tagval <= o_wb_addr[(AW-1):CW];
                        lastpc <= tags[i_pc[(CW-1):PW]];
                else if ((i_stall_n)&&(~o_wb_cyc))
                else
                        // Otherwise, as long as we're not reading new stuff,
                        tagval <= tags[lastpc[(CW-1):PW]];
                        // the tag line changes any time the pipeline steps
 
                        // forwards.  Our purpose here is primarily just to 
 
                        // catch sudden changes.  The result is that walking
 
                        // from one cache line to the next will cost a clock.
 
                        tagval <= tags[i_pc[(CW-1):PW]];
 
 
 
        // i_pc will only increment when everything else isn't stalled, thus
        // i_pc will only increment when everything else isn't stalled, thus
        // we can set it without worrying about that.   Doing this enables
        // we can set it without worrying about that.   Doing this enables
        // us to work in spite of stalls.  For example, if the next address
        // us to work in spite of stalls.  For example, if the next address
        // isn't valid, but the decoder is stalled, get the next address
        // isn't valid, but the decoder is stalled, get the next address
        // anyway.
        // anyway.
        initial lastpc = 0;
        initial lastpc = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
                if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
                        lastpc <= i_pc;
                        lastpc <= i_pc;
 
 
        assign  lasttag = lastpc[(AW-1):PW];
        assign  lasttag = lastpc[(AW-1):PW];
        // initial      lasttag = 0;
        // initial      lasttag = 0;
        // always @(posedge i_clk)
        // always @(posedge i_clk)
                // if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
                // if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
                        // lasttag <= i_pc[(AW-1):PW];
                        // lasttag <= i_pc[(AW-1):PW];
 
 
        wire    r_v_from_pc, r_v_from_last;
        wire    r_v_from_pc, r_v_from_last;
        assign  r_v_from_pc = ((i_pc[(AW-1):PW] == lasttag)
        assign  r_v_from_pc = ((i_pc[(AW-1):PW] == lasttag)
                                &&(tagval == i_pc[(AW-1):CW])
                                &&(tagval == i_pc[(AW-1):CW])
                                &&(vmask[i_pc[(CW-1):PW]]));
                                &&(vmask[i_pc[(CW-1):PW]]));
        assign  r_v_from_last = (
        assign  r_v_from_last = (
                                //(lastpc[(AW-1):PW] == lasttag)&&
                                //(lastpc[(AW-1):PW] == lasttag)&&
                                (tagval == lastpc[(AW-1):CW])
                                (tagval == lastpc[(AW-1):CW])
                                &&(vmask[lastpc[(CW-1):PW]]));
                                &&(vmask[lastpc[(CW-1):PW]]));
 
 
        reg     [1:0]    delay;
        reg     [1:0]    delay;
 
 
        initial delay = 2'h3;
        initial delay = 2'h3;
        initial r_v = 1'b0;
        initial r_v = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache)||(i_new_pc)||((r_v)&&(i_stall_n)))
                if ((i_rst)||(i_clear_cache)||(i_new_pc)||((r_v)&&(i_stall_n)))
                begin
                begin
                        r_v <= r_v_from_pc;
                        r_v <= r_v_from_pc;
                        delay <= 2'h2;
                        delay <= 2'h2;
                end else if (~r_v) begin // Otherwise, r_v was true and we were
                end else if (~r_v) begin // Otherwise, r_v was true and we were
                        r_v <= r_v_from_last;   // stalled, hence only if ~r_v
                        r_v <= r_v_from_last;   // stalled, hence only if ~r_v
                        if (o_wb_cyc)
                        if (o_wb_cyc)
                                delay <= 2'h2;
                                delay <= 2'h2;
                        else if (delay != 0)
                        else if (delay != 0)
                                delay <= delay + 2'b11; // i.e. delay -= 1;
                                delay <= delay + 2'b11; // i.e. delay -= 1;
                end
                end
 
 
        assign  o_v = (r_v)&&(~i_new_pc);
        assign  o_v = (r_v)&&(~i_new_pc);
 
 
 
 
        initial o_wb_cyc  = 1'b0;
        initial o_wb_cyc  = 1'b0;
        initial o_wb_stb  = 1'b0;
        initial o_wb_stb  = 1'b0;
        initial o_wb_addr = {(AW){1'b0}};
        initial o_wb_addr = {(AW){1'b0}};
        initial rdaddr    = 0;
        initial rdaddr    = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                if ((i_rst)||(i_clear_cache))
                begin
                begin
                        o_wb_cyc <= 1'b0;
                        o_wb_cyc <= 1'b0;
                        o_wb_stb <= 1'b0;
                        o_wb_stb <= 1'b0;
                end else if (o_wb_cyc)
                end else if (o_wb_cyc)
                begin
                begin
                        if ((o_wb_stb)&&(~i_wb_stall))
                        if ((o_wb_stb)&&(~i_wb_stall))
                        begin
                        begin
                                if (o_wb_addr[(PW-1):0] == {(PW){1'b1}})
                                if (o_wb_addr[(PW-1):0] == {(PW){1'b1}})
                                        o_wb_stb <= 1'b0;
                                        o_wb_stb <= 1'b0;
                                else
                                else
                                        o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
                                        o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
                        end
                        end
 
 
                        if (i_wb_ack)
                        if (i_wb_ack)
                        begin
                        begin
                                rdaddr <= rdaddr + 1;
                                rdaddr <= rdaddr + 1;
                                if (rdaddr[(PW-1):0] == {(PW){1'b1}})
                                if (rdaddr[(PW-1):0] == {(PW){1'b1}})
                                        tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
                                        tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
                        end
                        end
 
 
                        if (((i_wb_ack)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}))||(i_wb_err))
                        if (((i_wb_ack)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}))||(i_wb_err))
                                o_wb_cyc <= 1'b0;
                                o_wb_cyc <= 1'b0;
 
 
                        // else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
                        // else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
                        //      tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
                        //      tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
 
 
                end else if ((~r_v)&&(delay==0)
                end else if ((~r_v)&&(delay==0)
                        &&((tagval != lastpc[(AW-1):CW])
                        &&((tagval != lastpc[(AW-1):CW])
                                ||(~vmask[lastpc[(CW-1):PW]]))
                                ||(~vmask[lastpc[(CW-1):PW]]))
                        &&(~o_illegal))
                        &&(~o_illegal))
                begin
                begin
                        o_wb_cyc  <= 1'b1;
                        o_wb_cyc  <= 1'b1;
                        o_wb_stb  <= 1'b1;
                        o_wb_stb  <= 1'b1;
                        o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
                        o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
                        rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
                        rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
                end
                end
 
 
        // Can't initialize an array, so leave cache uninitialized
        // Can't initialize an array, so leave cache uninitialized
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                if ((o_wb_cyc)&&(i_wb_ack))
                        cache[rdaddr] <= i_wb_data;
                        cache[rdaddr] <= i_wb_data;
 
 
        // VMask ... is a section loaded?
        // VMask ... is a section loaded?
        initial vmask = 0;
        initial vmask = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                if ((i_rst)||(i_clear_cache))
                        vmask <= 0;
                        vmask <= 0;
                else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
                else begin
                        vmask[lastpc[(CW-1):PW]] <= 1'b0;
                        if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
                else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
 
                        vmask[rdaddr[(CW-1):PW]] <= 1'b1;
                        vmask[rdaddr[(CW-1):PW]] <= 1'b1;
 
                        if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
 
                                vmask[lastpc[(CW-1):PW]] <= 1'b0;
 
                end
 
 
        reg     illegal_valid;
        reg     illegal_valid;
        initial illegal_cache = 0;
        initial illegal_cache = 0;
        initial illegal_valid = 0;
        initial illegal_valid = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                if ((i_rst)||(i_clear_cache))
                begin
                begin
                        illegal_cache <= 0;
                        illegal_cache <= 0;
                        illegal_valid <= 0;
                        illegal_valid <= 0;
                end else if ((o_wb_cyc)&&(i_wb_err))
                end else if ((o_wb_cyc)&&(i_wb_err))
                begin
                begin
                        illegal_cache <= lastpc[(AW-1):PW];
                        illegal_cache <= lastpc[(AW-1):PW];
                        illegal_valid <= 1'b1;
                        illegal_valid <= 1'b1;
                end
                end
 
 
        initial o_illegal = 1'b0;
        initial o_illegal = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                if ((i_rst)||(i_clear_cache))
                        o_illegal <= 1'b0;
                        o_illegal <= 1'b0;
                else
                else
                        o_illegal <= (illegal_valid)
                        o_illegal <= (illegal_valid)
                                &&(tagval == i_pc[(AW-1):CW])
                                &&(tagval == i_pc[(AW-1):CW])
                                &&(illegal_cache == i_pc[(AW-1):PW]);
                                &&(illegal_cache == i_pc[(AW-1):PW]);
 
 
endmodule
endmodule
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.