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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pfcache.v] - Diff between revs 176 and 194

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Rev 176 Rev 194
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// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
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                        i_stall_n, i_pc, o_i, o_pc, o_v,
                        i_stall_n, i_pc, o_i, o_pc, o_v,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
                        o_illegal);
                        o_illegal);
        parameter       LGCACHELEN = 8, ADDRESS_WIDTH=24,
        parameter       LGCACHELEN = 8, ADDRESS_WIDTH=24,
                        CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH,
                        LGLINES=5; // Log of the number of separate cache lines
                        CW=LGCACHELEN, PW=LGCACHELEN-5;
        localparam      CACHELEN=(1<<LGCACHELEN); // Size of our cache memory
 
        localparam      CW=LGCACHELEN;  // Short hand for LGCACHELEN
 
        localparam      PW=LGCACHELEN-LGLINES; // Size of a cache line
 
        localparam      BUSW = 32;      // Number of data lines on the bus
 
        localparam      AW=ADDRESS_WIDTH; // Shorthand for ADDRESS_WIDTH
        input                           i_clk, i_rst, i_new_pc;
        input                           i_clk, i_rst, i_new_pc;
        input                           i_clear_cache;
        input                           i_clear_cache;
        input                           i_stall_n;
        input                           i_stall_n;
        input           [(AW-1):0]       i_pc;
        input           [(AW-1):0]       i_pc;
        output  wire    [(BUSW-1):0]     o_i;
        output  wire    [(BUSW-1):0]     o_i;
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        assign  o_wb_we = 1'b0;
        assign  o_wb_we = 1'b0;
        assign  o_wb_data = 0;
        assign  o_wb_data = 0;
 
 
        wire                    r_v;
        wire                    r_v;
        reg     [(BUSW-1):0]     cache   [0:((1<<CW)-1)];
        reg     [(BUSW-1):0]     cache   [0:((1<<CW)-1)];
        reg     [(AW-CW-1):0]    tags    [0:((1<<(CW-PW))-1)];
        reg     [(AW-CW-1):0]    tags    [0:((1<<(LGLINES))-1)];
        reg     [((1<<(CW-PW))-1):0]     vmask;
        reg     [((1<<(LGLINES))-1):0]   vmask;
 
 
        reg     [(AW-1):0]       lastpc;
        reg     [(AW-1):0]       lastpc;
        reg     [(CW-1):0]       rdaddr;
        reg     [(CW-1):0]       rdaddr;
        reg     [(AW-1):CW]     tagvalipc, tagvallst;
        reg     [(AW-1):CW]     tagvalipc, tagvallst;
        wire    [(AW-1):CW]     tagval;
        wire    [(AW-1):CW]     tagval;
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        // cache line would get read, and the instruction would read from the
        // cache line would get read, and the instruction would read from the
        // last cache line.
        // last cache line.
        reg     svmask;
        reg     svmask;
        initial vmask = 0;
        initial vmask = 0;
        initial svmask = 1'b0;
        initial svmask = 1'b0;
        reg     [(CW-PW-1):0]    saddr;
        reg     [(LGLINES-1):0]  saddr;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                if ((i_rst)||(i_clear_cache))
                begin
                begin
                        vmask <= 0;
                        vmask <= 0;
                        svmask<= 1'b0;
                        svmask<= 1'b0;

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