////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: pfcache.v
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// Filename: pfcache.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: Keeping our CPU fed with instructions, at one per clock and
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// Purpose: Keeping our CPU fed with instructions, at one per clock and
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// with no stalls. An unusual feature of this cache is the
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// with no stalls. An unusual feature of this cache is the
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// requirement that the entire cache may be cleared (if necessary).
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// requirement that the entire cache may be cleared (if necessary).
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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module pfcache(i_clk, i_rst, i_new_pc, i_clear_cache,
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module pfcache(i_clk, i_rst, i_new_pc, i_clear_cache,
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// i_early_branch, i_from_addr,
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// i_early_branch, i_from_addr,
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i_stall_n, i_pc, o_i, o_pc, o_v,
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i_stall_n, i_pc, o_i, o_pc, o_v,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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o_illegal);
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o_illegal);
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parameter LGCACHELEN = 8, ADDRESS_WIDTH=24,
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parameter LGCACHELEN = 8, ADDRESS_WIDTH=24,
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LGLINES=5; // Log of the number of separate cache lines
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LGLINES=5; // Log of the number of separate cache lines
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localparam CACHELEN=(1<<LGCACHELEN); // Size of our cache memory
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localparam CACHELEN=(1<<LGCACHELEN); // Size of our cache memory
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localparam CW=LGCACHELEN; // Short hand for LGCACHELEN
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localparam CW=LGCACHELEN; // Short hand for LGCACHELEN
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localparam PW=LGCACHELEN-LGLINES; // Size of a cache line
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localparam PW=LGCACHELEN-LGLINES; // Size of a cache line
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localparam BUSW = 32; // Number of data lines on the bus
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localparam BUSW = 32; // Number of data lines on the bus
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localparam AW=ADDRESS_WIDTH; // Shorthand for ADDRESS_WIDTH
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localparam AW=ADDRESS_WIDTH; // Shorthand for ADDRESS_WIDTH
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input i_clk, i_rst, i_new_pc;
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input i_clk, i_rst, i_new_pc;
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input i_clear_cache;
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input i_clear_cache;
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input i_stall_n;
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input i_stall_n;
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input [(AW-1):0] i_pc;
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input [(AW-1):0] i_pc;
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output wire [(BUSW-1):0] o_i;
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output wire [(BUSW-1):0] o_i;
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output wire [(AW-1):0] o_pc;
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output wire [(AW-1):0] o_pc;
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output wire o_v;
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output wire o_v;
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//
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//
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output reg o_wb_cyc, o_wb_stb;
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output reg o_wb_cyc, o_wb_stb;
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output wire o_wb_we;
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output wire o_wb_we;
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output reg [(AW-1):0] o_wb_addr;
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output reg [(AW-1):0] o_wb_addr;
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output wire [(BUSW-1):0] o_wb_data;
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output wire [(BUSW-1):0] o_wb_data;
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//
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//
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input i_wb_ack, i_wb_stall, i_wb_err;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [(BUSW-1):0] i_wb_data;
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input [(BUSW-1):0] i_wb_data;
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//
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//
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output reg o_illegal;
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output reg o_illegal;
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// Fixed bus outputs: we read from the bus only, never write.
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// Fixed bus outputs: we read from the bus only, never write.
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// Thus the output data is ... irrelevant and don't care. We set it
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// Thus the output data is ... irrelevant and don't care. We set it
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// to zero just to set it to something.
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// to zero just to set it to something.
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assign o_wb_we = 1'b0;
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assign o_wb_we = 1'b0;
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assign o_wb_data = 0;
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assign o_wb_data = 0;
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wire r_v;
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wire r_v;
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reg [(BUSW-1):0] cache [0:((1<<CW)-1)];
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reg [(BUSW-1):0] cache [0:((1<<CW)-1)];
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reg [(AW-CW-1):0] tags [0:((1<<(LGLINES))-1)];
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reg [(AW-CW-1):0] tags [0:((1<<(LGLINES))-1)];
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reg [((1<<(LGLINES))-1):0] vmask;
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reg [((1<<(LGLINES))-1):0] vmask;
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reg [(AW-1):0] lastpc;
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reg [(AW-1):0] lastpc;
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reg [(CW-1):0] rdaddr;
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reg [(CW-1):0] rdaddr;
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reg [(AW-1):CW] tagvalipc, tagvallst;
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reg [(AW-1):CW] tagvalipc, tagvallst;
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wire [(AW-1):CW] tagval;
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wire [(AW-1):CW] tagval;
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wire [(AW-1):PW] lasttag;
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wire [(AW-1):PW] lasttag;
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reg illegal_valid;
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reg illegal_valid;
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reg [(AW-1):PW] illegal_cache;
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reg [(AW-1):PW] illegal_cache;
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// initial o_i = 32'h76_00_00_00; // A NOOP instruction
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// initial o_i = 32'h76_00_00_00; // A NOOP instruction
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// initial o_pc = 0;
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// initial o_pc = 0;
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reg [(BUSW-1):0] r_pc_cache, r_last_cache;
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reg [(BUSW-1):0] r_pc_cache, r_last_cache;
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reg [(AW-1):0] r_pc, r_lastpc;
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reg [(AW-1):0] r_pc, r_lastpc;
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reg isrc;
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reg isrc;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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// We don't have the logic to select what to read, we must
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// We don't have the logic to select what to read, we must
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// read both the value at i_pc and lastpc. cache[i_pc] is
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// read both the value at i_pc and lastpc. cache[i_pc] is
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// the value we return if the cache is good, cacne[lastpc] is
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// the value we return if the cache is good, cacne[lastpc] is
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// the value we return if we've been stalled, weren't valid,
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// the value we return if we've been stalled, weren't valid,
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// or had to wait a clock or two. (Remember i_pc can't stop
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// or had to wait a clock or two. (Remember i_pc can't stop
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// changing for a clock, so we need to keep track of the last
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// changing for a clock, so we need to keep track of the last
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// one from before it stopped.)
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// one from before it stopped.)
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//
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//
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// Here we keep track of which answer we want/need
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// Here we keep track of which answer we want/need
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isrc <= ((r_v)&&(i_stall_n))||(i_new_pc);
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isrc <= ((r_v)&&(i_stall_n))||(i_new_pc);
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// Here we read both, and select which was write using isrc
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// Here we read both, and select which was write using isrc
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// on the next clock.
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// on the next clock.
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r_pc_cache <= cache[i_pc[(CW-1):0]];
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r_pc_cache <= cache[i_pc[(CW-1):0]];
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r_last_cache <= cache[lastpc[(CW-1):0]];
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r_last_cache <= cache[lastpc[(CW-1):0]];
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r_pc <= i_pc;
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r_pc <= i_pc;
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r_lastpc <= lastpc;
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r_lastpc <= lastpc;
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end
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end
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assign o_pc = (isrc) ? r_pc : r_lastpc;
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assign o_pc = (isrc) ? r_pc : r_lastpc;
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assign o_i = (isrc) ? r_pc_cache : r_last_cache;
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assign o_i = (isrc) ? r_pc_cache : r_last_cache;
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reg tagsrc;
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reg tagsrc;
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always @(posedge i_clk)
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always @(posedge i_clk)
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// It may be possible to recover a clock once the cache line
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// It may be possible to recover a clock once the cache line
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// has been filled, but our prior attempt to do so has lead
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// has been filled, but our prior attempt to do so has lead
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// to a race condition, so we keep this logic simple.
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// to a race condition, so we keep this logic simple.
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if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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tagsrc <= 1'b1;
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tagsrc <= 1'b1;
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else
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else
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tagsrc <= 1'b0;
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tagsrc <= 1'b0;
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initial tagvalipc = 0;
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initial tagvalipc = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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tagvalipc <= tags[i_pc[(CW-1):PW]];
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tagvalipc <= tags[i_pc[(CW-1):PW]];
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initial tagvallst = 0;
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initial tagvallst = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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tagvallst <= tags[lastpc[(CW-1):PW]];
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tagvallst <= tags[lastpc[(CW-1):PW]];
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assign tagval = (tagsrc)?tagvalipc : tagvallst;
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assign tagval = (tagsrc)?tagvalipc : tagvallst;
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// i_pc will only increment when everything else isn't stalled, thus
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// i_pc will only increment when everything else isn't stalled, thus
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// we can set it without worrying about that. Doing this enables
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// we can set it without worrying about that. Doing this enables
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// us to work in spite of stalls. For example, if the next address
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// us to work in spite of stalls. For example, if the next address
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// isn't valid, but the decoder is stalled, get the next address
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// isn't valid, but the decoder is stalled, get the next address
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// anyway.
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// anyway.
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initial lastpc = 0;
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initial lastpc = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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lastpc <= i_pc;
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lastpc <= i_pc;
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assign lasttag = lastpc[(AW-1):PW];
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assign lasttag = lastpc[(AW-1):PW];
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wire w_v_from_pc, w_v_from_last;
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wire w_v_from_pc, w_v_from_last;
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assign w_v_from_pc = ((i_pc[(AW-1):PW] == lasttag)
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assign w_v_from_pc = ((i_pc[(AW-1):PW] == lasttag)
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&&(tagvalipc == i_pc[(AW-1):CW])
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&&(tagvalipc == i_pc[(AW-1):CW])
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&&(vmask[i_pc[(CW-1):PW]]));
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&&(vmask[i_pc[(CW-1):PW]]));
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assign w_v_from_last = (
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assign w_v_from_last = (
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//(lastpc[(AW-1):PW] == lasttag)&&
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//(lastpc[(AW-1):PW] == lasttag)&&
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(tagval == lastpc[(AW-1):CW])
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(tagval == lastpc[(AW-1):CW])
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&&(vmask[lastpc[(CW-1):PW]]));
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&&(vmask[lastpc[(CW-1):PW]]));
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reg [1:0] delay;
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reg [1:0] delay;
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initial delay = 2'h3;
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initial delay = 2'h3;
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reg rvsrc;
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reg rvsrc;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache)||(i_new_pc)||((r_v)&&(i_stall_n)))
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if ((i_rst)||(i_clear_cache)||(i_new_pc)||((r_v)&&(i_stall_n)))
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begin
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begin
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// r_v <= r_v_from_pc;
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// r_v <= r_v_from_pc;
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rvsrc <= 1'b1;
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rvsrc <= 1'b1;
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delay <= 2'h2;
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delay <= 2'h2;
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end else if (~r_v) begin // Otherwise, r_v was true and we were
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end else if (~r_v) begin // Otherwise, r_v was true and we were
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// stalled, hence only if ~r_v
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// stalled, hence only if ~r_v
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rvsrc <= 1'b0;
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rvsrc <= 1'b0;
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if (o_wb_cyc)
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if (o_wb_cyc)
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delay <= 2'h2;
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delay <= 2'h2;
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else if (delay != 0)
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else if (delay != 0)
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delay <= delay + 2'b11; // i.e. delay -= 1;
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delay <= delay + 2'b11; // i.e. delay -= 1;
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end
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end
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reg r_v_from_pc, r_v_from_last;
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reg r_v_from_pc, r_v_from_last;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_v_from_pc <= w_v_from_pc;
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r_v_from_pc <= w_v_from_pc;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_v_from_last <= w_v_from_last;
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r_v_from_last <= w_v_from_last;
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assign r_v = ((rvsrc)?(r_v_from_pc):(r_v_from_last));
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assign r_v = ((rvsrc)?(r_v_from_pc):(r_v_from_last));
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assign o_v = (((rvsrc)?(r_v_from_pc):(r_v_from_last))
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assign o_v = (((rvsrc)?(r_v_from_pc):(r_v_from_last))
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||((o_illegal)&&(~o_wb_cyc)))
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||((o_illegal)&&(~o_wb_cyc)))
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&&(~i_new_pc)&&(~i_rst);
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&&(~i_new_pc)&&(~i_rst);
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reg last_ack;
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reg last_ack;
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initial last_ack = 1'b0;
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initial last_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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last_ack <= (o_wb_cyc)&&(
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last_ack <= (o_wb_cyc)&&(
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(rdaddr[(PW-1):1]=={(PW-1){1'b1}})
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(rdaddr[(PW-1):1]=={(PW-1){1'b1}})
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&&((rdaddr[0])||(i_wb_ack)));
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&&((rdaddr[0])||(i_wb_ack)));
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reg needload;
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reg needload;
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initial needload = 1'b0;
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initial needload = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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needload <= ((~r_v)&&(delay==0)
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needload <= ((~r_v)&&(delay==0)
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&&((tagvallst != lastpc[(AW-1):CW])
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&&((tagvallst != lastpc[(AW-1):CW])
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||(~vmask[lastpc[(CW-1):PW]]))
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||(~vmask[lastpc[(CW-1):PW]]))
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&&((~illegal_valid)
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&&((~illegal_valid)
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||(lastpc[(AW-1):PW] != illegal_cache)));
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||(lastpc[(AW-1):PW] != illegal_cache)));
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reg last_addr;
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reg last_addr;
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initial last_addr = 1'b0;
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initial last_addr = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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last_addr <= (o_wb_cyc)&&(o_wb_addr[(PW-1):1] == {(PW-1){1'b1}})
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last_addr <= (o_wb_cyc)&&(o_wb_addr[(PW-1):1] == {(PW-1){1'b1}})
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&&((~i_wb_stall)|(o_wb_addr[0]));
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&&((~i_wb_stall)|(o_wb_addr[0]));
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|
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initial o_wb_cyc = 1'b0;
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initial o_wb_cyc = 1'b0;
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initial o_wb_stb = 1'b0;
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initial o_wb_stb = 1'b0;
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initial o_wb_addr = {(AW){1'b0}};
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initial o_wb_addr = {(AW){1'b0}};
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initial rdaddr = 0;
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initial rdaddr = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache))
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if ((i_rst)||(i_clear_cache))
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begin
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begin
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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o_wb_stb <= 1'b0;
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o_wb_stb <= 1'b0;
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end else if (o_wb_cyc)
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end else if (o_wb_cyc)
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begin
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begin
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if (i_wb_err)
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if (i_wb_err)
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o_wb_stb <= 1'b0;
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o_wb_stb <= 1'b0;
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else if ((o_wb_stb)&&(~i_wb_stall)&&(last_addr))
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else if ((o_wb_stb)&&(~i_wb_stall)&&(last_addr))
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o_wb_stb <= 1'b0;
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o_wb_stb <= 1'b0;
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|
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if (((i_wb_ack)&&(last_ack))||(i_wb_err))
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if (((i_wb_ack)&&(last_ack))||(i_wb_err))
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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|
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// else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
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// else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
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// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
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// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
|
|
|
end else if (needload)
|
end else if (needload)
|
begin
|
begin
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o_wb_cyc <= 1'b1;
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_stb <= 1'b1;
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end
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end
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|
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (o_wb_cyc) // &&(i_wb_ack)
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if (o_wb_cyc) // &&(i_wb_ack)
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tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
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tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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if ((o_wb_cyc)&&(i_wb_ack))
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rdaddr <= rdaddr + 1;
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rdaddr <= rdaddr + 1;
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else if (~o_wb_cyc)
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else if (~o_wb_cyc)
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rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
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rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
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|
|
always @(posedge i_clk)
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always @(posedge i_clk)
|
if ((o_wb_stb)&&(~i_wb_stall)&&(~last_addr))
|
if ((o_wb_stb)&&(~i_wb_stall)&&(~last_addr))
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o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
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o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
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else if (~o_wb_cyc)
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else if (~o_wb_cyc)
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o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
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o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
|
|
|
// Can't initialize an array, so leave cache uninitialized
|
// Can't initialize an array, so leave cache uninitialized
|
// We'll also never get an ack without sys being active, so skip
|
// We'll also never get an ack without sys being active, so skip
|
// that check. Or rather, let's just use o_wb_cyc instead. This
|
// that check. Or rather, let's just use o_wb_cyc instead. This
|
// will work because multiple writes to the same address, ending with
|
// will work because multiple writes to the same address, ending with
|
// a valid write, aren't a problem.
|
// a valid write, aren't a problem.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (o_wb_cyc) // &&(i_wb_ack)
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if (o_wb_cyc) // &&(i_wb_ack)
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cache[rdaddr] <= i_wb_data;
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cache[rdaddr] <= i_wb_data;
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|
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// VMask ... is a section loaded?
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// VMask ... is a section loaded?
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// Note "svmask". It's purpose is to delay the vmask setting by one
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// Note "svmask". It's purpose is to delay the vmask setting by one
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// clock, so that we can insure the right value of the cache is loaded
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// clock, so that we can insure the right value of the cache is loaded
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// before declaring that the cache line is valid. Without this, the
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// before declaring that the cache line is valid. Without this, the
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// cache line would get read, and the instruction would read from the
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// cache line would get read, and the instruction would read from the
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// last cache line.
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// last cache line.
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reg svmask;
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reg svmask;
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initial vmask = 0;
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initial vmask = 0;
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initial svmask = 1'b0;
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initial svmask = 1'b0;
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reg [(LGLINES-1):0] saddr;
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reg [(LGLINES-1):0] saddr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache))
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if ((i_rst)||(i_clear_cache))
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begin
|
begin
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vmask <= 0;
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vmask <= 0;
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svmask<= 1'b0;
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svmask<= 1'b0;
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end
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end
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else begin
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else begin
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svmask <= ((o_wb_cyc)&&(i_wb_ack)&&(last_ack));
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svmask <= ((o_wb_cyc)&&(i_wb_ack)&&(last_ack));
|
|
|
if (svmask)
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if (svmask)
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vmask[saddr] <= 1'b1;
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vmask[saddr] <= 1'b1;
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if ((~o_wb_cyc)&&(needload))
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if ((~o_wb_cyc)&&(needload))
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vmask[lastpc[(CW-1):PW]] <= 1'b0;
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vmask[lastpc[(CW-1):PW]] <= 1'b0;
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end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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if ((o_wb_cyc)&&(i_wb_ack))
|
saddr <= rdaddr[(CW-1):PW];
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saddr <= rdaddr[(CW-1):PW];
|
|
|
initial illegal_cache = 0;
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initial illegal_cache = 0;
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initial illegal_valid = 0;
|
initial illegal_valid = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_clear_cache))
|
if ((i_rst)||(i_clear_cache))
|
begin
|
begin
|
illegal_cache <= 0;
|
illegal_cache <= 0;
|
illegal_valid <= 0;
|
illegal_valid <= 0;
|
end else if ((o_wb_cyc)&&(i_wb_err))
|
end else if ((o_wb_cyc)&&(i_wb_err))
|
begin
|
begin
|
illegal_cache <= o_wb_addr[(AW-1):PW];
|
illegal_cache <= o_wb_addr[(AW-1):PW];
|
illegal_valid <= 1'b1;
|
illegal_valid <= 1'b1;
|
end
|
end
|
|
|
initial o_illegal = 1'b0;
|
initial o_illegal = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_clear_cache)||(o_wb_cyc))
|
if ((i_rst)||(i_clear_cache)||(o_wb_cyc))
|
o_illegal <= 1'b0;
|
o_illegal <= 1'b0;
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else
|
else
|
o_illegal <= (illegal_valid)
|
o_illegal <= (illegal_valid)
|
&&(illegal_cache == i_pc[(AW-1):PW]);
|
&&(illegal_cache == i_pc[(AW-1):PW]);
|
|
|
endmodule
|
endmodule
|
|
|
