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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Diff between revs 11 and 18

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//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
module  pipefetch(i_clk, i_rst, i_new_pc, i_stall_n, i_pc,
module  pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
                        o_i, o_pc, o_v,
                        o_i, o_pc, o_v,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);
        parameter       RESET_ADDRESS=32'h0010_0000,
        parameter       RESET_ADDRESS=32'h0010_0000,
                        LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
                        LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
                        BUSW=32;
                        BUSW=32;
        input                           i_clk, i_rst, i_new_pc, i_stall_n;
        input                           i_clk, i_rst, i_new_pc,
 
                                        i_clear_cache, i_stall_n;
        input           [(BUSW-1):0]     i_pc;
        input           [(BUSW-1):0]     i_pc;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(BUSW-1):0]     o_pc;
        output  reg     [(BUSW-1):0]     o_pc;
        output  wire                    o_v;
        output  wire                    o_v;
        //
        //
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                                                + (1<<(LGCACHELEN-1)));
                                                + (1<<(LGCACHELEN-1)));
        initial r_nvalid = 0;
        initial r_nvalid = 0;
        initial r_cache_base = RESET_ADDRESS;
        initial r_cache_base = RESET_ADDRESS;
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                if (i_rst)
                if ((i_rst)||(i_clear_cache))
                begin
                begin
                        o_wb_cyc <= 1'b0;
                        o_wb_cyc <= 1'b0;
 
                        o_wb_stb <= 1'b0;
                        // r_cache_base <= RESET_ADDRESS;
                        // r_cache_base <= RESET_ADDRESS;
                // end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
                // end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
                //              &&(i_pc >= r_cache_base)
                //              &&(i_pc >= r_cache_base)
                //              &&(i_pc < r_cache_base + bus_nvalid))
                //              &&(i_pc < r_cache_base + bus_nvalid))
                // begin
                // begin
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                        end
                        end
                end
                end
        end
        end
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst) // Required, so we can reload memoy and then reset
                if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
                        r_nvalid <= 0;
                        r_nvalid <= 0;
                else if ((~o_wb_cyc)&&(
                else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                        r_nvalid <= 0;
                        r_nvalid <= 0;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
                        r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
                else if ((o_wb_cyc)&&(i_wb_ack))
                else if ((o_wb_cyc)&&(i_wb_ack))
                        r_nvalid <= r_nvalid+1;
                        r_nvalid <= r_nvalid+1;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((~o_wb_cyc)&&(
                if (i_clear_cache)
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                        r_cache_base <= i_pc;
 
                else if ((~o_wb_cyc)&&(
 
                                (w_pc_out_of_bounds)
 
                                ||(w_ran_off_end_of_cache)))
                        r_cache_base <= (i_new_pc) ? i_pc : r_addr;
                        r_cache_base <= (i_new_pc) ? i_pc : r_addr;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
                        r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((~o_wb_cyc)&&(
                if (i_clear_cache)
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                        r_cache_offset <= 0;
 
                else if ((~o_wb_cyc)&&(
 
                                (w_pc_out_of_bounds)
 
                                ||(w_ran_off_end_of_cache)))
                        r_cache_offset <= 0;
                        r_cache_offset <= 0;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
                        r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
                if (i_clear_cache)
 
                        o_wb_addr <= i_pc;
 
                else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
                                        ||(w_ran_off_end_of_cache)))
                                        ||(w_ran_off_end_of_cache)))
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
                        o_wb_addr <= o_wb_addr + 1;
                        o_wb_addr <= o_wb_addr + 1;
 
 
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                        cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
                        cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
                                        <= i_wb_data;
                                        <= i_wb_data;
 
 
        initial r_addr_set = 1'b0;
        initial r_addr_set = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if ((i_rst)||(i_clear_cache))
                        r_addr_set <= 1'b0;
                        r_addr_set <= 1'b0;
                else if (i_new_pc)
                else if (i_new_pc)
                        r_addr_set <= 1'b1;
                        r_addr_set <= 1'b1;
 
 
        // Now, read from the cache
        // Now, read from the cache
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                        o_i <= cache[c_rdaddr];
                        o_i <= cache[c_rdaddr];
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_stall_n)
                if (i_stall_n)
                        o_pc <= r_addr;
                        o_pc <= r_addr;
 
 
 
 
endmodule
endmodule
 
 
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