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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipemem.v] - Diff between revs 69 and 131

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Rev 69 Rev 131
Line 66... Line 66...
        output  reg     [31:0]   o_wb_data;
        output  reg     [31:0]   o_wb_data;
        // Wishbone inputs
        // Wishbone inputs
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
 
 
 
        reg     cyc;
        reg                     r_wb_cyc_gbl, r_wb_cyc_lcl;
        reg                     r_wb_cyc_gbl, r_wb_cyc_lcl;
        reg     [3:0]            rdaddr, wraddr;
        reg     [3:0]            rdaddr, wraddr;
        wire    [3:0]            nxt_rdaddr;
        wire    [3:0]            nxt_rdaddr;
        reg     [(5-1):0]        fifo_oreg [0:15];
        reg     [(5-1):0]        fifo_oreg [0:15];
        initial rdaddr = 0;
        initial rdaddr = 0;
Line 86... Line 87...
                        rdaddr <= 0;
                        rdaddr <= 0;
                else if ((i_wb_ack)&&(cyc))
                else if ((i_wb_ack)&&(cyc))
                        rdaddr <= rdaddr + 4'h1;
                        rdaddr <= rdaddr + 4'h1;
        assign  nxt_rdaddr = rdaddr + 4'h1;
        assign  nxt_rdaddr = rdaddr + 4'h1;
 
 
        reg     cyc;
 
        wire    gbl_stb, lcl_stb;
        wire    gbl_stb, lcl_stb;
        assign  lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
        assign  lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
        assign  gbl_stb = (~lcl_stb);
        assign  gbl_stb = (~lcl_stb);
                        //= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
                        //= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
 
 

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