| Line 112... |
Line 112... |
`define CPU_STEP_BIT 6
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`define CPU_STEP_BIT 6
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`define CPU_GIE_BIT 5
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`define CPU_GIE_BIT 5
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`define CPU_SLEEP_BIT 4
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`define CPU_SLEEP_BIT 4
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module zipcpu(i_clk, i_rst, i_interrupt,
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module zipcpu(i_clk, i_rst, i_interrupt,
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// Debug interface
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// Debug interface
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i_halt, i_dbg_reg, i_dbg_we, i_dbg_data,
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i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
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o_dbg_stall, o_dbg_reg,
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o_dbg_stall, o_dbg_reg, o_dbg_cc,
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o_break,
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o_break,
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// CPU interface to the wishbone bus
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// CPU interface to the wishbone bus
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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// Accounting/CPU usage interface
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// Accounting/CPU usage interface
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o_op_stall, o_pf_stall, o_i_count);
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o_op_stall, o_pf_stall, o_i_count);
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parameter RESET_ADDRESS=32'h0100000;
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parameter RESET_ADDRESS=32'h0100000;
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input i_clk, i_rst, i_interrupt;
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input i_clk, i_rst, i_interrupt;
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// Debug interface -- inputs
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// Debug interface -- inputs
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input i_halt;
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input i_halt, i_clear_pf_cache;
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input [4:0] i_dbg_reg;
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input [4:0] i_dbg_reg;
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input i_dbg_we;
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input i_dbg_we;
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input [31:0] i_dbg_data;
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input [31:0] i_dbg_data;
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// Debug interface -- outputs
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// Debug interface -- outputs
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output reg o_dbg_stall;
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output reg o_dbg_stall;
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output reg [31:0] o_dbg_reg;
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output reg [31:0] o_dbg_reg;
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output reg [3:0] o_dbg_cc;
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output wire o_break;
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output wire o_break;
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// Wishbone interface -- outputs
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// Wishbone interface -- outputs
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire [31:0] o_wb_addr, o_wb_data;
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output wire [31:0] o_wb_addr, o_wb_data;
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// Wishbone interface -- inputs
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// Wishbone interface -- inputs
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| Line 161... |
Line 162... |
// PIPELINE STAGE #1 :: Prefetch
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// PIPELINE STAGE #1 :: Prefetch
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// Variable declarations
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// Variable declarations
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//
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//
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reg [31:0] pf_pc;
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reg [31:0] pf_pc;
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reg new_pc;
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reg new_pc;
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wire clear_pipeline;
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assign clear_pipeline = new_pc || i_clear_pf_cache;
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|
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wire dcd_stalled;
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wire dcd_stalled;
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wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
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wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
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wire [31:0] pf_addr, pf_data;
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wire [31:0] pf_addr, pf_data;
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wire [31:0] instruction, instruction_pc;
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wire [31:0] instruction, instruction_pc;
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| Line 281... |
Line 284... |
//
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//
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// PIPELINE STAGE #4 :: ALU / Memory
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// PIPELINE STAGE #4 :: ALU / Memory
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// Calculate stall conditions
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// Calculate stall conditions
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assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid)&&(~opM))
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assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid)&&(~opM))
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||((opvalid)&&(wr_reg_ce)&&(wr_reg_id == { op_gie, `CPU_PC_REG }));
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||((opvalid)&&(wr_reg_ce)&&(wr_reg_id == { op_gie, `CPU_PC_REG }));
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assign alu_ce = (master_ce)&&(opvalid)&&(~opM)&&(~alu_stall)&&(~new_pc);
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assign alu_ce = (master_ce)&&(opvalid)&&(~opM)&&(~alu_stall)&&(~clear_pipeline);
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//
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//
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assign mem_ce = (master_ce)&&(opvalid)&&(opM)&&(~mem_stalled)&&(~new_pc)&&(set_cond);
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assign mem_ce = (master_ce)&&(opvalid)&&(opM)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
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assign mem_stalled = (mem_busy)||((opvalid)&&(opM)&&(
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assign mem_stalled = (mem_busy)||((opvalid)&&(opM)&&(
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(~master_ce)
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(~master_ce)
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// Stall waiting for flags to be valid
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// Stall waiting for flags to be valid
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||((~opF[8])&&(
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||((~opF[8])&&(
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((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG}))))
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((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG}))))
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| Line 312... |
Line 315... |
pf_cyc, pf_stb, pf_we, pf_addr,
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pf_cyc, pf_stb, pf_we, pf_addr,
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pf_data,
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pf_data,
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pf_ack, pf_stall, i_wb_data);
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pf_ack, pf_stall, i_wb_data);
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`else // Pipe fetch
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`else // Pipe fetch
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pipefetch #(RESET_ADDRESS)
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pipefetch #(RESET_ADDRESS)
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pf(i_clk, i_rst, new_pc, ~dcd_stalled, pf_pc,
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pf(i_clk, i_rst, new_pc, i_clear_pf_cache, ~dcd_stalled, pf_pc,
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instruction, instruction_pc, pf_valid,
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instruction, instruction_pc, pf_valid,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_ack, pf_stall, i_wb_data,
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pf_ack, pf_stall, i_wb_data,
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mem_cyc);
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mem_cyc);
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assign instruction_gie = gie;
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assign instruction_gie = gie;
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| Line 324... |
Line 327... |
|
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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dcdvalid <= 1'b0;
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dcdvalid <= 1'b0;
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else if (dcd_ce)
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else if (dcd_ce)
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dcdvalid <= (~new_pc);
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dcdvalid <= (~clear_pipeline);
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else if ((~dcd_stalled)||(new_pc))
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else if ((~dcd_stalled)||(clear_pipeline))
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dcdvalid <= 1'b0;
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dcdvalid <= 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (dcd_ce)
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if (dcd_ce)
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begin
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begin
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| Line 509... |
Line 512... |
// have in our queue. This instruction must then
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// have in our queue. This instruction must then
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// move forward, and get a stall cycle inserted.
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// move forward, and get a stall cycle inserted.
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// Hence, the test on dcd_stalled here. If we must
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// Hence, the test on dcd_stalled here. If we must
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// wait until our operands are valid, then we aren't
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// wait until our operands are valid, then we aren't
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// valid yet until then.
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// valid yet until then.
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opvalid<= (~new_pc)&&(dcdvalid)&&(~dcd_stalled);
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opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
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else if ((~op_stall)||(new_pc))
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else if ((~op_stall)||(clear_pipeline))
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opvalid <= 1'b0;
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opvalid <= 1'b0;
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// Here's part of our debug interface. When we recognize a break
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// Here's part of our debug interface. When we recognize a break
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// instruction, we set the op_break flag. That'll prevent this
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// instruction, we set the op_break flag. That'll prevent this
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// instruction from entering the ALU, and cause an interrupt before
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// instruction from entering the ALU, and cause an interrupt before
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| Line 526... |
Line 529... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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op_break <= 1'b0;
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op_break <= 1'b0;
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else if (op_ce)
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else if (op_ce)
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op_break <= (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
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op_break <= (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
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else if ((~op_stall)||(new_pc))
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else if ((~op_stall)||(clear_pipeline))
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op_break <= 1'b0;
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op_break <= 1'b0;
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|
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (op_ce)
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if (op_ce)
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begin
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begin
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| Line 624... |
Line 627... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if ((alu_ce)||(mem_ce))
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if ((alu_ce)||(mem_ce))
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alu_pc <= op_pc;
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alu_pc <= op_pc;
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initial alu_pc_valid = 1'b0;
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initial alu_pc_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~new_pc)
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alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~clear_pipeline)
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&&((~opM)
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&&((~opM)
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||(~mem_stalled));
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||(~mem_stalled));
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|
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memops domem(i_clk, i_rst, mem_ce,
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memops domem(i_clk, i_rst, mem_ce,
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(opn[0]), opB, opA, opR,
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(opn[0]), opB, opA, opR,
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| Line 674... |
Line 677... |
// What value to write?
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// What value to write?
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assign wr_reg_vl = (alu_wr)?alu_result:mem_result;
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assign wr_reg_vl = (alu_wr)?alu_result:mem_result;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wr_reg_ce)
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if (wr_reg_ce)
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regset[wr_reg_id] <= wr_reg_vl;
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regset[wr_reg_id] <= wr_reg_vl;
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else if ((i_halt)&&(i_dbg_we))
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regset[i_dbg_reg] <= i_dbg_data[31:0];
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|
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//
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//
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// Write back to the condition codes/flags register ...
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// Write back to the condition codes/flags register ...
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// When shall we write to our flags register? alF_wr already
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// When shall we write to our flags register? alF_wr already
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// includes the set condition ...
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// includes the set condition ...
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| Line 830... |
Line 835... |
else if (dcd_ce)
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else if (dcd_ce)
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pf_pc <= pf_pc + 1;
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pf_pc <= pf_pc + 1;
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|
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initial new_pc = 1'b1;
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initial new_pc = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if ((i_rst)||(i_clear_pf_cache))
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new_pc <= 1'b1;
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new_pc <= 1'b1;
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else if (w_switch_to_interrupt)
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else if (w_switch_to_interrupt)
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new_pc <= 1'b1;
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new_pc <= 1'b1;
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else if (w_release_from_interrupt)
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else if (w_release_from_interrupt)
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new_pc <= 1'b1;
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new_pc <= 1'b1;
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| Line 856... |
Line 861... |
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
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else if (i_dbg_reg[3:0] == `CPU_CC_REG)
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o_dbg_reg <= { 25'h00, step, gie, sleep,
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o_dbg_reg <= { 25'h00, step, gie, sleep,
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((i_dbg_reg[4])?flags:iflags) };
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((i_dbg_reg[4])?flags:iflags) };
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end
|
end
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always @(posedge i_clk)
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always @(posedge i_clk)
|
|
o_dbg_cc <= { break_en, step, gie, sleep };
|
|
|
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always @(posedge i_clk)
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o_dbg_stall <= (~i_halt)||(pf_cyc)||(mem_cyc)||(mem_busy)
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o_dbg_stall <= (~i_halt)||(pf_cyc)||(mem_cyc)||(mem_busy)
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||((~opvalid)&&(~i_rst))
|
||((~opvalid)&&(~i_rst))
|
||((~dcdvalid)&&(~i_rst));
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||((~dcdvalid)&&(~i_rst));
|
|
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//
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//
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