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[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Diff between revs 201 and 205

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Rev 201 Rev 205
Line 43... Line 43...
//      The difference between these control signals allows individual stages
//      The difference between these control signals allows individual stages
//      to propagate instructions independently.  In general, the logic works
//      to propagate instructions independently.  In general, the logic works
//      as:
//      as:
//
//
//
//
//      assign  (n)_ce = (n-1)_valid && (~(n)_stall)
//      assign  (n)_ce = (n-1)_valid && (!(n)_stall)
//
//
//
//
//      always @(posedge i_clk)
//      always @(posedge i_clk)
//              if ((i_rst)||(clear_pipeline))
//              if ((i_rst)||(clear_pipeline))
//                      (n)_valid = 0
//                      (n)_valid = 0
Line 259... Line 259...
        wire    [3:0]    dcd_F;
        wire    [3:0]    dcd_F;
        wire            dcd_wR, dcd_rA, dcd_rB,
        wire            dcd_wR, dcd_rA, dcd_rB,
                                dcd_ALU, dcd_M, dcd_DIV, dcd_FP,
                                dcd_ALU, dcd_M, dcd_DIV, dcd_FP,
                                dcd_wF, dcd_gie, dcd_break, dcd_lock,
                                dcd_wF, dcd_gie, dcd_break, dcd_lock,
                                dcd_pipe, dcd_ljmp;
                                dcd_pipe, dcd_ljmp;
        reg             r_dcd_valid;
 
        wire            dcd_valid;
        wire            dcd_valid;
        wire    [AW:0]   dcd_pc /* verilator public_flat */;
        wire    [AW:0]   dcd_pc /* verilator public_flat */;
        wire    [31:0]   dcd_I;
        wire    [31:0]   dcd_I;
        wire            dcd_zI; // true if dcd_I == 0
        wire            dcd_zI; // true if dcd_I == 0
        wire    dcd_A_stall, dcd_B_stall, dcd_F_stall;
        wire    dcd_A_stall, dcd_B_stall, dcd_F_stall;
Line 296... Line 295...
        wire    [14:0]   op_Fl;
        wire    [14:0]   op_Fl;
        reg     [6:0]    r_op_F;
        reg     [6:0]    r_op_F;
        wire    [7:0]    op_F;
        wire    [7:0]    op_F;
        wire            op_ce, op_phase, op_pipe, op_change_data_ce;
        wire            op_ce, op_phase, op_pipe, op_change_data_ce;
        // Some pipeline control wires
        // Some pipeline control wires
`ifdef  OPT_PIPELINED
 
        reg     op_A_alu, op_A_mem;
 
        reg     op_B_alu, op_B_mem;
 
`endif
 
        reg     op_illegal;
        reg     op_illegal;
        wire    op_break;
        wire    op_break;
        wire    op_lock;
        wire    op_lock;
 
 
`ifdef  VERILATOR
`ifdef  VERILATOR
Line 345... Line 340...
 
 
        wire    div_ce, div_error, div_busy, div_valid;
        wire    div_ce, div_error, div_busy, div_valid;
        wire    [31:0]   div_result;
        wire    [31:0]   div_result;
        wire    [3:0]    div_flags;
        wire    [3:0]    div_flags;
 
 
        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_div)
        assign  div_ce = (master_ce)&&(!clear_pipeline)&&(op_valid_div)
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
                                &&(!mem_rdbusy)&&(!div_busy)&&(!fpu_busy)
                                &&(set_cond);
                                &&(set_cond);
 
 
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
        wire    [31:0]   fpu_result;
        wire    [31:0]   fpu_result;
        wire    [3:0]    fpu_flags;
        wire    [3:0]    fpu_flags;
 
 
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_fpu)
        assign  fpu_ce = (master_ce)&&(!clear_pipeline)&&(op_valid_fpu)
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
                                &&(!mem_rdbusy)&&(!div_busy)&&(!fpu_busy)
                                &&(set_cond);
                                &&(set_cond);
 
 
        wire    adf_ce_unconditional;
        wire    adf_ce_unconditional;
 
 
        //
        //
Line 377... Line 372...
 
 
 
 
        //
        //
        //      MASTER: clock enable.
        //      MASTER: clock enable.
        //
        //
        assign  master_ce = ((~i_halt)||(alu_phase))&&(~o_break)&&(~sleep);
        assign  master_ce = ((!i_halt)||(alu_phase))&&(!o_break)&&(!sleep);
 
 
 
 
        //
        //
        //      PIPELINE STAGE #1 :: Prefetch
        //      PIPELINE STAGE #1 :: Prefetch
        //              Calculate stall conditions
        //              Calculate stall conditions
Line 390... Line 385...
        //
        //
 
 
        //
        //
        //      PIPELINE STAGE #2 :: Instruction Decode
        //      PIPELINE STAGE #2 :: Instruction Decode
        //              Calculate stall conditions
        //              Calculate stall conditions
        assign          dcd_ce = ((~dcd_valid)||(~dcd_stalled))&&(~clear_pipeline);
 
 
 
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        assign          dcd_stalled = (dcd_valid)&&(op_stall);
        assign          dcd_stalled = (dcd_valid)&&(op_stall);
`else
`else // Not pipelined -- either double or single fetch
        // If not pipelined, there will be no op_valid_ anything, and the
        assign          dcd_stalled = (dcd_valid)&&(op_stall);
        // op_stall will be false, dcd_X_stall will be false, thus we can simply
 
        // do a ...
 
        assign          dcd_stalled = 1'b0;
 
`endif
`endif
        //
        //
        //      PIPELINE STAGE #3 :: Read Operands
        //      PIPELINE STAGE #3 :: Read Operands
        //              Calculate stall conditions
        //              Calculate stall conditions
        wire    prelock_stall;
        wire    prelock_stall;
Line 416... Line 407...
                        ||(mem_busy)||(div_busy)||(fpu_busy);
                        ||(mem_busy)||(div_busy)||(fpu_busy);
 
 
        assign  op_stall = (op_valid)&&( // Only stall if we're loaded w/validins
        assign  op_stall = (op_valid)&&( // Only stall if we're loaded w/validins
                        // Stall if we're stopped, and not allowed to execute
                        // Stall if we're stopped, and not allowed to execute
                        // an instruction
                        // an instruction
                        // (~master_ce)         // Already captured in alu_stall
                        // (!master_ce)         // Already captured in alu_stall
                        //
                        //
                        // Stall if going into the ALU and the ALU is stalled
                        // Stall if going into the ALU and the ALU is stalled
                        //      i.e. if the memory is busy, or we are single
                        //      i.e. if the memory is busy, or we are single
                        //      stepping.  This also includes our stalls for
                        //      stepping.  This also includes our stalls for
                        //      op_break and op_lock, so we don't need to
                        //      op_break and op_lock, so we don't need to
Line 450... Line 441...
                                // CC register
                                // CC register
                                ||(dcd_F_stall)
                                ||(dcd_F_stall)
                        );
                        );
        assign  op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);
        assign  op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);
 
 
 
`else
 
        assign  op_stall = (alu_busy)||(div_busy)||(fpu_busy)||(wr_reg_ce)
 
                        ||(mem_busy)||(op_valid)||(!master_ce)||(wr_flags_ce);
 
        assign  op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);
 
`endif
 
 
        // BUT ... op_ce is too complex for many of the data operations.  So
        // BUT ... op_ce is too complex for many of the data operations.  So
        // let's make their circuit enable code simpler.  In particular, if
        // let's make their circuit enable code simpler.  In particular, if
        // op_ doesn't need to be preserved, we can change it all we want
        // op_ doesn't need to be preserved, we can change it all we want
        // ... right?  The clear_pipeline code, for example, really only needs
        // ... right?  The clear_pipeline code, for example, really only needs
        // to determine whether op_valid is true.
        // to determine whether op_valid is true.
        assign  op_change_data_ce = (~op_stall);
        assign  op_change_data_ce = (!op_stall);
`else
 
        assign  op_stall = (op_valid)&&(~master_ce);
 
        assign  op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(~clear_pipeline);
 
        assign  op_change_data_ce = 1'b1;
 
`endif
 
 
 
        //
        //
        //      PIPELINE STAGE #4 :: ALU / Memory
        //      PIPELINE STAGE #4 :: ALU / Memory
        //              Calculate stall conditions
        //              Calculate stall conditions
        //
        //
Line 477... Line 468...
        //      since we don't know if it'll put us to sleep or not.
        //      since we don't know if it'll put us to sleep or not.
        // 4. Last case: Stall if we would otherwise move a break instruction
        // 4. Last case: Stall if we would otherwise move a break instruction
        //      through the ALU.  Break instructions are not allowed through
        //      through the ALU.  Break instructions are not allowed through
        //      the ALU.
        //      the ALU.
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        assign  alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(op_valid_alu)) //Case 1&2
        assign  alu_stall = (((!master_ce)||(mem_rdbusy)||(alu_busy))&&(op_valid_alu)) //Case 1&2
                        ||(prelock_stall)
                        ||(prelock_stall)
                        ||((op_valid)&&(op_break))
                        ||((op_valid)&&(op_break))
                        ||(wr_reg_ce)&&(wr_write_cc)
                        ||(wr_reg_ce)&&(wr_write_cc)
                        ||(div_busy)||(fpu_busy);
                        ||(div_busy)||(fpu_busy);
        assign  alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall)
        assign  alu_ce = (master_ce)&&(op_valid_alu)&&(!alu_stall)
                                &&(~clear_pipeline);
                                &&(!clear_pipeline);
`else
`else
        assign  alu_stall = (op_valid_alu)&&((~master_ce)||(op_break));
        assign  alu_stall = (op_valid_alu)&&((!master_ce)||(op_break));
        assign  alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall)&&(~clear_pipeline);
        assign  alu_ce = (master_ce)&&(op_valid_alu)&&(!alu_stall)&&(!clear_pipeline);
`endif
`endif
        //
        //
 
 
        //
        //
        // Note: if you change the conditions for mem_ce, you must also change
        // Note: if you change the conditions for mem_ce, you must also change
        // alu_pc_valid.
        // alu_pc_valid.
        //
        //
`ifdef  OPT_PIPELINED
        assign  mem_ce = (master_ce)&&(op_valid_mem)&&(!mem_stalled)
        assign  mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled)
                        &&(!clear_pipeline);
                        &&(~clear_pipeline);
 
`else
 
        // If we aren't pipelined, then no one will be changing what's in the
 
        // pipeline (i.e. clear_pipeline), while our only instruction goes
 
        // through the ... pipeline.
 
        //
 
        // However, in hind sight this logic didn't work.  What happens when
 
        // something gets in the pipeline and then (due to interrupt or some
 
        // such) needs to be voided?  Thus we avoid simplification and keep
 
        // what worked here.
 
        assign  mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled)
 
                        &&(~clear_pipeline);
 
`endif
 
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
        assign  mem_stalled = (~master_ce)||(alu_busy)||((op_valid_mem)&&(
        assign  mem_stalled = (!master_ce)||(alu_busy)||((op_valid_mem)&&(
                                (mem_pipe_stalled)
                                (mem_pipe_stalled)
                                ||(prelock_stall)
                                ||(prelock_stall)
                                ||((~op_pipe)&&(mem_busy))
                                ||((!op_pipe)&&(mem_busy))
                                ||(div_busy)
                                ||(div_busy)
                                ||(fpu_busy)
                                ||(fpu_busy)
                                // Stall waiting for flags to be valid
                                // Stall waiting for flags to be valid
                                // Or waiting for a write to the PC register
                                // Or waiting for a write to the PC register
                                // Or CC register, since that can change the
                                // Or CC register, since that can change the
Line 525... Line 504...
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                                        &&((wr_write_pc)||(wr_write_cc)))));
                                        &&((wr_write_pc)||(wr_write_cc)))));
`else
`else
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        assign  mem_stalled = (mem_busy)||((op_valid_mem)&&(
        assign  mem_stalled = (mem_busy)||((op_valid_mem)&&(
                                (~master_ce)
                                (!master_ce)
                                // Stall waiting for flags to be valid
                                // Stall waiting for flags to be valid
                                // Or waiting for a write to the PC register
                                // Or waiting for a write to the PC register
                                // Or CC register, since that can change the
                                // Or CC register, since that can change the
                                //  PC as well
                                //  PC as well
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
`else
`else
        assign  mem_stalled = (op_valid_mem)&&(~master_ce);
        assign  mem_stalled = (op_valid_mem)&&(!master_ce);
`endif
`endif
`endif
`endif
 
 
        // ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
        // ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
        assign  adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(op_valid)
        assign  adf_ce_unconditional = (master_ce)&&(!clear_pipeline)&&(op_valid)
                                &&(~op_valid_mem)&&(~mem_rdbusy)
                                &&(!op_valid_mem)&&(!mem_rdbusy)
                                &&((~op_valid_alu)||(~alu_stall))&&(~op_break)
                                &&((!op_valid_alu)||(!alu_stall))&&(!op_break)
                                &&(~div_busy)&&(~fpu_busy)&&(~clear_pipeline);
                                &&(!div_busy)&&(!fpu_busy)&&(!clear_pipeline);
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #1 :: Prefetch
        //      PIPELINE STAGE #1 :: Prefetch
        //
        //
        //
        //
`ifdef  OPT_SINGLE_FETCH
        wire    pf_stalled;
        wire            pf_ce;
        assign  pf_stalled = (dcd_stalled)||(dcd_phase);
 
 
 
        wire    pf_new_pc;
 
        assign  pf_new_pc = (new_pc)||((dcd_early_branch)&&(!clear_pipeline));
 
 
        assign          pf_ce = (~pf_valid)&&(~dcd_valid)&&(~op_valid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid);
        wire    [(AW-1):0]       pf_request_address;
 
        assign  pf_request_address = ((dcd_early_branch)&&(!clear_pipeline))
 
                                ? dcd_branch_pc:pf_pc[(AW+1):2];
 
        assign  pf_gie = gie;
 
`ifdef  OPT_SINGLE_FETCH
        prefetch        #(ADDRESS_WIDTH)
        prefetch        #(ADDRESS_WIDTH)
                        pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc[(AW+1):2], gie,
                        pf(i_clk, (i_rst), pf_new_pc, w_clear_icache,
                                pf_instruction, pf_instruction_pc, pf_gie,
                                (!pf_stalled),
 
                                pf_request_address,
 
                                pf_instruction, pf_instruction_pc,
                                        pf_valid, pf_illegal,
                                        pf_valid, pf_illegal,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_ack, pf_stall, pf_err, i_wb_data);
                                pf_ack, pf_stall, pf_err, i_wb_data);
 
 
        initial r_dcd_valid = 1'b0;
`else
        always @(posedge i_clk)
`ifdef  OPT_DOUBLE_FETCH
                if (clear_pipeline)
 
                        r_dcd_valid <= 1'b0;
 
                else if (dcd_ce)
 
                        r_dcd_valid <= (pf_valid)||(pf_illegal);
 
                else if (op_ce)
 
                        r_dcd_valid <= 1'b0;
 
        assign  dcd_valid = r_dcd_valid;
 
 
 
`else // Pipe fetch
        wire    [1:0]    pf_dbg;
 
        dblfetch #(ADDRESS_WIDTH)
 
                pf(i_clk, i_rst, pf_new_pc,
 
                                w_clear_icache,
 
                                (!pf_stalled),
 
                                pf_request_address,
 
                                pf_instruction, pf_instruction_pc,
 
                                        pf_valid,
 
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
 
                                        pf_ack, pf_stall, pf_err, i_wb_data,
 
                                pf_illegal);
 
 
 
`else // Not single fetch and not double fetch
 
 
        wire    pf_stalled;
 
        assign  pf_stalled = (dcd_stalled)||(dcd_phase);
 
`ifdef  OPT_TRADITIONAL_PFCACHE
`ifdef  OPT_TRADITIONAL_PFCACHE
        wire    [(AW-1):0]       pf_request_address;
 
        assign  pf_request_address = ((dcd_early_branch)&&(!clear_pipeline))
 
                                ? dcd_branch_pc:pf_pc[(AW+1):2];
 
        pfcache #(LGICACHE, ADDRESS_WIDTH)
        pfcache #(LGICACHE, ADDRESS_WIDTH)
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
                pf(i_clk, i_rst, pf_new_pc, w_clear_icache,
                                        w_clear_icache,
 
                                // dcd_pc,
                                // dcd_pc,
                                (!pf_stalled),
                                (!pf_stalled),
                                pf_request_address,
                                pf_request_address,
                                pf_instruction, pf_instruction_pc, pf_valid,
                                pf_instruction, pf_instruction_pc, pf_valid,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
                                pf_illegal);
                                pf_illegal);
`else
`else
        pipefetch       #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH)
        pipefetch       #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH)
                        pf(i_clk, i_rst, (new_pc)||(dcd_early_branch),
                        pf(i_clk, i_rst, pf_new_pc,
                                        w_clear_icache, (!pf_stalled),
                                        w_clear_icache, (!pf_stalled),
                                        (new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc,
                                        (new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc,
                                        pf_instruction, pf_instruction_pc, pf_valid,
                                        pf_instruction, pf_instruction_pc, pf_valid,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
                                (mem_cyc_lcl)||(mem_cyc_gbl),
                                (mem_cyc_lcl)||(mem_cyc_gbl),
                                pf_illegal);
                                pf_illegal);
`endif
`endif  // OPT_TRADITIONAL_CACHE
`ifdef  OPT_NO_USERMODE
`endif  // OPT_DOUBLE_FETCH
        assign  pf_gie = 1'b0;
`endif  // OPT_SINGLE_FETCH
`else
 
        assign  pf_gie = gie;
 
`endif
 
 
 
        initial r_dcd_valid = 1'b0;
        assign          dcd_ce = (!dcd_valid)||(!dcd_stalled);
        always @(posedge i_clk)
 
                if ((clear_pipeline)||(w_clear_icache))
 
                        r_dcd_valid <= 1'b0;
 
                else if (dcd_ce)
 
                        r_dcd_valid <= ((dcd_phase)||(pf_valid))
 
                                        &&(~dcd_ljmp)&&(~dcd_early_branch);
 
                else if (op_ce)
 
                        r_dcd_valid <= 1'b0;
 
        assign  dcd_valid = r_dcd_valid;
 
`endif
 
 
 
        // If not pipelined, there will be no op_valid_ anything, and the
 
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
                        IMPLEMENT_FPU)
                        IMPLEMENT_FPU)
                instruction_decoder(i_clk, (clear_pipeline),
                instruction_decoder(i_clk,
                        (~dcd_valid)||(~op_stall), dcd_stalled, pf_instruction, pf_gie,
                        (clear_pipeline)||(w_clear_icache),
                        pf_instruction_pc, pf_valid, pf_illegal, dcd_phase,
                        dcd_ce,
 
                        dcd_stalled, pf_instruction, pf_gie,
 
                        pf_instruction_pc, pf_valid, pf_illegal,
 
                        dcd_valid, dcd_phase,
                        dcd_illegal, dcd_pc, dcd_gie,
                        dcd_illegal, dcd_pc, dcd_gie,
                        { dcd_Rcc, dcd_Rpc, dcd_R },
                        { dcd_Rcc, dcd_Rpc, dcd_R },
                        { dcd_Acc, dcd_Apc, dcd_A },
                        { dcd_Acc, dcd_Apc, dcd_A },
                        { dcd_Bcc, dcd_Bpc, dcd_B },
                        { dcd_Bcc, dcd_Bpc, dcd_B },
                        dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn,
                        dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn,
Line 727... Line 702...
                        op_rB <= dcd_rB;
                        op_rB <= dcd_rB;
                end
                end
`endif
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
`ifdef  OPT_PIPELINED
 
                if (op_ce)
                if (op_ce)
`endif
 
                begin
                begin
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
                        if ((wr_reg_ce)&&(wr_reg_id == dcd_A))
                        if ((wr_reg_ce)&&(wr_reg_id == dcd_A))
                                r_op_Av <= wr_gpreg_vl;
                                r_op_Av <= wr_gpreg_vl;
                        else
                        else
Line 744... Line 717...
                                r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags };
                                r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags };
                        else
                        else
                                r_op_Av <= w_op_Av;
                                r_op_Av <= w_op_Av;
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
                end else
                end else
                begin // We were going to pick these up when they became valid,
                begin
                        // but for some reason we're stuck here as they became
 
                        // valid.  Pick them up now anyway
 
                        // if (((op_A_alu)&&(alu_wR))||((op_A_mem)&&(mem_valid)))
 
                                // r_op_Av <= wr_gpreg_vl;
 
                        if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA))
                        if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA))
                                r_op_Av <= wr_gpreg_vl;
                                r_op_Av <= wr_gpreg_vl;
`endif
`endif
                end
                end
 
 
Line 796... Line 765...
        // conditions checking those bits.  Therefore, Vivado complains that
        // conditions checking those bits.  Therefore, Vivado complains that
        // these two bits are redundant.  Hence the convoluted expression
        // these two bits are redundant.  Hence the convoluted expression
        // below, arriving at what we finally want in the (now wire net)
        // below, arriving at what we finally want in the (now wire net)
        // op_F.
        // op_F.
        always @(posedge i_clk)
        always @(posedge i_clk)
`ifdef  OPT_PIPELINED
 
                if (op_ce) // Cannot do op_change_data_ce here since op_F depends
                if (op_ce) // Cannot do op_change_data_ce here since op_F depends
                        // upon being either correct for a valid op, or correct
                        // upon being either correct for a valid op, or correct
                        // for the last valid op
                        // for the last valid op
`endif
 
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
                        case(dcd_F[2:0])
                        case(dcd_F[2:0])
                        3'h0:   r_op_F <= 7'h00;        // Always
                        3'h0:   r_op_F <= 7'h00;        // Always
                        3'h1:   r_op_F <= 7'h11;        // Z
                        3'h1:   r_op_F <= 7'h11;        // Z
                        3'h2:   r_op_F <= 7'h44;        // LT
                        3'h2:   r_op_F <= 7'h44;        // LT
Line 816... Line 783...
                        endcase
                        endcase
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
        assign  op_F = { r_op_F[3], r_op_F[6:0] };
        assign  op_F = { r_op_F[3], r_op_F[6:0] };
 
 
        wire    w_op_valid;
        wire    w_op_valid;
        assign  w_op_valid = (~clear_pipeline)&&(dcd_valid)&&(~dcd_ljmp)&&(!dcd_early_branch);
        assign  w_op_valid = (!clear_pipeline)&&(dcd_valid)&&(!dcd_ljmp)&&(!dcd_early_branch);
        initial op_valid     = 1'b0;
        initial op_valid     = 1'b0;
        initial op_valid_alu = 1'b0;
        initial op_valid_alu = 1'b0;
        initial op_valid_mem = 1'b0;
        initial op_valid_mem = 1'b0;
        initial op_valid_div = 1'b0;
        initial op_valid_div = 1'b0;
        initial op_valid_fpu = 1'b0;
        initial op_valid_fpu = 1'b0;
Line 843... Line 810...
                        //   wait until our operands are valid, then we aren't
                        //   wait until our operands are valid, then we aren't
                        //   valid yet until then.
                        //   valid yet until then.
                        op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch);
                        op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch);
                        op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal)
                        op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal)
                                        ||(dcd_early_branch));
                                        ||(dcd_early_branch));
                        op_valid_mem <= (dcd_M)&&(~dcd_illegal)&&(w_op_valid);
                        op_valid_mem <= (dcd_M)&&(!dcd_illegal)&&(w_op_valid);
                        op_valid_div <= (dcd_DIV)&&(~dcd_illegal)&&(w_op_valid);
                        op_valid_div <= (dcd_DIV)&&(!dcd_illegal)&&(w_op_valid);
                        op_valid_fpu <= (dcd_FP)&&(~dcd_illegal)&&(w_op_valid);
                        op_valid_fpu <= (dcd_FP)&&(!dcd_illegal)&&(w_op_valid);
                end else if ((adf_ce_unconditional)||(mem_ce))
                end else if ((adf_ce_unconditional)||(mem_ce))
                begin
                begin
                        op_valid     <= 1'b0;
                        op_valid     <= 1'b0;
                        op_valid_alu <= 1'b0;
                        op_valid_alu <= 1'b0;
                        op_valid_mem <= 1'b0;
                        op_valid_mem <= 1'b0;
Line 864... Line 831...
        // break to repeat and continue upon return.  To get out of this
        // break to repeat and continue upon return.  To get out of this
        // condition, replace the break instruction with what it is supposed
        // condition, replace the break instruction with what it is supposed
        // to be, step through it, and then replace it back.  In this fashion,
        // to be, step through it, and then replace it back.  In this fashion,
        // a debugger can step through code.
        // a debugger can step through code.
        // assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001);
        // assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001);
`ifdef  OPT_PIPELINED
 
        reg     r_op_break;
        reg     r_op_break;
 
 
        initial r_op_break = 1'b0;
        initial r_op_break = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(clear_pipeline))  r_op_break <= 1'b0;
                if ((i_rst)||(clear_pipeline))  r_op_break <= 1'b0;
                else if (op_ce)
                else if (op_ce)
                        r_op_break <= (dcd_break);
                        r_op_break <= (dcd_break);
                else if (!op_valid)
                else if (!op_valid)
                        r_op_break <= 1'b0;
                        r_op_break <= 1'b0;
        assign  op_break = r_op_break;
        assign  op_break = r_op_break;
`else
 
        assign  op_break = dcd_break;
 
`endif
 
 
 
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        generate
        generate
        if (IMPLEMENT_LOCK != 0)
        if (IMPLEMENT_LOCK != 0)
        begin
        begin
Line 890... Line 853...
                initial r_op_lock = 1'b0;
                initial r_op_lock = 1'b0;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (clear_pipeline)
                        if (clear_pipeline)
                                r_op_lock <= 1'b0;
                                r_op_lock <= 1'b0;
                        else if (op_ce)
                        else if (op_ce)
                                r_op_lock <= (dcd_valid)&&(dcd_lock)&&(~clear_pipeline);
                                r_op_lock <= (dcd_valid)&&(dcd_lock)&&(!clear_pipeline);
                assign  op_lock = r_op_lock;
                assign  op_lock = r_op_lock;
 
 
        end else begin
        end else begin
                assign  op_lock = 1'b0;
                assign  op_lock = 1'b0;
        end endgenerate
        end endgenerate
Line 923... Line 886...
        // this logic should just optimize.
        // this logic should just optimize.
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                begin
                begin
                        op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR))
                        op_wF <= (dcd_wF)&&((!dcd_Rcc)||(!dcd_wR))
                                &&(~dcd_early_branch)&&(~dcd_illegal);
                                &&(!dcd_early_branch)&&(!dcd_illegal);
                        op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal);
                        op_wR <= (dcd_wR)&&(!dcd_early_branch)&&(!dcd_illegal);
                end
                end
`else
`else
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR))
                op_wF <= (dcd_wF)&&((!dcd_Rcc)||(!dcd_wR))
                        &&(~dcd_early_branch)&&(~dcd_illegal);
                        &&(!dcd_early_branch)&&(!dcd_illegal);
                op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal);
                op_wR <= (dcd_wR)&&(!dcd_early_branch)&&(!dcd_illegal);
        end
        end
`endif
`endif
 
 
`ifdef  VERILATOR
`ifdef  VERILATOR
`ifdef  OPT_PIPELINED
`ifdef  SINGLE_FETCH
 
        always @(*)
 
        begin
 
                op_sim      = dcd_sim;
 
                op_sim_immv = dcd_sim_immv;
 
        end
 
`else
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_change_data_ce)
                if (op_change_data_ce)
                begin
                begin
                        op_sim      <= dcd_sim;
                        op_sim      <= dcd_sim;
                        op_sim_immv <= dcd_sim_immv;
                        op_sim_immv <= dcd_sim_immv;
                end
                end
`else
 
        always @(*)
 
        begin
 
                op_sim      = dcd_sim;
 
                op_sim_immv = dcd_sim_immv;
 
        end
 
`endif
`endif
`endif
`endif
 
 
`ifdef  OPT_PIPELINED
 
        reg     [3:0]    r_op_opn;
        reg     [3:0]    r_op_opn;
        reg     [4:0]    r_op_R;
        reg     [4:0]    r_op_R;
        reg             r_op_Rcc;
        reg             r_op_Rcc;
        reg             r_op_gie;
        reg             r_op_gie;
 
 
 
        initial r_op_gie = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_change_data_ce)
                if (op_change_data_ce)
                begin
                begin
                        // Which ALU operation?  Early branches are
                        // Which ALU operation?  Early branches are
                        // unimplemented moves
                        // unimplemented moves
Line 976... Line 940...
                        //
                        //
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1];
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1];
                end
                end
        assign  op_opn = r_op_opn;
        assign  op_opn = r_op_opn;
        assign  op_R = r_op_R;
        assign  op_R = r_op_R;
`ifdef  OPT_NO_USERMODE
 
        assign  op_gie = 1'b0;
 
`else
 
        assign  op_gie = r_op_gie;
        assign  op_gie = r_op_gie;
`endif
 
        assign  op_Rcc = r_op_Rcc;
        assign  op_Rcc = r_op_Rcc;
`else
 
        assign  op_opn = dcd_opn;
 
        assign  op_R = dcd_R;
 
`ifdef  OPT_NO_USERMODE
 
        assign  op_gie = 1'b0;
 
`else
 
        assign  op_gie = dcd_gie;
 
`endif
 
        // With no pipelining, there is no early branching.  We keep it
 
        always @(posedge i_clk)
 
                op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1];
 
`endif
 
        assign  op_Fl = (op_gie)?(w_uflags):(w_iflags);
        assign  op_Fl = (op_gie)?(w_uflags):(w_iflags);
 
 
`ifdef  OPT_CIS
`ifdef  OPT_CIS
        reg     r_op_phase;
        reg     r_op_phase;
        initial r_op_phase = 1'b0;
        initial r_op_phase = 1'b0;
Line 1085... Line 1034...
                                // if we're not piping this new instruction.
                                // if we're not piping this new instruction.
                                // If we were piping, the pipe logic in the
                                // If we were piping, the pipe logic in the
                                // decode circuit has told us that the hazard
                                // decode circuit has told us that the hazard
                                // is clear, so we're okay then.
                                // is clear, so we're okay then.
                                //
                                //
                                ((~dcd_zI)&&(
                                ((!dcd_zI)&&(
                                        ((op_R == dcd_B)&&(op_wR))
                                        ((op_R == dcd_B)&&(op_wR))
                                        ||((mem_rdbusy)&&(~dcd_pipe))
                                        ||((mem_rdbusy)&&(!dcd_pipe))
                                        ))
                                        ))
                                // Stall following any instruction that will
                                // Stall following any instruction that will
                                // set the flags, if we're going to need the
                                // set the flags, if we're going to need the
                                // flags (CC) register for op_B.
                                // flags (CC) register for op_B.
                                ||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc))
                                ||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc))
                                // Stall on any ongoing memory operation that
                                // Stall on any ongoing memory operation that
                                // will write to op_B -- captured above
                                // will write to op_B -- captured above
                                // ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcd_B)&&(~dcd_zI))
                                // ||((mem_busy)&&(!mem_we)&&(mem_last_reg==dcd_B)&&(!dcd_zI))
                                )
                                )
                        ||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd));
                        ||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd));
        assign  dcd_F_stall = ((~dcd_F[3])
        assign  dcd_F_stall = ((!dcd_F[3])
                                        ||((dcd_rA)&&(dcd_Acc))
                                        ||((dcd_rA)&&(dcd_Acc))
                                        ||((dcd_rB)&&(dcd_Bcc)))
                                        ||((dcd_rB)&&(dcd_Bcc)))
                                        &&(op_valid)&&(op_Rcc);
                                        &&(op_valid)&&(op_Rcc);
                                // &&(dcd_valid) is checked for elsewhere
                                // &&(dcd_valid) is checked for elsewhere
`else
`else
Line 1167... Line 1116...
                end else if (alu_ce)
                end else if (alu_ce)
                begin
                begin
                        // alu_reg <= op_R;
                        // alu_reg <= op_R;
                        alu_wR  <= (op_wR)&&(set_cond);
                        alu_wR  <= (op_wR)&&(set_cond);
                        alu_wF  <= (op_wF)&&(set_cond);
                        alu_wF  <= (op_wF)&&(set_cond);
                end else if (~alu_busy) begin
                end else if (!alu_busy) begin
                        // These are strobe signals, so clear them if not
                        // These are strobe signals, so clear them if not
                        // set for any particular clock
                        // set for any particular clock
                        alu_wR <= (i_halt)&&(i_dbg_we);
                        alu_wR <= (i_halt)&&(i_dbg_we);
                        alu_wF <= 1'b0;
                        alu_wF <= 1'b0;
                end
                end
Line 1207... Line 1156...
        // DEBUG Register write access starts here
        // DEBUG Register write access starts here
        //
        //
        reg             dbgv;
        reg             dbgv;
        initial dbgv = 1'b0;
        initial dbgv = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
                dbgv <= (!i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
        reg     [31:0]   dbg_val;
        reg     [31:0]   dbg_val;
        always @(posedge i_clk)
        always @(posedge i_clk)
                dbg_val <= i_dbg_data;
                dbg_val <= i_dbg_data;
`ifdef  OPT_NO_USERMODE
`ifdef  OPT_NO_USERMODE
        assign  alu_gie = 1'b0;
        assign  alu_gie = 1'b0;
Line 1230... Line 1179...
 
 
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        reg     [(AW-1):0]       r_alu_pc;
        reg     [(AW-1):0]       r_alu_pc;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((adf_ce_unconditional)
                if ((adf_ce_unconditional)
                        ||((master_ce)&&(op_valid_mem)&&(~clear_pipeline)
                        ||((master_ce)&&(op_valid_mem)&&(!clear_pipeline)
                                &&(~mem_stalled)))
                                &&(!mem_stalled)))
                        r_alu_pc  <= op_pc;
                        r_alu_pc  <= op_pc;
        assign  alu_pc = r_alu_pc;
        assign  alu_pc = r_alu_pc;
`else
`else
        assign  alu_pc = op_pc;
        assign  alu_pc = op_pc;
`endif
`endif
Line 1254... Line 1203...
        initial r_alu_pc_valid = 1'b0;
        initial r_alu_pc_valid = 1'b0;
        initial mem_pc_valid = 1'b0;
        initial mem_pc_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (clear_pipeline)
                if (clear_pipeline)
                        r_alu_pc_valid <= 1'b0;
                        r_alu_pc_valid <= 1'b0;
                else if ((adf_ce_unconditional)&&(!op_phase)) //Includes&&(~alu_clear_pipeline)
                else if ((adf_ce_unconditional)&&(!op_phase))
                        r_alu_pc_valid <= 1'b1;
                        r_alu_pc_valid <= 1'b1;
                else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
                else if (((!alu_busy)&&(!div_busy)&&(!fpu_busy))||(clear_pipeline))
                        r_alu_pc_valid <= 1'b0;
                        r_alu_pc_valid <= 1'b0;
        assign  alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
        assign  alu_pc_valid = (r_alu_pc_valid)&&((!alu_busy)&&(!div_busy)&&(!fpu_busy));
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        mem_pc_valid <= 1'b0;
                        mem_pc_valid <= 1'b0;
                else
                else
                        mem_pc_valid <= (mem_ce);
                        mem_pc_valid <= (mem_ce);
Line 1324... Line 1273...
                                mem_stb_gbl, mem_stb_lcl,
                                mem_stb_gbl, mem_stb_lcl,
                                mem_we, mem_addr, mem_data, mem_sel,
                                mem_we, mem_addr, mem_data, mem_sel,
                                mem_ack, mem_stall, mem_err, i_wb_data);
                                mem_ack, mem_stall, mem_err, i_wb_data);
 
 
`else // PIPELINED_BUS_ACCESS
`else // PIPELINED_BUS_ACCESS
        memops  #(AW,IMPLEMENT_LOCK,WITH_LOCAL_BUS) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
        memops  #(AW,IMPLEMENT_LOCK,WITH_LOCAL_BUS) domem(i_clk, i_rst,
 
                        (mem_ce)&&(set_cond), bus_lock,
                                (op_opn[2:0]), op_Bv, op_Av, op_R,
                                (op_opn[2:0]), op_Bv, op_Av, op_R,
                                mem_busy,
                                mem_busy,
                                mem_valid, bus_err, mem_wreg, mem_result,
                                mem_valid, bus_err, mem_wreg, mem_result,
                        mem_cyc_gbl, mem_cyc_lcl,
                        mem_cyc_gbl, mem_cyc_lcl,
                                mem_stb_gbl, mem_stb_lcl,
                                mem_stb_gbl, mem_stb_lcl,
                                mem_we, mem_addr, mem_data, mem_sel,
                                mem_we, mem_addr, mem_data, mem_sel,
                                mem_ack, mem_stall, mem_err, i_wb_data);
                                mem_ack, mem_stall, mem_err, i_wb_data);
        assign  mem_pipe_stalled = 1'b0;
        assign  mem_pipe_stalled = 1'b0;
`endif // PIPELINED_BUS_ACCESS
`endif // PIPELINED_BUS_ACCESS
        assign  mem_rdbusy = ((mem_busy)&&(~mem_we));
        assign  mem_rdbusy = ((mem_busy)&&(!mem_we));
 
 
        // Either the prefetch or the instruction gets the memory bus, but
        // Either the prefetch or the instruction gets the memory bus, but
        // never both.
        // never both.
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
                // Memory access to the arbiter, priority position
                // Memory access to the arbiter, priority position
Line 1387... Line 1337...
        //      Note that the flags needed to be checked before issuing the
        //      Note that the flags needed to be checked before issuing the
        //      bus instruction, so they don't need to be checked here.
        //      bus instruction, so they don't need to be checked here.
        //      Further, alu_wR includes (set_cond), so we don't need to
        //      Further, alu_wR includes (set_cond), so we don't need to
        //      check for that here either.
        //      check for that here either.
        assign  wr_reg_ce = (dbgv)||(mem_valid)
        assign  wr_reg_ce = (dbgv)||(mem_valid)
                                ||((~clear_pipeline)&&(~alu_illegal)
                                ||((!clear_pipeline)&&(!alu_illegal)
                                        &&(((alu_wR)&&(alu_valid))
                                        &&(((alu_wR)&&(alu_valid))
                                                ||(div_valid)||(fpu_valid)));
                                                ||(div_valid)||(fpu_valid)));
        // Which register shall be written?
        // Which register shall be written?
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
        //              One or PC, one for CC, and one for GIE match
        //              One or PC, one for CC, and one for GIE match
Line 1429... Line 1379...
 
 
        //
        //
        // Write back to the condition codes/flags register ...
        // Write back to the condition codes/flags register ...
        // When shall we write to our flags register?  alu_wF already
        // When shall we write to our flags register?  alu_wF already
        // includes the set condition ...
        // includes the set condition ...
        assign  wr_flags_ce = ((alu_wF)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
        assign  wr_flags_ce = ((alu_wF)||(div_valid)||(fpu_valid))&&(!clear_pipeline)&&(!alu_illegal);
        assign  w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag,
        assign  w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag,
                        udiv_err_flag, ubus_err_flag, trap, ill_err_u,
                        udiv_err_flag, ubus_err_flag, trap, ill_err_u,
                        ubreak, step, 1'b1, sleep,
                        ubreak, step, 1'b1, sleep,
                        ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
                        ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
        assign  w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag,
        assign  w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag,
                        idiv_err_flag, ibus_err_flag, trap, ill_err_i,
                        idiv_err_flag, ibus_err_flag, trap, ill_err_i,
                        break_en, 1'b0, 1'b0, sleep,
                        break_en, 1'b0, 1'b0, sleep,
                        ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
                        ((wr_flags_ce)&&(!alu_gie))?alu_flags:iflags };
 
 
 
 
        // What value to write?
        // What value to write?
        always @(posedge i_clk)
        always @(posedge i_clk)
                // If explicitly writing the register itself
                // If explicitly writing the register itself
Line 1453... Line 1403...
                                : alu_flags);
                                : alu_flags);
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((wr_reg_ce)&&(wr_write_scc))
                if ((wr_reg_ce)&&(wr_write_scc))
                        iflags <= wr_gpreg_vl[3:0];
                        iflags <= wr_gpreg_vl[3:0];
                else if ((wr_flags_ce)&&(~alu_gie))
                else if ((wr_flags_ce)&&(!alu_gie))
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
                                : alu_flags);
                                : alu_flags);
 
 
        // The 'break' enable  bit.  This bit can only be set from supervisor
        // The 'break' enable  bit.  This bit can only be set from supervisor
        // mode.  It control what the CPU does upon encountering a break
        // mode.  It control what the CPU does upon encountering a break
Line 1484... Line 1434...
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        reg     r_break_pending;
        reg     r_break_pending;
 
 
        initial r_break_pending = 1'b0;
        initial r_break_pending = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((clear_pipeline)||(~op_valid))
                if ((clear_pipeline)||(!op_valid))
                        r_break_pending <= 1'b0;
                        r_break_pending <= 1'b0;
                else if (op_break)
                else if (op_break)
                        r_break_pending <= (~alu_busy)&&(~div_busy)&&(~fpu_busy)&&(~mem_busy)&&(!wr_reg_ce);
                        r_break_pending <= (!alu_busy)&&(!div_busy)&&(!fpu_busy)&&(!mem_busy)&&(!wr_reg_ce);
                else
                else
                        r_break_pending <= 1'b0;
                        r_break_pending <= 1'b0;
        assign  break_pending = r_break_pending;
        assign  break_pending = r_break_pending;
`else
`else
        assign  break_pending = op_break;
        assign  break_pending = op_break;
`endif
`endif
 
 
 
 
        assign  o_break = ((break_en)||(~op_gie))&&(break_pending)
        assign  o_break = ((break_en)||(!op_gie))&&(break_pending)
                                &&(~clear_pipeline)
                                &&(!clear_pipeline)
                        ||((~alu_gie)&&(bus_err))
                        ||((!alu_gie)&&(bus_err))
                        ||((~alu_gie)&&(div_error))
                        ||((!alu_gie)&&(div_error))
                        ||((~alu_gie)&&(fpu_error))
                        ||((!alu_gie)&&(fpu_error))
                        ||((~alu_gie)&&(alu_illegal)&&(!clear_pipeline));
                        ||((!alu_gie)&&(alu_illegal)&&(!clear_pipeline));
 
 
        // The sleep register.  Setting the sleep register causes the CPU to
        // The sleep register.  Setting the sleep register causes the CPU to
        // sleep until the next interrupt.  Setting the sleep register within
        // sleep until the next interrupt.  Setting the sleep register within
        // interrupt mode causes the processor to halt until a reset.  This is
        // interrupt mode causes the processor to halt until a reset.  This is
        // a panic/fault halt.  The trick is that you cannot be allowed to
        // a panic/fault halt.  The trick is that you cannot be allowed to
Line 1518... Line 1468...
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_sleep_is_halt <= 1'b0;
                        r_sleep_is_halt <= 1'b0;
                else if ((wr_reg_ce)&&(wr_write_cc)
                else if ((wr_reg_ce)&&(wr_write_cc)
                                &&(wr_spreg_vl[`CPU_SLEEP_BIT])
                                &&(wr_spreg_vl[`CPU_SLEEP_BIT])
                                &&(~wr_spreg_vl[`CPU_GIE_BIT]))
                                &&(!wr_spreg_vl[`CPU_GIE_BIT]))
                        r_sleep_is_halt <= 1'b1;
                        r_sleep_is_halt <= 1'b1;
 
 
        // Trying to switch to user mode, either via a WAIT or an RTU
        // Trying to switch to user mode, either via a WAIT or an RTU
        // instruction will cause the CPU to sleep until an interrupt, in
        // instruction will cause the CPU to sleep until an interrupt, in
        // the NO-USERMODE build.
        // the NO-USERMODE build.
Line 1534... Line 1484...
                        sleep <= 1'b1;
                        sleep <= 1'b1;
`else
`else
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(w_switch_to_interrupt))
                if ((i_rst)||(w_switch_to_interrupt))
                        sleep <= 1'b0;
                        sleep <= 1'b0;
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
                else if ((wr_reg_ce)&&(wr_write_cc)&&(!alu_gie))
                        // In supervisor mode, we have no protections.  The
                        // In supervisor mode, we have no protections.  The
                        // supervisor can set the sleep bit however he wants.
                        // supervisor can set the sleep bit however he wants.
                        // Well ... not quite.  Switching to user mode and
                        // Well ... not quite.  Switching to user mode and
                        // sleep mode shouold only be possible if the interrupt
                        // sleep mode shouold only be possible if the interrupt
                        // flag isn't set.
                        // flag isn't set.
                        //      Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
                        //      Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
                        //              don't set the sleep bit
                        //              don't set the sleep bit
                        //      otherwise however it would o.w. be set
                        //      otherwise however it would o.w. be set
                        sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
                        sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
                                &&((~i_interrupt)||(~wr_spreg_vl[`CPU_GIE_BIT]));
                                &&((!i_interrupt)||(!wr_spreg_vl[`CPU_GIE_BIT]));
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
                        // In user mode, however, you can only set the sleep
                        // In user mode, however, you can only set the sleep
                        // mode while remaining in user mode.  You can't switch
                        // mode while remaining in user mode.  You can't switch
                        // to sleep mode *and* supervisor mode at the same
                        // to sleep mode *and* supervisor mode at the same
                        // time, lest you halt the CPU.
                        // time, lest you halt the CPU.
Line 1556... Line 1506...
`endif
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        step <= 1'b0;
                        step <= 1'b0;
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_write_ucc))
                else if ((wr_reg_ce)&&(!alu_gie)&&(wr_write_ucc))
                        step <= wr_spreg_vl[`CPU_STEP_BIT];
                        step <= wr_spreg_vl[`CPU_STEP_BIT];
 
 
        // The GIE register.  Only interrupts can disable the interrupt register
        // The GIE register.  Only interrupts can disable the interrupt register
`ifdef  OPT_NO_USERMODE
`ifdef  OPT_NO_USERMODE
        assign  w_switch_to_interrupt    = 1'b0;
        assign  w_switch_to_interrupt    = 1'b0;
        assign  w_release_from_interrupt = 1'b0;
        assign  w_release_from_interrupt = 1'b0;
`else
`else
        assign  w_switch_to_interrupt = (gie)&&(
        assign  w_switch_to_interrupt = (gie)&&(
                        // On interrupt (obviously)
                        // On interrupt (obviously)
                        ((i_interrupt)&&(~alu_phase)&&(~bus_lock))
                        ((i_interrupt)&&(!alu_phase)&&(!bus_lock))
                        // If we are stepping the CPU
                        // If we are stepping the CPU
                        ||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
                        ||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(!alu_phase)&&(!bus_lock))
                        // If we encounter a break instruction, if the break
                        // If we encounter a break instruction, if the break
                        //      enable isn't set.
                        //      enable isn't set.
                        ||((master_ce)&&(break_pending)&&(~break_en))
                        ||((master_ce)&&(break_pending)&&(!break_en))
                        // On an illegal instruction
                        // On an illegal instruction
                        ||((alu_illegal)&&(!clear_pipeline))
                        ||((alu_illegal)&&(!clear_pipeline))
                        // On division by zero.  If the divide isn't
                        // On division by zero.  If the divide isn't
                        // implemented, div_valid and div_error will be short
                        // implemented, div_valid and div_error will be short
                        // circuited and that logic will be bypassed
                        // circuited and that logic will be bypassed
Line 1585... Line 1535...
                        // also set as well, else this will fail.
                        // also set as well, else this will fail.
                        ||(fpu_error)
                        ||(fpu_error)
                        //
                        //
                        ||(bus_err)
                        ||(bus_err)
                        // If we write to the CC register
                        // If we write to the CC register
                        ||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
                        ||((wr_reg_ce)&&(!wr_spreg_vl[`CPU_GIE_BIT])
                                &&(wr_reg_id[4])&&(wr_write_cc))
                                &&(wr_reg_id[4])&&(wr_write_cc))
                        );
                        );
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
        assign  w_release_from_interrupt = (!gie)&&(!i_interrupt)
                        // Then if we write the sCC register
                        // Then if we write the sCC register
                        &&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
                        &&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
                                &&(wr_write_scc))
                                &&(wr_write_scc))
                        );
                        );
`endif
`endif
Line 1621... Line 1571...
 
 
        initial r_trap = 1'b0;
        initial r_trap = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(w_release_from_interrupt))
                if ((i_rst)||(w_release_from_interrupt))
                        r_trap <= 1'b0;
                        r_trap <= 1'b0;
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
                else if ((alu_gie)&&(wr_reg_ce)&&(!wr_spreg_vl[`CPU_GIE_BIT])
                                &&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
                                &&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
                        r_trap <= 1'b1;
                        r_trap <= 1'b1;
                else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie))
                else if ((wr_reg_ce)&&(wr_write_ucc)&&(!alu_gie))
                        r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
                        r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
 
 
        reg     r_ubreak;
        reg     r_ubreak;
 
 
        initial r_ubreak = 1'b0;
        initial r_ubreak = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(w_release_from_interrupt))
                if ((i_rst)||(w_release_from_interrupt))
                        r_ubreak <= 1'b0;
                        r_ubreak <= 1'b0;
                else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
                else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
                        r_ubreak <= 1'b1;
                        r_ubreak <= 1'b1;
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
                else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
                        r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
                        r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
 
 
        assign  trap = r_trap;
        assign  trap = r_trap;
        assign  ubreak = r_ubreak;
        assign  ubreak = r_ubreak;
`endif
`endif
Line 1651... Line 1601...
                if (i_rst)
                if (i_rst)
                        ill_err_i <= 1'b0;
                        ill_err_i <= 1'b0;
                // Only the debug interface can clear this bit
                // Only the debug interface can clear this bit
                else if ((dbgv)&&(wr_write_scc))
                else if ((dbgv)&&(wr_write_scc))
                        ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
                        ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
                else if ((alu_illegal)&&(~alu_gie)&&(!clear_pipeline))
                else if ((alu_illegal)&&(!alu_gie)&&(!clear_pipeline))
                        ill_err_i <= 1'b1;
                        ill_err_i <= 1'b1;
 
 
`ifdef  OPT_NO_USERMODE
`ifdef  OPT_NO_USERMODE
        assign  ill_err_u = 1'b0;
        assign  ill_err_u = 1'b0;
`else
`else
Line 1667... Line 1617...
                // or reset
                // or reset
                if ((i_rst)||(w_release_from_interrupt))
                if ((i_rst)||(w_release_from_interrupt))
                        r_ill_err_u <= 1'b0;
                        r_ill_err_u <= 1'b0;
                // If the supervisor (or debugger) writes to this register,
                // If the supervisor (or debugger) writes to this register,
                // clearing the bit, then clear it
                // clearing the bit, then clear it
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
                else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
                        r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
                        r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
                else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline))
                else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline))
                        r_ill_err_u <= 1'b1;
                        r_ill_err_u <= 1'b1;
 
 
        assign  ill_err_u = r_ill_err_u;
        assign  ill_err_u = r_ill_err_u;
Line 1686... Line 1636...
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        ibus_err_flag <= 1'b0;
                        ibus_err_flag <= 1'b0;
                else if ((dbgv)&&(wr_write_scc))
                else if ((dbgv)&&(wr_write_scc))
                        ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
                        ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
                else if ((bus_err)&&(~alu_gie))
                else if ((bus_err)&&(!alu_gie))
                        ibus_err_flag <= 1'b1;
                        ibus_err_flag <= 1'b1;
        // User bus error flag -- if ever set, it will cause an interrupt to
        // User bus error flag -- if ever set, it will cause an interrupt to
        // supervisor mode.
        // supervisor mode.
`ifdef  OPT_NO_USERMODE
`ifdef  OPT_NO_USERMODE
        assign  ubus_err_flag = 1'b0;
        assign  ubus_err_flag = 1'b0;
Line 1699... Line 1649...
 
 
        initial r_ubus_err_flag = 1'b0;
        initial r_ubus_err_flag = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(w_release_from_interrupt))
                if ((i_rst)||(w_release_from_interrupt))
                        r_ubus_err_flag <= 1'b0;
                        r_ubus_err_flag <= 1'b0;
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
                else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
                        r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
                        r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
                else if ((bus_err)&&(alu_gie))
                else if ((bus_err)&&(alu_gie))
                        r_ubus_err_flag <= 1'b1;
                        r_ubus_err_flag <= 1'b1;
 
 
        assign  ubus_err_flag = r_ubus_err_flag;
        assign  ubus_err_flag = r_ubus_err_flag;
Line 1721... Line 1671...
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (i_rst)
                        if (i_rst)
                                r_idiv_err_flag <= 1'b0;
                                r_idiv_err_flag <= 1'b0;
                        else if ((dbgv)&&(wr_write_scc))
                        else if ((dbgv)&&(wr_write_scc))
                                r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
                                r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
                        else if ((div_error)&&(~alu_gie))
                        else if ((div_error)&&(!alu_gie))
                                r_idiv_err_flag <= 1'b1;
                                r_idiv_err_flag <= 1'b1;
 
 
                assign  idiv_err_flag = r_idiv_err_flag;
                assign  idiv_err_flag = r_idiv_err_flag;
`ifdef  OPT_NO_USERMODE
`ifdef  OPT_NO_USERMODE
                assign  udiv_err_flag = 1'b0;
                assign  udiv_err_flag = 1'b0;
Line 1734... Line 1684...
                // cause a sudden switch interrupt to supervisor mode.
                // cause a sudden switch interrupt to supervisor mode.
                initial r_udiv_err_flag = 1'b0;
                initial r_udiv_err_flag = 1'b0;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if ((i_rst)||(w_release_from_interrupt))
                        if ((i_rst)||(w_release_from_interrupt))
                                r_udiv_err_flag <= 1'b0;
                                r_udiv_err_flag <= 1'b0;
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
                        else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)
                                        &&(wr_write_ucc))
                                        &&(wr_write_ucc))
                                r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
                                r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
                        else if ((div_error)&&(alu_gie))
                        else if ((div_error)&&(alu_gie))
                                r_udiv_err_flag <= 1'b1;
                                r_udiv_err_flag <= 1'b1;
 
 
Line 1759... Line 1709...
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (i_rst)
                        if (i_rst)
                                r_ifpu_err_flag <= 1'b0;
                                r_ifpu_err_flag <= 1'b0;
                        else if ((dbgv)&&(wr_write_scc))
                        else if ((dbgv)&&(wr_write_scc))
                                r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
                                r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
                        else if ((fpu_error)&&(fpu_valid)&&(!alu_gie))
                                r_ifpu_err_flag <= 1'b1;
                                r_ifpu_err_flag <= 1'b1;
                // User floating point error flag -- if ever set, it will cause
                // User floating point error flag -- if ever set, it will cause
                // a sudden switch interrupt to supervisor mode.
                // a sudden switch interrupt to supervisor mode.
                initial r_ufpu_err_flag = 1'b0;
                initial r_ufpu_err_flag = 1'b0;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if ((i_rst)&&(w_release_from_interrupt))
                        if ((i_rst)&&(w_release_from_interrupt))
                                r_ufpu_err_flag <= 1'b0;
                                r_ufpu_err_flag <= 1'b0;
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
                        else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)
                                        &&(wr_write_ucc))
                                        &&(wr_write_ucc))
                                r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
                                r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
                                r_ufpu_err_flag <= 1'b1;
                                r_ufpu_err_flag <= 1'b1;
 
 
Line 1787... Line 1737...
 
 
        initial r_ihalt_phase = 0;
        initial r_ihalt_phase = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_ihalt_phase <= 1'b0;
                        r_ihalt_phase <= 1'b0;
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
                else if ((!alu_gie)&&(alu_pc_valid)&&(!clear_pipeline))
                        r_ihalt_phase <= alu_phase;
                        r_ihalt_phase <= alu_phase;
 
 
        assign  ihalt_phase = r_ihalt_phase;
        assign  ihalt_phase = r_ihalt_phase;
 
 
`ifdef  OPT_NO_USERMODE
`ifdef  OPT_NO_USERMODE
Line 1803... Line 1753...
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(w_release_from_interrupt))
                if ((i_rst)||(w_release_from_interrupt))
                        r_uhalt_phase <= 1'b0;
                        r_uhalt_phase <= 1'b0;
                else if ((alu_gie)&&(alu_pc_valid))
                else if ((alu_gie)&&(alu_pc_valid))
                        r_uhalt_phase <= alu_phase;
                        r_uhalt_phase <= alu_phase;
                else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc))
                else if ((!alu_gie)&&(wr_reg_ce)&&(wr_write_ucc))
                        r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT];
                        r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT];
 
 
        assign  uhalt_phase = r_uhalt_phase;
        assign  uhalt_phase = r_uhalt_phase;
`endif
`endif
`else
`else
Line 1820... Line 1770...
        //      We support two: upc and ipc.  If the instruction is normal,
        //      We support two: upc and ipc.  If the instruction is normal,
        // we increment upc, if interrupt level we increment ipc.  If
        // we increment upc, if interrupt level we increment ipc.  If
        // the instruction writes the PC, we write whichever PC is appropriate.
        // the instruction writes the PC, we write whichever PC is appropriate.
        //
        //
        // Do we need to all our partial results from the pipeline?
        // Do we need to all our partial results from the pipeline?
        // What happens when the pipeline has gie and ~gie instructions within
        // What happens when the pipeline has gie and !gie instructions within
        // it?  Do we clear both?  What if a gie instruction tries to clear
        // it?  Do we clear both?  What if a gie instruction tries to clear
        // a non-gie instruction?
        // a non-gie instruction?
`ifdef  OPT_NO_USERMODE
`ifdef  OPT_NO_USERMODE
        assign  upc = {(AW+2){1'b0}};
        assign  upc = {(AW+2){1'b0}};
`else
`else
Line 1832... Line 1782...
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
                        r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
                        r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
                else if ((alu_gie)&&
                else if ((alu_gie)&&
                                (((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal))
                                (((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal))
                                ||(mem_pc_valid)))
                                ||(mem_pc_valid)))
                        r_upc <= { alu_pc, 2'b00 };
                        r_upc <= { alu_pc, 2'b00 };
        assign  upc = r_upc;
        assign  upc = r_upc;
`endif
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        ipc <= { RESET_BUS_ADDRESS, 2'b00 };
                        ipc <= { RESET_BUS_ADDRESS, 2'b00 };
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
                else if ((wr_reg_ce)&&(!wr_reg_id[4])&&(wr_write_pc))
                        ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
                        ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
                else if ((!alu_gie)&&(!alu_phase)&&
                else if ((!alu_gie)&&(!alu_phase)&&
                                (((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal))
                                (((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal))
                                ||(mem_pc_valid)))
                                ||(mem_pc_valid)))
                        ipc <= { alu_pc, 2'b00 };
                        ipc <= { alu_pc, 2'b00 };
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        pf_pc <= { RESET_BUS_ADDRESS, 2'b00 };
                        pf_pc <= { RESET_BUS_ADDRESS, 2'b00 };
                else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache)))
                else if ((w_switch_to_interrupt)||((!gie)&&(w_clear_icache)))
                        pf_pc <= { ipc[(AW+1):2], 2'b00 };
                        pf_pc <= { ipc[(AW+1):2], 2'b00 };
                else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache)))
                else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache)))
                        pf_pc <= { upc[(AW+1):2], 2'b00 };
                        pf_pc <= { upc[(AW+1):2], 2'b00 };
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                        pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
                        pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
`ifdef  OPT_PIPELINED
                else if ((dcd_early_branch)&&(!clear_pipeline))
                else if ((dcd_early_branch)&&(~clear_pipeline))
 
                        pf_pc <= { dcd_branch_pc + 1'b1, 2'b00 };
                        pf_pc <= { dcd_branch_pc + 1'b1, 2'b00 };
                else if ((new_pc)||((!pf_stalled)&&(pf_valid)))
                else if ((new_pc)||((!pf_stalled)&&(pf_valid)))
                        pf_pc <= { pf_pc[(AW+1):2] + {{(AW-1){1'b0}},1'b1}, 2'b00 };
                        pf_pc <= { pf_pc[(AW+1):2] + {{(AW-1){1'b0}},1'b1}, 2'b00 };
`else
 
                else if ((alu_gie==gie)&&(
 
                                ((alu_pc_valid)&&(~clear_pipeline))
 
                                ||(mem_pc_valid)))
 
                        pf_pc <= { alu_pc[(AW-1):0], 2'b00 };
 
`endif
 
 
 
`ifdef  OPT_PIPELINED
        // If we aren't pipelined, or equivalently if we have no cache, these
 
        // instructions will get quietly (or not so quietly) ignored by the
 
        // optimizer.
        reg     r_clear_icache;
        reg     r_clear_icache;
        initial r_clear_icache = 1'b1;
        initial r_clear_icache = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_pf_cache))
                if ((i_rst)||(i_clear_pf_cache))
                        r_clear_icache <= 1'b1;
                        r_clear_icache <= 1'b1;
                else if ((wr_reg_ce)&&(wr_write_scc))
                else if ((wr_reg_ce)&&(wr_write_scc))
                        r_clear_icache <=  wr_spreg_vl[`CPU_CLRCACHE_BIT];
                        r_clear_icache <=  wr_spreg_vl[`CPU_CLRCACHE_BIT];
                else
                else
                        r_clear_icache <= 1'b0;
                        r_clear_icache <= 1'b0;
        assign  w_clear_icache = r_clear_icache;
        assign  w_clear_icache = r_clear_icache;
`else
 
        assign  w_clear_icache = i_clear_pf_cache;
 
`endif
 
 
 
        initial new_pc = 1'b1;
        initial new_pc = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(w_clear_icache))
                if ((i_rst)||(w_clear_icache))
                        new_pc <= 1'b1;
                        new_pc <= 1'b1;
Line 1947... Line 1889...
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_halted <= (i_halt)&&(
                r_halted <= (i_halt)&&(
                        // To be halted, any long lasting instruction must
                        // To be halted, any long lasting instruction must
                        // be completed.
                        // be completed.
                        (~pf_cyc)&&(~mem_busy)&&(~alu_busy)
                        (!pf_cyc)&&(!mem_busy)&&(!alu_busy)
                                &&(~div_busy)&&(~fpu_busy)
                                &&(!div_busy)&&(!fpu_busy)
                        // Operations must either be valid, or illegal
                        // Operations must either be valid, or illegal
                        &&((op_valid)||(i_rst)||(dcd_illegal))
                        &&((op_valid)||(i_rst)||(dcd_illegal))
                        // Decode stage must be either valid, in reset, or ill
                        // Decode stage must be either valid, in reset, or ill
                        &&((dcd_valid)||(i_rst)||(pf_illegal)));
                        &&((dcd_valid)||(i_rst)||(pf_illegal)));
`else
`else
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_halted <= (i_halt)&&((op_valid)||(i_rst));
                r_halted <= (i_halt)&&((op_valid)||(i_rst));
`endif
`endif
        assign  o_dbg_stall = ~r_halted;
        assign  o_dbg_stall = !r_halted;
 
 
        //
        //
        //
        //
        // Produce accounting outputs: Account for any CPU stalls, so we can
        // Produce accounting outputs: Account for any CPU stalls, so we can
        // later evaluate how well we are doing.
        // later evaluate how well we are doing.
        //
        //
        //
        //
        assign  o_op_stall = (master_ce)&&(op_stall);
        assign  o_op_stall = (master_ce)&&(op_stall);
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
        assign  o_pf_stall = (master_ce)&&(!pf_valid);
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
        assign  o_i_count  = (alu_pc_valid)&&(!clear_pipeline);
 
 
`ifdef  DEBUG_SCOPE
`ifdef  DEBUG_SCOPE
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_debug <= {
                o_debug <= {
                /*
                /*

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