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[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Diff between revs 2 and 3

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Rev 2 Rev 3
Line 202... Line 202...
        reg     [1:0]    opA_cc, opB_cc;
        reg     [1:0]    opA_cc, opB_cc;
        reg     [31:0]   r_opA, r_opB, op_pc;
        reg     [31:0]   r_opA, r_opB, op_pc;
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        reg             opR_wr, opM, opF_wr, op_gie,
        reg             opR_wr, opM, opF_wr, op_gie,
                        opA_rd, opB_rd;
                        opA_rd, opB_rd;
        reg     [7:0]    opFl;
        wire    [7:0]    opFl;
        // reg  [6:0]   r_opF;
        reg     [6:0]    r_opF;
        wire    [8:0]    opF;
        wire    [8:0]    opF;
        wire            op_ce;
        wire            op_ce;
 
 
 
 
 
 
Line 305... Line 305...
                                        pf_valid,
                                        pf_valid,
                                pf_cyc, pf_stb, pf_we, pf_addr,
                                pf_cyc, pf_stb, pf_we, pf_addr,
                                        pf_data,
                                        pf_data,
                                pf_ack, pf_stall, i_wb_data);
                                pf_ack, pf_stall, i_wb_data);
`else // Pipe fetch
`else // Pipe fetch
        pipefetch       pf(i_clk, i_rst, new_pc, ~dcd_stalled, pf_pc,
        pipefetch       #(RESET_ADDRESS)
 
                        pf(i_clk, i_rst, new_pc, ~dcd_stalled, pf_pc,
                                        instruction, instruction_pc, pf_valid,
                                        instruction, instruction_pc, pf_valid,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_ack, pf_stall, i_wb_data);
                                        pf_ack, pf_stall, i_wb_data,
 
                                mem_cyc);
        assign  instruction_gie = gie;
        assign  instruction_gie = gie;
`endif
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
Line 455... Line 457...
        // conditions check whether bits are on, and those are the only two
        // conditions check whether bits are on, and those are the only two
        // conditions checking those bits.  Therefore, Vivado complains that
        // conditions checking those bits.  Therefore, Vivado complains that
        // these two bits are redundant.  Hence the convoluted expression
        // these two bits are redundant.  Hence the convoluted expression
        // below, arriving at what we finally want in the (now wire net)
        // below, arriving at what we finally want in the (now wire net)
        // opF.
        // opF.
 
`define NEWCODE
`ifdef  NEWCODE
`ifdef  NEWCODE
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                begin // Set the flag condition codes
                begin // Set the flag condition codes
                        case(dcdF[2:0])
                        case(dcdF[2:0])
Line 577... Line 580...
                                &&((opvalid)&&(opR[3:0] == `CPU_CC_REG))
                                &&((opvalid)&&(opR[3:0] == `CPU_CC_REG))
                        ||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr)));
                        ||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr)));
        assign  opA = { r_opA[31:8], ((opA_cc[0]) ?
        assign  opA = { r_opA[31:8], ((opA_cc[0]) ?
                        ((opA_cc[1])?w_uflags:w_iflags) : r_opA[7:0]) };
                        ((opA_cc[1])?w_uflags:w_iflags) : r_opA[7:0]) };
        assign  opB = { r_opB[31:8], ((opB_cc[0]) ?
        assign  opB = { r_opB[31:8], ((opB_cc[0]) ?
                        ((opA_cc[1])?w_uflags:w_iflags) : r_opB[7:0]) };
                        ((opB_cc[1])?w_uflags:w_iflags) : r_opB[7:0]) };
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #4 :: Apply Instruction
        //      PIPELINE STAGE #4 :: Apply Instruction
        //
        //

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