| Line 114... |
Line 114... |
//
|
//
|
// Slice LUTs ZipSystem ZipCPU
|
// Slice LUTs ZipSystem ZipCPU
|
// Single Fetching 2521 1734
|
// Single Fetching 2521 1734
|
// Pipelined fetching 2796 2046
|
// Pipelined fetching 2796 2046
|
//
|
//
|
// `define SINGLE_FETCH
|
// `define OPT_SINGLE_FETCH
|
//
|
//
|
//
|
//
|
//
|
//
|
`define CPU_CC_REG 4'he
|
`define CPU_CC_REG 4'he
|
`define CPU_PC_REG 4'hf
|
`define CPU_PC_REG 4'hf
|
| Line 126... |
Line 126... |
`define CPU_BREAK_BIT 7
|
`define CPU_BREAK_BIT 7
|
`define CPU_STEP_BIT 6
|
`define CPU_STEP_BIT 6
|
`define CPU_GIE_BIT 5
|
`define CPU_GIE_BIT 5
|
`define CPU_SLEEP_BIT 4
|
`define CPU_SLEEP_BIT 4
|
// Compile time defines
|
// Compile time defines
|
// `define SINGLE_FETCH
|
// (Currently unused)
|
`define NG_CONDITIONAL_FLAGS
|
// `define OPT_SINGLE_FETCH
|
`define NG_PRECLEAR_BUS // 0.61 w/ or w/o
|
// (Best path--define these!)
|
// `define NG_BRANCH_DELAY_SLOT
|
`define OPT_CONDITIONAL_FLAGS
|
`define NG_ILLEGAL_INSTRUCTION
|
`define OPT_PRECLEAR_BUS
|
`define NG_EARLY_BRANCHING // 0.60 w/, 0.61 w/o ????
|
`define OPT_ILLEGAL_INSTRUCTION
|
|
`define OPT_EARLY_BRANCHING
|
|
`define OPT_PIPELINED_BUS_ACCESS
|
module zipcpu(i_clk, i_rst, i_interrupt,
|
module zipcpu(i_clk, i_rst, i_interrupt,
|
// Debug interface
|
// Debug interface
|
i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
|
i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
|
o_dbg_stall, o_dbg_reg, o_dbg_cc,
|
o_dbg_stall, o_dbg_reg, o_dbg_cc,
|
o_break,
|
o_break,
|
| Line 145... |
Line 147... |
o_wb_we, o_wb_addr, o_wb_data,
|
o_wb_we, o_wb_addr, o_wb_data,
|
i_wb_ack, i_wb_stall, i_wb_data,
|
i_wb_ack, i_wb_stall, i_wb_data,
|
i_wb_err,
|
i_wb_err,
|
// Accounting/CPU usage interface
|
// Accounting/CPU usage interface
|
o_op_stall, o_pf_stall, o_i_count);
|
o_op_stall, o_pf_stall, o_i_count);
|
parameter RESET_ADDRESS=32'h0100000;
|
parameter RESET_ADDRESS=32'h0100000, LGICACHE=9;
|
input i_clk, i_rst, i_interrupt;
|
input i_clk, i_rst, i_interrupt;
|
// Debug interface -- inputs
|
// Debug interface -- inputs
|
input i_halt, i_clear_pf_cache;
|
input i_halt, i_clear_pf_cache;
|
input [4:0] i_dbg_reg;
|
input [4:0] i_dbg_reg;
|
input i_dbg_we;
|
input i_dbg_we;
|
| Line 178... |
Line 180... |
|
|
// Condition codes
|
// Condition codes
|
reg [3:0] flags, iflags; // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
|
reg [3:0] flags, iflags; // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
|
wire [10:0] w_uflags, w_iflags;
|
wire [10:0] w_uflags, w_iflags;
|
reg trap, break_en, step, gie, sleep;
|
reg trap, break_en, step, gie, sleep;
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
reg ill_err;
|
reg ill_err;
|
|
`else
|
|
wire ill_err;
|
`endif
|
`endif
|
reg bus_err_flag;
|
reg bus_err_flag;
|
|
|
// The master chip enable
|
// The master chip enable
|
wire master_ce;
|
wire master_ce;
|
| Line 220... |
Line 224... |
dcdM, dcdF_wr, dcd_gie, dcd_break;
|
dcdM, dcdF_wr, dcd_gie, dcd_break;
|
reg [31:0] dcd_pc;
|
reg [31:0] dcd_pc;
|
reg [23:0] r_dcdI;
|
reg [23:0] r_dcdI;
|
wire dcdA_stall, dcdB_stall, dcdF_stall;
|
wire dcdA_stall, dcdB_stall, dcdF_stall;
|
|
|
`ifdef NG_PRECLEAR_BUS
|
`ifdef OPT_PRECLEAR_BUS
|
reg dcd_clear_bus;
|
reg dcd_clear_bus;
|
`endif
|
`endif
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
reg dcd_illegal;
|
reg dcd_illegal;
|
`endif
|
`endif
|
`ifdef NG_EARLY_BRANCHING
|
`ifdef OPT_EARLY_BRANCHING
|
reg dcd_early_branch_stb, dcd_early_branch;
|
reg dcd_early_branch_stb, dcd_early_branch;
|
reg [31:0] dcd_branch_pc;
|
reg [31:0] dcd_branch_pc;
|
`else
|
`else
|
wire dcd_early_branch_stb, dcd_early_branch;
|
wire dcd_early_branch_stb, dcd_early_branch;
|
wire [31:0] dcd_branch_pc;
|
wire [31:0] dcd_branch_pc;
|
| Line 255... |
Line 259... |
opA_rd, opB_rd;
|
opA_rd, opB_rd;
|
wire [10:0] opFl;
|
wire [10:0] opFl;
|
reg [6:0] r_opF;
|
reg [6:0] r_opF;
|
wire [8:0] opF;
|
wire [8:0] opF;
|
wire op_ce;
|
wire op_ce;
|
`ifdef NG_PRECLEAR_BUS
|
`ifdef OPT_PRECLEAR_BUS
|
reg op_clear_bus;
|
reg op_clear_bus;
|
`endif
|
`endif
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
reg op_illegal;
|
reg op_illegal;
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
| Line 277... |
Line 281... |
wire [31:0] alu_result;
|
wire [31:0] alu_result;
|
wire [3:0] alu_flags;
|
wire [3:0] alu_flags;
|
wire alu_valid;
|
wire alu_valid;
|
wire set_cond;
|
wire set_cond;
|
reg alu_wr, alF_wr, alu_gie;
|
reg alu_wr, alF_wr, alu_gie;
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
reg alu_illegal;
|
reg alu_illegal;
|
|
`else
|
|
wire alu_illegal;
|
`endif
|
`endif
|
|
|
|
|
|
|
wire mem_ce, mem_stalled;
|
wire mem_ce, mem_stalled;
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
|
wire mem_pipe_stalled;
|
|
`endif
|
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err,
|
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err,
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
|
wire [4:0] mem_wreg;
|
wire [4:0] mem_wreg;
|
|
|
wire mem_busy, mem_rdbusy;
|
wire mem_busy, mem_rdbusy;
|
| Line 309... |
Line 318... |
|
|
|
|
//
|
//
|
// MASTER: clock enable.
|
// MASTER: clock enable.
|
//
|
//
|
assign master_ce = (~i_halt)&&(~o_break)&&(~sleep)&&(~mem_rdbusy);
|
assign master_ce = (~i_halt)&&(~o_break)&&(~sleep);
|
|
|
|
|
//
|
//
|
// PIPELINE STAGE #1 :: Prefetch
|
// PIPELINE STAGE #1 :: Prefetch
|
// Calculate stall conditions
|
// Calculate stall conditions
|
| Line 323... |
Line 332... |
// Calculate stall conditions
|
// Calculate stall conditions
|
assign dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
|
assign dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
|
assign dcd_stalled = (dcdvalid)&&(
|
assign dcd_stalled = (dcdvalid)&&(
|
(op_stall)
|
(op_stall)
|
||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
|
||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
|
`ifndef NG_BRANCH_DELAY_SLOT
|
|
||((opvalid_mem)&&(op_wr_pc))
|
||((opvalid_mem)&&(op_wr_pc))
|
`endif
|
|
||((opvalid_mem)&&(opR_cc)));
|
||((opvalid_mem)&&(opR_cc)));
|
//
|
//
|
// PIPELINE STAGE #3 :: Read Operands
|
// PIPELINE STAGE #3 :: Read Operands
|
// Calculate stall conditions
|
// Calculate stall conditions
|
assign op_stall = ((mem_stalled)&&(opvalid_mem))
|
assign op_stall = ((mem_stalled)&&(opvalid_mem))
|
| Line 348... |
Line 355... |
// prior operation will write either the PC or CC registers.
|
// prior operation will write either the PC or CC registers.
|
// 4. Last case: Stall if we would otherwise move a break instruction
|
// 4. Last case: Stall if we would otherwise move a break instruction
|
// through the ALU. Break instructions are not allowed through
|
// through the ALU. Break instructions are not allowed through
|
// the ALU.
|
// the ALU.
|
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
|
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
|
`ifdef BEFORE
|
|
||((opvalid)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
|
&&((wr_write_pc)||(wr_write_cc)) // Case 3
|
|
`else
|
|
||((opvalid_mem)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
||((opvalid_mem)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
&&((wr_write_pc)||(wr_write_cc))) // Case 3
|
&&((wr_write_pc)||(wr_write_cc))) // Case 3
|
`endif
|
|
||((opvalid)&&(op_break)); // Case 4
|
||((opvalid)&&(op_break)); // Case 4
|
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
|
assign alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
|
//
|
//
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
|
&&(set_cond)&&(~mem_stalled);
|
|
assign mem_stalled = (~master_ce)||((opvalid_mem)&&(
|
|
(mem_pipe_stalled)
|
|
||((~op_pipe)&&(mem_busy))
|
|
// Stall waiting for flags to be valid
|
|
// Or waiting for a write to the PC register
|
|
// Or CC register, since that can change the
|
|
// PC as well
|
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
|
&&((wr_write_pc)||(wr_write_cc)))));
|
|
`else
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
|
|
|
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
|
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
|
(~master_ce)
|
(~master_ce)
|
// Stall waiting for flags to be valid
|
// Stall waiting for flags to be valid
|
// Or waiting for a write to the PC register
|
// Or waiting for a write to the PC register
|
// Or CC register, since that can change the
|
// Or CC register, since that can change the
|
// PC as well
|
// PC as well
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
|
|
`endif
|
|
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #1 :: Prefetch
|
// PIPELINE STAGE #1 :: Prefetch
|
//
|
//
|
//
|
//
|
`ifdef SINGLE_FETCH
|
`ifdef OPT_SINGLE_FETCH
|
wire pf_ce;
|
wire pf_ce;
|
|
|
assign pf_ce = (~dcd_stalled);
|
assign pf_ce = (~dcd_stalled);
|
prefetch pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
|
prefetch pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
|
instruction, instruction_pc, instruction_gie,
|
instruction, instruction_pc, instruction_gie,
|
pf_valid, pf_illegal,
|
pf_valid, pf_illegal,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_ack, pf_stall, pf_err, i_wb_data);
|
pf_ack, pf_stall, pf_err, i_wb_data);
|
`else // Pipe fetch
|
`else // Pipe fetch
|
pipefetch #(RESET_ADDRESS)
|
pipefetch #(RESET_ADDRESS, LGICACHE)
|
pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
|
pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
|
i_clear_pf_cache, ~dcd_stalled,
|
i_clear_pf_cache, ~dcd_stalled,
|
(new_pc)?pf_pc:dcd_branch_pc,
|
(new_pc)?pf_pc:dcd_branch_pc,
|
instruction, instruction_pc, pf_valid,
|
instruction, instruction_pc, pf_valid,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
`ifdef NG_PRECLEAR_BUS
|
`ifdef OPT_PRECLEAR_BUS
|
((dcd_clear_bus)&&(dcdvalid))
|
((dcd_clear_bus)&&(dcdvalid))
|
||((op_clear_bus)&&(opvalid))
|
||((op_clear_bus)&&(opvalid))
|
||
|
||
|
`endif
|
`endif
|
(mem_cyc_lcl)||(mem_cyc_gbl),
|
(mem_cyc_lcl)||(mem_cyc_gbl),
|
| Line 409... |
Line 426... |
else if (dcd_ce)
|
else if (dcd_ce)
|
dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
|
dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
|
else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
|
else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
|
dcdvalid <= 1'b0;
|
dcdvalid <= 1'b0;
|
|
|
`ifdef NG_EARLY_BRANCHING
|
`ifdef OPT_EARLY_BRANCHING
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG))
|
if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(~sleep))
|
begin
|
begin
|
dcd_early_branch <= 1'b0;
|
dcd_early_branch <= 1'b0;
|
// First case, a move to PC instruction
|
// First case, a move to PC instruction
|
if ((instruction[31:28] == 4'h2)
|
if ((instruction[31:28] == 4'h2)
|
&&((instruction_gie)
|
&&((instruction_gie)
|
| Line 454... |
Line 471... |
else if (~instruction[28]) // 4'h2 = MOV
|
else if (~instruction[28]) // 4'h2 = MOV
|
dcd_branch_pc <= instruction_pc+32'h01+{ {(17){instruction[14]}}, instruction[14:0] };
|
dcd_branch_pc <= instruction_pc+32'h01+{ {(17){instruction[14]}}, instruction[14:0] };
|
else // if (instruction[28]) // 4'h3 = LDI
|
else // if (instruction[28]) // 4'h3 = LDI
|
dcd_branch_pc <= instruction_pc+32'h01+{ {(8){instruction[23]}}, instruction[23:0] };
|
dcd_branch_pc <= instruction_pc+32'h01+{ {(8){instruction[23]}}, instruction[23:0] };
|
end
|
end
|
`else // NG_EARLY_BRANCHING
|
`else // OPT_EARLY_BRANCHING
|
assign dcd_early_branch_stb = 1'b0;
|
assign dcd_early_branch_stb = 1'b0;
|
assign dcd_early_branch = 1'b0;
|
assign dcd_early_branch = 1'b0;
|
assign dcd_branch_pc = 32'h00;
|
assign dcd_branch_pc = 32'h00;
|
`endif // NG_EARLY_BRANCHING
|
`endif // OPT_EARLY_BRANCHING
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dcd_ce)
|
if (dcd_ce)
|
begin
|
begin
|
dcd_pc <= instruction_pc+1;
|
dcd_pc <= instruction_pc+1;
|
| Line 476... |
Line 493... |
dcdA_cc <= (instruction[27:24] == `CPU_CC_REG);
|
dcdA_cc <= (instruction[27:24] == `CPU_CC_REG);
|
dcdB_cc <= (instruction[19:16] == `CPU_CC_REG);
|
dcdB_cc <= (instruction[19:16] == `CPU_CC_REG);
|
dcdA_pc <= (instruction[27:24] == `CPU_PC_REG);
|
dcdA_pc <= (instruction[27:24] == `CPU_PC_REG);
|
dcdB_pc <= (instruction[19:16] == `CPU_PC_REG);
|
dcdB_pc <= (instruction[19:16] == `CPU_PC_REG);
|
dcdM <= 1'b0;
|
dcdM <= 1'b0;
|
`ifdef NG_CONDITIONAL_FLAGS
|
`ifdef OPT_CONDITIONAL_FLAGS
|
dcdF_wr <= (instruction[23:21]==3'h0);
|
dcdF_wr <= (instruction[23:21]==3'h0);
|
`else
|
`else
|
dcdF_wr <= 1'b1;
|
dcdF_wr <= 1'b1;
|
`endif
|
`endif
|
`ifdef NG_PRECLEAR_BUS
|
`ifdef OPT_PRECLEAR_BUS
|
dcd_clear_bus <= 1'b0;
|
dcd_clear_bus <= 1'b0;
|
`endif
|
`endif
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
dcd_illegal <= pf_illegal;
|
dcd_illegal <= pf_illegal;
|
`endif
|
`endif
|
|
|
// Set the condition under which we do this operation
|
// Set the condition under which we do this operation
|
// The top four bits are a mask, the bottom four the
|
// The top four bits are a mask, the bottom four the
|
| Line 515... |
Line 532... |
dcdF_wr <= 1'b0; // Don't write flags
|
dcdF_wr <= 1'b0; // Don't write flags
|
dcdF <= 4'h8; // This is unconditional
|
dcdF <= 4'h8; // This is unconditional
|
dcdOp <= 4'h2;
|
dcdOp <= 4'h2;
|
end
|
end
|
4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
|
4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
|
`ifdef NG_CONDITIONAL_FLAGS
|
`ifdef OPT_CONDITIONAL_FLAGS
|
// Don't write flags except for multiplies
|
// Don't write flags except for multiplies
|
// and then only if they are unconditional
|
// and then only if they are unconditional
|
dcdF_wr <= ((instruction[27:25] != 3'h7)
|
dcdF_wr <= ((instruction[27:25] != 3'h7)
|
&&(instruction[23:21]==3'h0));
|
&&(instruction[23:21]==3'h0));
|
`else
|
`else
|
| Line 534... |
Line 551... |
dcdA_rd <= 1'b0;
|
dcdA_rd <= 1'b0;
|
dcdB_rd <= 1'b0;
|
dcdB_rd <= 1'b0;
|
dcdOp <= 4'h2;
|
dcdOp <= 4'h2;
|
// Might also be a break. Big
|
// Might also be a break. Big
|
// instruction set hole here.
|
// instruction set hole here.
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
|
dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
|
`endif
|
`endif
|
end else if (instruction[27:24] == 4'hf)
|
end else if (instruction[27:24] == 4'hf)
|
begin // Load partial immediate(s)
|
begin // Load partial immediate(s)
|
dcdA_wr <= 1'b1;
|
dcdA_wr <= 1'b1;
|
| Line 563... |
Line 580... |
if (instruction[20])
|
if (instruction[20])
|
r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
|
r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
|
else
|
else
|
r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
|
r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
|
dcdM <= 1'b1; // Memory operation
|
dcdM <= 1'b1; // Memory operation
|
`ifdef NG_PRECLEAR_BUS
|
`ifdef OPT_PRECLEAR_BUS
|
dcd_clear_bus <= (instruction[23:21]==3'h0);
|
dcd_clear_bus <= (instruction[23:21]==3'h0);
|
`endif
|
`endif
|
end
|
end
|
default: begin
|
default: begin
|
dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
|
dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
|
| Line 584... |
Line 601... |
dcd_gie <= instruction_gie;
|
dcd_gie <= instruction_gie;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dcd_ce)
|
if (dcd_ce)
|
dcd_break <= (instruction[31:0] == 32'h4e000001);
|
dcd_break <= (instruction[31:0] == 32'h4e000001);
|
else if ((clear_pipeline)||(~dcdvalid))
|
else if ((clear_pipeline)||(~dcdvalid)) // SHOULDNT THIS BE ||op_ce?
|
dcd_break <= 1'b0;
|
dcd_break <= 1'b0;
|
|
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
|
reg [23:0] r_opI;
|
|
reg [4:0] op_B;
|
|
reg op_pipe;
|
|
|
|
initial op_pipe = 1'b0;
|
|
// To be a pipeable operation, there must be
|
|
// two valid adjacent instructions
|
|
// Both must be memory instructions
|
|
// Both must be writes, or both must be reads
|
|
// Both operations must be to the same identical address,
|
|
// or at least a single (one) increment above that address
|
|
always @(posedge i_clk)
|
|
if (op_ce)
|
|
op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
|
|
&&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
|
|
&&(dcdB == op_B) // Same address register
|
|
&&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
|
|
always @(posedge i_clk)
|
|
if (op_ce) // &&(dcdvalid))
|
|
r_opI <= r_dcdI;
|
|
always @(posedge i_clk)
|
|
if (op_ce) // &&(dcdvalid))
|
|
op_B <= dcdB;
|
|
`endif
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #3 :: Read Operands (Registers)
|
// PIPELINE STAGE #3 :: Read Operands (Registers)
|
//
|
//
|
| Line 666... |
Line 708... |
// move forward, and get a stall cycle inserted.
|
// move forward, and get a stall cycle inserted.
|
// Hence, the test on dcd_stalled here. If we must
|
// Hence, the test on dcd_stalled here. If we must
|
// wait until our operands are valid, then we aren't
|
// wait until our operands are valid, then we aren't
|
// valid yet until then.
|
// valid yet until then.
|
opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
`else
|
`else
|
opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
| Line 696... |
Line 738... |
if (i_rst) op_break <= 1'b0;
|
if (i_rst) op_break <= 1'b0;
|
else if (op_ce) op_break <= (dcd_break);
|
else if (op_ce) op_break <= (dcd_break);
|
else if ((clear_pipeline)||(~opvalid))
|
else if ((clear_pipeline)||(~opvalid))
|
op_break <= 1'b0;
|
op_break <= 1'b0;
|
|
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if(op_ce)
|
if(op_ce)
|
op_illegal <= dcd_illegal;
|
op_illegal <= dcd_illegal;
|
`endif
|
`endif
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_ce)
|
begin
|
begin
|
opn <= dcdOp; // Which ALU operation?
|
opn <= dcdOp; // Which ALU operation?
|
// opM <= dcdM; // Is this a memory operation?
|
// opM <= dcdM; // Is this a memory operation?
|
`ifdef NG_EARLY_BRANCH
|
`ifdef OPT_EARLY_BRANCHING
|
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
|
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
|
opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
|
opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
|
`else
|
`else
|
// Will we write the flags/CC Register with our result?
|
// Will we write the flags/CC Register with our result?
|
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
|
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
|
// Will we be writing our results into a register?
|
// Will we be writing our results into a register?
|
opR_wr <= dcdA_wr;
|
opR_wr <= dcdA_wr;
|
`endif
|
`endif
|
// What register will these results be written into?
|
// What register will these results be written into?
|
opR <= dcdA;
|
opR <= dcdA;
|
opR_cc <= (dcdA_wr)&&(dcdA_cc);
|
opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
|
// User level (1), vs supervisor (0)/interrupts disabled
|
// User level (1), vs supervisor (0)/interrupts disabled
|
op_gie <= dcd_gie;
|
op_gie <= dcd_gie;
|
|
|
// We're not done with these yet--we still need them
|
// We're not done with these yet--we still need them
|
// for the unclocked assign. We need the unclocked
|
// for the unclocked assign. We need the unclocked
|
| Line 731... |
Line 773... |
// use that value.
|
// use that value.
|
opA_rd <= dcdA_rd;
|
opA_rd <= dcdA_rd;
|
opB_rd <= dcdB_rd;
|
opB_rd <= dcdB_rd;
|
op_pc <= dcd_pc;
|
op_pc <= dcd_pc;
|
//
|
//
|
`ifdef NG_EARLY_BRANCHING
|
`ifdef OPT_EARLY_BRANCHING
|
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
|
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
|
`else
|
`else
|
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
|
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
|
`endif
|
`endif
|
|
|
`ifdef NG_PRECLEAR_BUS
|
`ifdef OPT_PRECLEAR_BUS
|
op_clear_bus <= dcd_clear_bus;
|
op_clear_bus <= dcd_clear_bus;
|
`endif
|
`endif
|
end
|
end
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
|
|
| Line 775... |
Line 817... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_ce)
|
opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0);
|
opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0);
|
assign opB = (opB_alu) ? alu_result : r_opB;
|
assign opB = (opB_alu) ? alu_result : r_opB;
|
assign dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
|
assign dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
|
|
// Stall on memory ops writing to my register
|
|
// (i.e. loads), or on any write to my
|
|
// register if I have an immediate offset
|
|
// Note the exception for writing to the PC:
|
|
// if I write to the PC, the whole next
|
|
// instruction is invalid, not just the
|
|
// operand. That'll get wiped in the
|
|
// next operation anyway, so don't stall
|
|
// here.
|
((opvalid)&&(opR_wr)&&(opR == dcdB)
|
((opvalid)&&(opR_wr)&&(opR == dcdB)
|
|
&&(opR != { op_gie, `CPU_PC_REG} )
|
&&((opvalid_mem)||(dcdI != 0)))
|
&&((opvalid_mem)||(dcdI != 0)))
|
|
// Stall on any write to the flags register,
|
|
// if we're going to need the flags value for
|
|
// opB.
|
||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
|
||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
|
|
// Stall on any ongoing memory operation that
|
|
// will write to opB
|
||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB)));
|
||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB)));
|
assign dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
|
assign dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
|
&&(opvalid)&&(opR_cc);
|
&&(opvalid)&&(opR_cc);
|
//
|
//
|
//
|
//
|
| Line 815... |
Line 872... |
if ((alu_ce)||(mem_ce))
|
if ((alu_ce)||(mem_ce))
|
alu_gie <= op_gie;
|
alu_gie <= op_gie;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((alu_ce)||(mem_ce))
|
if ((alu_ce)||(mem_ce))
|
alu_pc <= op_pc;
|
alu_pc <= op_pc;
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
|
always @(posedge i_clk)
|
|
if ((alu_ce)||(mem_ce))
|
|
alu_illegal <= op_illegal;
|
|
`endif
|
|
|
initial alu_pc_valid = 1'b0;
|
initial alu_pc_valid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~clear_pipeline)
|
alu_pc_valid <= (~i_rst)&&(master_ce)&&(~mem_rdbusy)&&(opvalid)&&(~clear_pipeline)
|
&&((opvalid_alu)||(~mem_stalled));
|
&&((opvalid_alu)||(~mem_stalled));
|
|
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
|
pipemem domem(i_clk, i_rst, mem_ce,
|
|
(opn[0]), opB, opA, opR,
|
|
mem_busy, mem_pipe_stalled,
|
|
mem_valid, bus_err, mem_wreg, mem_result,
|
|
mem_cyc_gbl, mem_cyc_lcl,
|
|
mem_stb_gbl, mem_stb_lcl,
|
|
mem_we, mem_addr, mem_data,
|
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
|
|
|
`else // PIPELINED_BUS_ACCESS
|
memops domem(i_clk, i_rst, mem_ce,
|
memops domem(i_clk, i_rst, mem_ce,
|
(opn[0]), opB, opA, opR,
|
(opn[0]), opB, opA, opR,
|
mem_busy, mem_valid, bus_err, mem_wreg, mem_result,
|
mem_busy,
|
|
mem_valid, bus_err, mem_wreg, mem_result,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_we, mem_addr, mem_data,
|
mem_we, mem_addr, mem_data,
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
|
`endif // PIPELINED_BUS_ACCESS
|
assign mem_rdbusy = (((mem_cyc_gbl)||(mem_cyc_lcl))&&(~mem_we));
|
assign mem_rdbusy = (((mem_cyc_gbl)||(mem_cyc_lcl))&&(~mem_we));
|
|
|
// Either the prefetch or the instruction gets the memory bus, but
|
// Either the prefetch or the instruction gets the memory bus, but
|
// never both.
|
// never both.
|
wbdblpriarb #(32,32) pformem(i_clk, i_rst,
|
wbdblpriarb #(32,32) pformem(i_clk, i_rst,
|
| Line 861... |
Line 937... |
// When shall we write back? On one of two conditions
|
// When shall we write back? On one of two conditions
|
// Note that the flags needed to be checked before issuing the
|
// Note that the flags needed to be checked before issuing the
|
// bus instruction, so they don't need to be checked here.
|
// bus instruction, so they don't need to be checked here.
|
// Further, alu_wr includes (set_cond), so we don't need to
|
// Further, alu_wr includes (set_cond), so we don't need to
|
// check for that here either.
|
// check for that here either.
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
assign wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
|
assign wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
|
`else
|
`else
|
assign wr_reg_ce = ((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
|
assign wr_reg_ce = ((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
|
`endif
|
`endif
|
// Which register shall be written?
|
// Which register shall be written?
|
|
// COULD SIMPLIFY THIS: by adding three bits to these registers,
|
|
// One or PC, one for CC, and one for GIE match
|
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
|
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
|
// Are we writing to the CC register?
|
// Are we writing to the CC register?
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
// Are we writing to the PC?
|
// Are we writing to the PC?
|
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
|
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
|
| Line 885... |
Line 963... |
//
|
//
|
// Write back to the condition codes/flags register ...
|
// Write back to the condition codes/flags register ...
|
// When shall we write to our flags register? alF_wr already
|
// When shall we write to our flags register? alF_wr already
|
// includes the set condition ...
|
// includes the set condition ...
|
assign wr_flags_ce = (alF_wr)&&(alu_valid)&&(~clear_pipeline)&&(~alu_illegal);
|
assign wr_flags_ce = (alF_wr)&&(alu_valid)&&(~clear_pipeline)&&(~alu_illegal);
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
assign w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
assign w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
assign w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
assign w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
`else
|
`else
|
assign w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
assign w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
assign w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
assign w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
| Line 937... |
Line 1015... |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
break_en <= wr_reg_vl[`CPU_BREAK_BIT];
|
break_en <= wr_reg_vl[`CPU_BREAK_BIT];
|
else if ((i_halt)&&(i_dbg_we)
|
else if ((i_halt)&&(i_dbg_we)
|
&&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
|
&&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
|
break_en <= i_dbg_data[`CPU_BREAK_BIT];
|
break_en <= i_dbg_data[`CPU_BREAK_BIT];
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
assign o_break = ((break_en)||(~op_gie))&&(op_break)
|
assign o_break = ((break_en)||(~op_gie))&&(op_break)
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
&&(~clear_pipeline)
|
&&(~clear_pipeline)
|
||((~alu_gie)&&(bus_err))
|
||((~alu_gie)&&(bus_err))
|
||((~alu_gie)&&(alu_valid)&&(alu_illegal));
|
||((~alu_gie)&&(alu_valid)&&(alu_illegal));
|
`else
|
`else
|
assign o_break = (((break_en)||(~op_gie))&&(op_break)
|
assign o_break = (((break_en)||(~op_gie))&&(op_break)
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
&&(~clear_pipeline))
|
&&(~clear_pipeline))
|
||((~alu_gie)&&(bus_err))
|
||((~alu_gie)&&(bus_err));
|
`endif
|
`endif
|
|
|
|
|
// The sleep register. Setting the sleep register causes the CPU to
|
// The sleep register. Setting the sleep register causes the CPU to
|
// sleep until the next interrupt. Setting the sleep register within
|
// sleep until the next interrupt. Setting the sleep register within
|
| Line 982... |
Line 1060... |
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
|
step <= wr_reg_vl[`CPU_STEP_BIT];
|
step <= wr_reg_vl[`CPU_STEP_BIT];
|
else if ((i_halt)&&(i_dbg_we)
|
else if ((i_halt)&&(i_dbg_we)
|
&&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
|
&&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
|
step <= i_dbg_data[`CPU_STEP_BIT];
|
step <= i_dbg_data[`CPU_STEP_BIT];
|
else if ((master_ce)&&(alu_pc_valid)&&(step)&&(gie))
|
else if ((alu_pc_valid)&&(step)&&(gie))
|
step <= 1'b0;
|
step <= 1'b0;
|
|
|
// The GIE register. Only interrupts can disable the interrupt register
|
// The GIE register. Only interrupts can disable the interrupt register
|
assign w_switch_to_interrupt = (gie)&&(
|
assign w_switch_to_interrupt = (gie)&&(
|
// On interrupt (obviously)
|
// On interrupt (obviously)
|
(i_interrupt)
|
(i_interrupt)
|
// If we are stepping the CPU
|
// If we are stepping the CPU
|
||((master_ce)&&(alu_pc_valid)&&(step))
|
||((alu_pc_valid)&&(step))
|
// If we encounter a break instruction, if the break
|
// If we encounter a break instruction, if the break
|
// enable isn't set.
|
// enable isn't set.
|
||((master_ce)&&(op_break)&&(~break_en))
|
||((master_ce)&&(~mem_rdbusy)&&(op_break)&&(~break_en))
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
// On an illegal instruction
|
// On an illegal instruction
|
||((alu_valid)&&(alu_illegal))
|
||((alu_valid)&&(alu_illegal))
|
`endif
|
`endif
|
// If we write to the CC register
|
// If we write to the CC register
|
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
|
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
|
| Line 1034... |
Line 1112... |
&&(~i_dbg_data[`CPU_GIE_BIT]))
|
&&(~i_dbg_data[`CPU_GIE_BIT]))
|
trap <= i_dbg_data[`CPU_TRAP_BIT];
|
trap <= i_dbg_data[`CPU_TRAP_BIT];
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
trap <= 1'b0;
|
trap <= 1'b0;
|
|
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
initial ill_err = 1'b0;
|
initial ill_err = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ill_err <= 1'b0;
|
ill_err <= 1'b0;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
ill_err <= 1'b0;
|
ill_err <= 1'b0;
|
else if ((alu_valid)&&(alu_illegal)&&(gie))
|
else if ((alu_valid)&&(alu_illegal)&&(gie))
|
ill_err <= 1'b1;
|
ill_err <= 1'b1;
|
|
`else
|
|
assign ill_err = 1'b0;
|
`endif
|
`endif
|
initial bus_err_flag = 1'b0;
|
initial bus_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
bus_err_flag <= 1'b0;
|
bus_err_flag <= 1'b0;
|
| Line 1141... |
Line 1221... |
// later evaluate how well we are doing.
|
// later evaluate how well we are doing.
|
//
|
//
|
//
|
//
|
assign o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
|
assign o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
|
assign o_pf_stall = (master_ce)&&(~pf_valid);
|
assign o_pf_stall = (master_ce)&&(~pf_valid);
|
assign o_i_count = alu_pc_valid;
|
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
|
endmodule
|
endmodule
|
|
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No newline at end of file
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No newline at end of file
|
