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///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    zipcpu.v
// Filename:    zipcpu.v
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
// Purpose:     This is the top level module holding the core of the Zip CPU
// Purpose:     This is the top level module holding the core of the Zip CPU
//              together.  The Zip CPU is designed to be as simple as possible.
//              together.  The Zip CPU is designed to be as simple as possible.
//      (actual implementation aside ...)  The instruction set is about as
//      (actual implementation aside ...)  The instruction set is about as
//      RISC as you can get, there are only 16 instruction types supported.
//      RISC as you can get, there are only 16 instruction types supported.
//      Please see the accompanying spec.pdf file for a description of these
//      Please see the accompanying spec.pdf file for a description of these
//      instructions.
//      instructions.
//
//
//      All instructions are 32-bits wide.  All bus accesses, both address and
//      All instructions are 32-bits wide.  All bus accesses, both address and
//      data, are 32-bits over a wishbone bus.
//      data, are 32-bits over a wishbone bus.
//
//
//      The Zip CPU is fully pipelined with the following pipeline stages:
//      The Zip CPU is fully pipelined with the following pipeline stages:
//
//
//              1. Prefetch, returns the instruction from memory. 
//              1. Prefetch, returns the instruction from memory. 
//
//
//              2. Instruction Decode
//              2. Instruction Decode
//
//
//              3. Read Operands
//              3. Read Operands
//
//
//              4. Apply Instruction
//              4. Apply Instruction
//
//
//              4. Write-back Results
//              4. Write-back Results
//
//
//      Further information about the inner workings of this CPU may be
//      Further information about the inner workings of this CPU may be
//      found in the spec.pdf file.  (The documentation within this file
//      found in the spec.pdf file.  (The documentation within this file
//      had become out of date and out of sync with the spec.pdf, so look
//      had become out of date and out of sync with the spec.pdf, so look
//      to the spec.pdf for accurate and up to date information.)
//      to the spec.pdf for accurate and up to date information.)
//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Tecnology, LLC
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
//
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
// fetches are more complicated and therefore use more FPGA resources, while
// fetches are more complicated and therefore use more FPGA resources, while
// single fetches will cause the CPU to stall for about 5 stalls each 
// single fetches will cause the CPU to stall for about 5 stalls each 
// instruction cycle, effectively reducing the instruction count per clock to
// instruction cycle, effectively reducing the instruction count per clock to
// about 0.2.  However, the area cost may be worth it.  Consider:
// about 0.2.  However, the area cost may be worth it.  Consider:
//
//
//      Slice LUTs              ZipSystem       ZipCPU
//      Slice LUTs              ZipSystem       ZipCPU
//      Single Fetching         2521            1734
//      Single Fetching         2521            1734
//      Pipelined fetching      2796            2046
//      Pipelined fetching      2796            2046
//
//
// `define      OPT_SINGLE_FETCH
 
//
 
//
//
//
//
`define CPU_CC_REG      4'he
`define CPU_CC_REG      4'he
`define CPU_PC_REG      4'hf
`define CPU_PC_REG      4'hf
 
`define CPU_BUSERR_BIT  10
`define CPU_TRAP_BIT    9
`define CPU_TRAP_BIT    9
 
`define CPU_ILL_BIT     8
`define CPU_BREAK_BIT   7
`define CPU_BREAK_BIT   7
`define CPU_STEP_BIT    6
`define CPU_STEP_BIT    6
`define CPU_GIE_BIT     5
`define CPU_GIE_BIT     5
`define CPU_SLEEP_BIT   4
`define CPU_SLEEP_BIT   4
// Compile time defines
// Compile time defines
//
//
`include "cpudefs.v"
`include "cpudefs.v"
//
//
 
//
 
//
 
// `define      DEBUG_SCOPE
 
//
 
//
 
//
module  zipcpu(i_clk, i_rst, i_interrupt,
module  zipcpu(i_clk, i_rst, i_interrupt,
                // Debug interface
                // Debug interface
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
                        o_break,
                        o_break,
                // CPU interface to the wishbone bus
                // CPU interface to the wishbone bus
                o_wb_gbl_cyc, o_wb_gbl_stb,
                o_wb_gbl_cyc, o_wb_gbl_stb,
                        o_wb_lcl_cyc, o_wb_lcl_stb,
                        o_wb_lcl_cyc, o_wb_lcl_stb,
                        o_wb_we, o_wb_addr, o_wb_data,
                        o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data,
                        i_wb_err,
                        i_wb_err,
                // Accounting/CPU usage interface
                // Accounting/CPU usage interface
                o_op_stall, o_pf_stall, o_i_count,
                o_op_stall, o_pf_stall, o_i_count
                //
`ifdef  DEBUG_SCOPE
                o_debug);
                , o_debug
 
`endif
 
                );
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
                        LGICACHE=6, AW=ADDRESS_WIDTH;
                        LGICACHE=6, AW=ADDRESS_WIDTH;
`ifdef  OPT_MULTIPLY
`ifdef  OPT_MULTIPLY
        parameter       IMPLEMENT_MPY = 1;
        parameter       IMPLEMENT_MPY = 1;
`else
`else
        parameter       IMPLEMENT_MPY = 0;
        parameter       IMPLEMENT_MPY = 0;
`endif
`endif
        input                   i_clk, i_rst, i_interrupt;
        input                   i_clk, i_rst, i_interrupt;
        // Debug interface -- inputs
        // Debug interface -- inputs
        input                   i_halt, i_clear_pf_cache;
        input                   i_halt, i_clear_pf_cache;
        input           [4:0]    i_dbg_reg;
        input           [4:0]    i_dbg_reg;
        input                   i_dbg_we;
        input                   i_dbg_we;
        input           [31:0]   i_dbg_data;
        input           [31:0]   i_dbg_data;
        // Debug interface -- outputs
        // Debug interface -- outputs
        output  reg             o_dbg_stall;
        output  reg             o_dbg_stall;
        output  reg     [31:0]   o_dbg_reg;
        output  reg     [31:0]   o_dbg_reg;
        output  reg     [3:0]    o_dbg_cc;
        output  reg     [3:0]    o_dbg_cc;
        output  wire            o_break;
        output  wire            o_break;
        // Wishbone interface -- outputs
        // Wishbone interface -- outputs
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
        output  wire    [(AW-1):0]       o_wb_addr;
        output  wire    [(AW-1):0]       o_wb_addr;
        output  wire    [31:0]   o_wb_data;
        output  wire    [31:0]   o_wb_data;
        // Wishbone interface -- inputs
        // Wishbone interface -- inputs
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
        input                   i_wb_err;
        input                   i_wb_err;
        // Accounting outputs ... to help us count stalls and usage
        // Accounting outputs ... to help us count stalls and usage
        output  wire            o_op_stall;
        output  wire            o_op_stall;
        output  wire            o_pf_stall;
        output  wire            o_pf_stall;
        output  wire            o_i_count;
        output  wire            o_i_count;
        //
        //
 
`ifdef  DEBUG_SCOPE
        output  reg     [31:0]   o_debug;
        output  reg     [31:0]   o_debug;
 
`endif
 
 
 
 
        // Registers
        // Registers
        //
        //
        //      The distributed RAM style comment is necessary on the
        //      The distributed RAM style comment is necessary on the
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
        // set and in the process ruining everything else.  It basically
        // set and in the process ruining everything else.  It basically
        // optimizes logic away, to where it no longer works.  The logic
        // optimizes logic away, to where it no longer works.  The logic
        // as described herein will work, this just makes sure XST implements
        // as described herein will work, this just makes sure XST implements
        // that logic.
        // that logic.
        //
        //
        (* ram_style = "distributed" *)
        (* ram_style = "distributed" *)
        reg     [31:0]   regset [0:31];
        reg     [31:0]   regset [0:31];
 
 
        // Condition codes
        // Condition codes
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
        reg     [3:0]    flags, iflags;
        reg     [3:0]    flags, iflags;
        wire    [10:0]   w_uflags, w_iflags;
        wire    [10:0]   w_uflags, w_iflags;
        reg             trap, break_en, step, gie, sleep;
        reg             trap, break_en, step, gie, sleep;
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        reg             ill_err;
        reg             ill_err_u, ill_err_i;
`else
`else
        wire            ill_err;
        wire            ill_err_u, ill_err_i;
`endif
`endif
        reg             bus_err_flag;
        reg             ibus_err_flag, ubus_err_flag;
 
 
        // The master chip enable
        // The master chip enable
        wire            master_ce;
        wire            master_ce;
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #1 :: Prefetch
        //      PIPELINE STAGE #1 :: Prefetch
        //              Variable declarations
        //              Variable declarations
        //
        //
        reg     [(AW-1):0]       pf_pc;
        reg     [(AW-1):0]       pf_pc;
        reg             new_pc, op_break;
        reg             new_pc, op_break;
        wire    clear_pipeline;
        wire    clear_pipeline;
        assign  clear_pipeline = new_pc || i_clear_pf_cache; //  || op_break;
        assign  clear_pipeline = new_pc || i_clear_pf_cache; //  || op_break;
 
 
        wire            dcd_stalled;
        wire            dcd_stalled;
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
        wire    [(AW-1):0]       pf_addr;
        wire    [(AW-1):0]       pf_addr;
        wire    [31:0]           pf_data;
        wire    [31:0]           pf_data;
        wire    [31:0]           instruction;
        wire    [31:0]           instruction;
        wire    [(AW-1):0]       instruction_pc;
        wire    [(AW-1):0]       instruction_pc;
        wire    pf_valid, instruction_gie, pf_illegal;
        wire    pf_valid, instruction_gie, pf_illegal;
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #2 :: Instruction Decode
        //      PIPELINE STAGE #2 :: Instruction Decode
        //              Variable declarations
        //              Variable declarations
        //
        //
        //
        //
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
        wire            op_stall, dcd_ce;
        wire            op_stall, dcd_ce;
        reg     [3:0]    dcdOp;
        reg     [3:0]    dcdOp;
        reg     [4:0]    dcdA, dcdB;
        reg     [4:0]    dcdA, dcdB;
        reg             dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
        reg             dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
        reg     [3:0]    dcdF;
        reg     [3:0]    dcdF;
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
        reg     [(AW-1):0]       dcd_pc;
        reg     [(AW-1):0]       dcd_pc;
        reg     [23:0]   r_dcdI;
        reg     [23:0]   r_dcdI;
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
        reg             dcd_zI; // true if dcdI == 0
        reg             dcd_zI; // true if dcdI == 0
`endif
`endif
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
 
 
`ifdef  OPT_PRECLEAR_BUS
`ifdef  OPT_PRECLEAR_BUS
        reg     dcd_clear_bus;
        reg     dcd_clear_bus;
`endif
`endif
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        reg     dcd_illegal;
        reg     dcd_illegal;
`endif
`endif
`ifdef  OPT_EARLY_BRANCHING
`ifdef  OPT_EARLY_BRANCHING
        reg                     dcd_early_branch_stb, dcd_early_branch;
        reg                     dcd_early_branch_stb, dcd_early_branch;
        reg     [(AW-1):0]       dcd_branch_pc;
        reg     [(AW-1):0]       dcd_branch_pc;
`else
`else
        wire                    dcd_early_branch_stb, dcd_early_branch;
        wire                    dcd_early_branch_stb, dcd_early_branch;
        wire    [(AW-1):0]       dcd_branch_pc;
        wire    [(AW-1):0]       dcd_branch_pc;
`endif
`endif
 
 
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #3 :: Read Operands
        //      PIPELINE STAGE #3 :: Read Operands
        //              Variable declarations
        //              Variable declarations
        //
        //
        //
        //
        //
        //
        // Now, let's read our operands
        // Now, let's read our operands
        reg     [4:0]    alu_reg;
        reg     [4:0]    alu_reg;
        reg     [3:0]    opn;
        reg     [3:0]    opn;
        reg     [4:0]    opR;
        reg     [4:0]    opR;
        reg     [31:0]   r_opA, r_opB;
        reg     [31:0]   r_opA, r_opB;
        reg     [(AW-1):0]       op_pc;
        reg     [(AW-1):0]       op_pc;
        wire    [31:0]   w_opA, w_opB;
        wire    [31:0]   w_opA, w_opB;
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        reg             opR_wr, opR_cc, opF_wr, op_gie;
        reg             opR_wr, opR_cc, opF_wr, op_gie;
        wire    [10:0]   opFl;
        wire    [10:0]   opFl;
        reg     [5:0]    r_opF;
        reg     [5:0]    r_opF;
        wire    [7:0]    opF;
        wire    [7:0]    opF;
        reg     [2:0]    opF_cp;
        reg     [2:0]    opF_cp;
        wire            op_ce;
        wire            op_ce;
        // Some pipeline control wires
        // Some pipeline control wires
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
        reg     opA_alu, opA_mem;
        reg     opA_alu, opA_mem;
        reg     opB_alu, opB_mem;
        reg     opB_alu, opB_mem;
`endif
`endif
`ifdef  OPT_PRECLEAR_BUS
`ifdef  OPT_PRECLEAR_BUS
        reg     op_clear_bus;
        reg     op_clear_bus;
`endif
`endif
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        reg     op_illegal;
        reg     op_illegal;
`endif
`endif
 
 
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #4 :: ALU / Memory
        //      PIPELINE STAGE #4 :: ALU / Memory
        //              Variable declarations
        //              Variable declarations
        //
        //
        //
        //
        reg     [(AW-1):0]       alu_pc;
        reg     [(AW-1):0]       alu_pc;
        reg             alu_pc_valid;;
        reg             alu_pc_valid;;
        wire            alu_ce, alu_stall;
        wire            alu_ce, alu_stall;
        wire    [31:0]   alu_result;
        wire    [31:0]   alu_result;
        wire    [3:0]    alu_flags;
        wire    [3:0]    alu_flags;
        wire            alu_valid;
        wire            alu_valid;
        wire            set_cond;
        wire            set_cond;
        reg             alu_wr, alF_wr, alu_gie;
        reg             alu_wr, alF_wr, alu_gie;
        wire            alu_illegal_op;
        wire            alu_illegal_op;
        wire            alu_illegal;
        wire            alu_illegal;
 
 
 
 
 
 
        wire    mem_ce, mem_stalled;
        wire    mem_ce, mem_stalled;
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
        wire    mem_pipe_stalled;
        wire    mem_pipe_stalled;
`endif
`endif
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
        wire    [4:0]            mem_wreg;
        wire    [4:0]            mem_wreg;
 
 
        wire                    mem_busy, mem_rdbusy;
        wire                    mem_busy, mem_rdbusy;
        wire    [(AW-1):0]       mem_addr;
        wire    [(AW-1):0]       mem_addr;
        wire    [31:0]           mem_data, mem_result;
        wire    [31:0]           mem_data, mem_result;
        reg     [4:0]            mem_last_reg; // Last register result to go in
        reg     [4:0]            mem_last_reg; // Last register result to go in
 
 
 
 
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #5 :: Write-back
        //      PIPELINE STAGE #5 :: Write-back
        //              Variable declarations
        //              Variable declarations
        //
        //
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
        wire    [4:0]    wr_reg_id;
        wire    [4:0]    wr_reg_id;
        wire    [31:0]   wr_reg_vl;
        wire    [31:0]   wr_reg_vl;
        wire    w_switch_to_interrupt, w_release_from_interrupt;
        wire    w_switch_to_interrupt, w_release_from_interrupt;
        reg     [(AW-1):0]       upc, ipc;
        reg     [(AW-1):0]       upc, ipc;
 
 
 
 
 
 
        //
        //
        //      MASTER: clock enable.
        //      MASTER: clock enable.
        //
        //
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
 
 
 
 
        //
        //
        //      PIPELINE STAGE #1 :: Prefetch
        //      PIPELINE STAGE #1 :: Prefetch
        //              Calculate stall conditions
        //              Calculate stall conditions
 
        //
 
        //      These are calculated externally, within the prefetch module.
 
        //
 
 
        //
        //
        //      PIPELINE STAGE #2 :: Instruction Decode
        //      PIPELINE STAGE #2 :: Instruction Decode
        //              Calculate stall conditions
        //              Calculate stall conditions
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
        assign          dcd_stalled = (dcdvalid)&&(
        assign          dcd_stalled = (dcdvalid)&&(
                                        (op_stall)
                                        (op_stall)
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
                                        ||((opvalid_mem)&&(op_wr_pc))
                                        ||((opvalid_mem)&&(op_wr_pc))
                                        ||((opvalid_mem)&&(opR_cc)));
                                        ||((opvalid_mem)&&(opR_cc)));
        //
        //
        //      PIPELINE STAGE #3 :: Read Operands
        //      PIPELINE STAGE #3 :: Read Operands
        //              Calculate stall conditions
        //              Calculate stall conditions
        assign  op_stall = ((opvalid)&&(~master_ce))||(
        assign  op_stall = ((opvalid)&&(~master_ce))||(
                        // Stall if going into the ALU and the ALU is stalled
                        // Stall if going into the ALU and the ALU is stalled
                        //      i.e. if the memory is busy, or we are single
                        //      i.e. if the memory is busy, or we are single
                        //      stepping
                        //      stepping
                        ((opvalid_alu)&&(alu_stall))
                        ((opvalid_alu)&&(alu_stall))
                        //
                        //
                        // ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
                        // ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
                        // Stall if we are going into memory with an operation
                        // Stall if we are going into memory with an operation
                        //      that cannot be pipelined, and the memory is
                        //      that cannot be pipelined, and the memory is
                        //      already busy
                        //      already busy
 
`ifdef  OPT_PIPELINED_BUS_ACCESS
                        ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
                        ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
                        //
                        //
                        // Stall if we are going into memory with a pipeable
                        // Stall if we are going into memory with a pipeable
                        //      operation, but the memory unit declares it is
                        //      operation, but the memory unit declares it is
                        //      not going to accept any more pipeline operations
                        //      not going to accept any more pipeline operations
                        ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
                        ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))
 
`else
 
                        ||((opvalid_mem)&&(mem_busy))
 
`endif
 
                        );
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
 
 
        //
        //
        //      PIPELINE STAGE #4 :: ALU / Memory
        //      PIPELINE STAGE #4 :: ALU / Memory
        //              Calculate stall conditions
        //              Calculate stall conditions
        //
        //
        // 1. Basic stall is if the previous stage is valid and the next is
        // 1. Basic stall is if the previous stage is valid and the next is
        //      busy.  
        //      busy.  
        // 2. Also stall if the prior stage is valid and the master clock enable
        // 2. Also stall if the prior stage is valid and the master clock enable
        //      is de-selected
        //      is de-selected
        // 3. Stall if someone on the other end is writing the CC register,
        // 3. Stall if someone on the other end is writing the CC register,
        //      since we don't know if it'll put us to sleep or not.
        //      since we don't know if it'll put us to sleep or not.
        // 4. Last case: Stall if we would otherwise move a break instruction
        // 4. Last case: Stall if we would otherwise move a break instruction
        //      through the ALU.  Break instructions are not allowed through
        //      through the ALU.  Break instructions are not allowed through
        //      the ALU.
        //      the ALU.
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
                        // Old case #3--this isn't an ALU stall though ...
                        // Old case #3--this isn't an ALU stall though ...
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                                &&(wr_write_cc)) // Case 3
                                &&(wr_write_cc)) // Case 3
                        ||((opvalid_alu)&&(op_break)); // Case 3
                        ||((opvalid_alu)&&(op_break)); // Case 3
        assign  alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
        assign  alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
        //
        //
`ifdef  OPT_PIPELINED_BUS_ACCESS
 
 
        //
 
        // Note: if you change the conditions for mem_ce, you must also change
 
        // alu_pc_valid.
 
        //
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
                        &&(set_cond)&&(~mem_stalled);
                        &&(set_cond)&&(~mem_stalled);
 
`ifdef  OPT_PIPELINED_BUS_ACCESS
        assign  mem_stalled = (~master_ce)||((opvalid_mem)&&(
        assign  mem_stalled = (~master_ce)||((opvalid_mem)&&(
                                (mem_pipe_stalled)
                                (mem_pipe_stalled)
                                ||((~op_pipe)&&(mem_busy))
                                ||((~op_pipe)&&(mem_busy))
                                // Stall waiting for flags to be valid
                                // Stall waiting for flags to be valid
                                // Or waiting for a write to the PC register
                                // Or waiting for a write to the PC register
                                // Or CC register, since that can change the
                                // Or CC register, since that can change the
                                //  PC as well
                                //  PC as well
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                                        &&((wr_write_pc)||(wr_write_cc)))));
                                        &&((wr_write_pc)||(wr_write_cc)))));
`else
`else
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
 
 
 
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
                                (~master_ce)
                                (~master_ce)
                                // Stall waiting for flags to be valid
                                // Stall waiting for flags to be valid
                                // Or waiting for a write to the PC register
                                // Or waiting for a write to the PC register
                                // Or CC register, since that can change the
                                // Or CC register, since that can change the
                                //  PC as well
                                //  PC as well
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
`endif
`endif
 
 
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #1 :: Prefetch
        //      PIPELINE STAGE #1 :: Prefetch
        //
        //
        //
        //
`ifdef  OPT_SINGLE_FETCH
`ifdef  OPT_SINGLE_FETCH
        wire            pf_ce;
        wire            pf_ce;
 
 
        assign          pf_ce = (~dcd_stalled);
        assign          pf_ce = (~dcd_stalled);
        prefetch        #(ADDRESS_WIDTH)
        prefetch        #(ADDRESS_WIDTH)
                        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
                        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
                                instruction, instruction_pc, instruction_gie,
                                instruction, instruction_pc, instruction_gie,
                                        pf_valid, pf_illegal,
                                        pf_valid, pf_illegal,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_ack, pf_stall, pf_err, i_wb_data);
                                pf_ack, pf_stall, pf_err, i_wb_data);
`else // Pipe fetch
`else // Pipe fetch
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
                        pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
                        pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
                                        i_clear_pf_cache, ~dcd_stalled,
                                        i_clear_pf_cache, ~dcd_stalled,
                                        (new_pc)?pf_pc:dcd_branch_pc,
                                        (new_pc)?pf_pc:dcd_branch_pc,
                                        instruction, instruction_pc, pf_valid,
                                        instruction, instruction_pc, pf_valid,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
`ifdef  OPT_PRECLEAR_BUS
`ifdef  OPT_PRECLEAR_BUS
                                ((dcd_clear_bus)&&(dcdvalid))
                                ((dcd_clear_bus)&&(dcdvalid))
                                ||((op_clear_bus)&&(opvalid))
                                ||((op_clear_bus)&&(opvalid))
                                ||
                                ||
`endif
`endif
                                (mem_cyc_lcl)||(mem_cyc_gbl),
                                (mem_cyc_lcl)||(mem_cyc_gbl),
                                pf_illegal);
                                pf_illegal);
        assign  instruction_gie = gie;
        assign  instruction_gie = gie;
`endif
`endif
 
 
        initial dcdvalid = 1'b0;
        initial dcdvalid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        dcdvalid <= 1'b0;
                        dcdvalid <= 1'b0;
                else if (dcd_ce)
                else if (dcd_ce)
                        dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
                        dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
                else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
                else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
                        dcdvalid <= 1'b0;
                        dcdvalid <= 1'b0;
 
 
`ifdef  OPT_EARLY_BRANCHING
`ifdef  OPT_EARLY_BRANCHING
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(master_ce))
                if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(master_ce))
                begin
                begin
                        dcd_early_branch <= 1'b0;
                        dcd_early_branch <= 1'b0;
                        // First case, a move to PC instruction
                        // First case, a move to PC instruction
                        if ((instruction[31:28] == 4'h2)
                        if ((instruction[31:28] == 4'h2)
 
                                // Offsets of the PC register *only*
 
                                &&(instruction[19:16] == `CPU_PC_REG)
                                &&((instruction_gie)
                                &&((instruction_gie)
                                        ||((~instruction[20])&&(~instruction[15])))
                                        ||((~instruction[20])&&(~instruction[15])))
                                &&(instruction[23:21]==3'h0))
                                &&(instruction[23:21]==3'h0)) // Unconditional
                        begin
                        begin
                                dcd_early_branch_stb <= 1'b1;
                                dcd_early_branch_stb <= 1'b1;
                                dcd_early_branch <= 1'b1;
                                dcd_early_branch <= 1'b1;
                                // r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
                                // r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
 
 
                        end else // Next case, an Add Imm -> PC instruction
                        end else // Next case, an Add Imm -> PC instruction
                        if ((instruction[31:28] == 4'ha) // Add
                        if ((instruction[31:28] == 4'ha) // Add
                                &&(~instruction[20]) // Immediate
                                &&(~instruction[20]) // Immediate
                                &&(instruction[23:21]==3'h0)) // Always
                                &&(instruction[23:21]==3'h0)) // Always
                        begin
                        begin
                                dcd_early_branch_stb <= 1'b1;
                                dcd_early_branch_stb <= 1'b1;
                                dcd_early_branch <= 1'b1;
                                dcd_early_branch <= 1'b1;
                                // r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
                                // r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
                        end else // Next case: load Immediate to PC
                        end else // Next case: load Immediate to PC
                        if (instruction[31:28] == 4'h3)
                        if (instruction[31:28] == 4'h3)
                        begin
                        begin
                                dcd_early_branch_stb <= 1'b1;
                                dcd_early_branch_stb <= 1'b1;
                                dcd_early_branch <= 1'b1;
                                dcd_early_branch <= 1'b1;
                                // r_dcdI <= { instruction[23:0] };
                                // r_dcdI <= { instruction[23:0] };
                        end
                        end
                end else
                end else
                begin
                begin
                        if (dcd_ce) dcd_early_branch <= 1'b0;
                        if (dcd_ce) dcd_early_branch <= 1'b0;
                        dcd_early_branch_stb <= 1'b0;
                        dcd_early_branch_stb <= 1'b0;
                end
                end
        generate
        generate
        if (AW == 24)
        if (AW == 24)
        begin
        begin
                always @(posedge i_clk)
                always @(posedge i_clk)
                if (dcd_ce)
                if (dcd_ce)
                begin
                begin
                        if (instruction[31]) // Add
                        if (instruction[31]) // Add
                        begin
                        begin
                                dcd_branch_pc <= instruction_pc
                                dcd_branch_pc <= instruction_pc
                                                + { {(AW-20){instruction[19]}}, instruction[19:0] }
                                                + { {(AW-20){instruction[19]}}, instruction[19:0] }
                                                + {{(AW-1){1'b0}},1'b1};
                                                + {{(AW-1){1'b0}},1'b1};
                        end else if (~instruction[28]) // 4'h2 = MOV
                        end else if (~instruction[28]) // 4'h2 = MOV
                                dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
                                dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
                        else // if (instruction[28]) // 4'h3 = LDI
                        else // if (instruction[28]) // 4'h3 = LDI
                                dcd_branch_pc <= instruction_pc+{ instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
                                dcd_branch_pc <= instruction_pc+{ instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
                end
                end
        end else begin
        end else begin
                always @(posedge i_clk)
                always @(posedge i_clk)
                if (dcd_ce)
                if (dcd_ce)
                begin
                begin
                        if (instruction[31]) // Add
                        if (instruction[31]) // Add
                        begin
                        begin
                                dcd_branch_pc <= instruction_pc
                                dcd_branch_pc <= instruction_pc
                                                        + { {(AW-20){instruction[19]}}, instruction[19:0] }
                                                        + { {(AW-20){instruction[19]}}, instruction[19:0] }
                                                        + {{(AW-1){1'b0}},1'b1};
                                                        + {{(AW-1){1'b0}},1'b1};
                        end else if (~instruction[28]) // 4'h2 = MOV
                        end else if (~instruction[28]) // 4'h2 = MOV
                        begin
                        begin
                                        dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
                                        dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
                        end else // if (instruction[28]) // 4'h3 = LDI
                        end else // if (instruction[28]) // 4'h3 = LDI
                        begin
                        begin
                                dcd_branch_pc <= instruction_pc+{ {(AW-24){instruction[23]}}, instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
                                dcd_branch_pc <= instruction_pc+{ {(AW-24){instruction[23]}}, instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
                        end
                        end
                end
                end
        end endgenerate
        end endgenerate
`else   //      OPT_EARLY_BRANCHING
`else   //      OPT_EARLY_BRANCHING
        assign  dcd_early_branch_stb = 1'b0;
        assign  dcd_early_branch_stb = 1'b0;
        assign  dcd_early_branch     = 1'b0;
        assign  dcd_early_branch     = 1'b0;
        assign  dcd_branch_pc        = {(AW){1'b0}};
        assign  dcd_branch_pc        = {(AW){1'b0}};
`endif  //      OPT_EARLY_BRANCHING
`endif  //      OPT_EARLY_BRANCHING
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (dcd_ce)
                if (dcd_ce)
                begin
                begin
                        dcd_pc <= instruction_pc
                        dcd_pc <= instruction_pc
                                +{{(AW-1){1'b0}},1'b1}; // i.e. dcd_pc+1
                                +{{(AW-1){1'b0}},1'b1}; // i.e. dcd_pc+1
 
 
                        // Record what operation we are doing
                        // Record what operation we are doing
                        dcdOp <= instruction[31:28];
                        dcdOp <= instruction[31:28];
 
 
                        // Default values
                        // Default values
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
                        dcdA_cc <=  (instruction[27:24] == `CPU_CC_REG);
                        dcdA_cc <=  (instruction[27:24] == `CPU_CC_REG);
                        dcdB_cc <=  (instruction[19:16] == `CPU_CC_REG);
                        dcdB_cc <=  (instruction[19:16] == `CPU_CC_REG);
                        dcdA_pc <=  (instruction[27:24] == `CPU_PC_REG);
                        dcdA_pc <=  (instruction[27:24] == `CPU_PC_REG);
                        dcdB_pc <=  (instruction[19:16] == `CPU_PC_REG);
                        dcdB_pc <=  (instruction[19:16] == `CPU_PC_REG);
                        dcdM    <= 1'b0;
                        dcdM    <= 1'b0;
`ifdef  OPT_CONDITIONAL_FLAGS
`ifdef  OPT_CONDITIONAL_FLAGS
                        dcdF_wr <= (instruction[23:21]==3'h0);
                        // Don't change the flags on conditional instructions,
 
                        // UNLESS: the conditional instruction was a CMP
 
                        // or TST instruction.
 
                        dcdF_wr <= ((instruction[23:21]==3'h0)
 
                                        ||(instruction[31:29] == 3'h0));
`else
`else
                        dcdF_wr <= 1'b1;
                        dcdF_wr <= 1'b1;
`endif
`endif
`ifdef  OPT_PRECLEAR_BUS
`ifdef  OPT_PRECLEAR_BUS
                        dcd_clear_bus <= 1'b0;
                        dcd_clear_bus <= 1'b0;
`endif
`endif
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
                        dcd_illegal <= pf_illegal;
                        dcd_illegal <= pf_illegal;
`endif
`endif
 
 
                        // Set the condition under which we do this operation
                        // Set the condition under which we do this operation
                        // The top four bits are a mask, the bottom four the
                        // The top four bits are a mask, the bottom four the
                        // value the flags must equal once anded with the mask
                        // value the flags must equal once anded with the mask
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
                        casez(instruction[31:28])
                        casez(instruction[31:28])
                        4'h2: begin // Move instruction
                        4'h2: begin // Move instruction
                                if (~instruction_gie)
                                if (~instruction_gie)
                                begin
                                begin
                                        dcdA[4] <= instruction[20];
                                        dcdA[4] <= instruction[20];
                                        dcdB[4] <= instruction[15];
                                        dcdB[4] <= instruction[15];
                                end
                                end
                                dcdA_wr <= 1'b1;
                                dcdA_wr <= 1'b1;
                                dcdA_rd <= 1'b0;
                                dcdA_rd <= 1'b0;
                                dcdB_rd <= 1'b1;
                                dcdB_rd <= 1'b1;
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                                dcd_zI <= (instruction[14:0] == 0);
                                dcd_zI <= (instruction[14:0] == 0);
`endif
`endif
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdF_wr <= 1'b0; // Don't write flags
                                end
                                end
                        4'h3: begin // Load immediate
                        4'h3: begin // Load immediate
                                dcdA_wr <= 1'b1;
                                dcdA_wr <= 1'b1;
                                dcdA_rd <= 1'b0;
                                dcdA_rd <= 1'b0;
                                dcdB_rd <= 1'b0;
                                dcdB_rd <= 1'b0;
                                r_dcdI <= { instruction[23:0] };
                                r_dcdI <= { instruction[23:0] };
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                                dcd_zI <= (instruction[23:0] == 0);
                                dcd_zI <= (instruction[23:0] == 0);
`endif
`endif
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdF    <= 4'h8; // This is unconditional
                                dcdF    <= 4'h8; // This is unconditional
                                dcdOp <= 4'h2;
                                dcdOp <= 4'h2;
                                end
                                end
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
`ifdef  OPT_CONDITIONAL_FLAGS
`ifdef  OPT_CONDITIONAL_FLAGS
                                // Don't write flags except for multiplies
                                // Don't write flags except for multiplies
                                //   and then only if they are unconditional
                                //   and then only if they are unconditional
                                dcdF_wr <= ((instruction[27:25] != 3'h7)
                                dcdF_wr <= ((instruction[27:25] != 3'h7)
                                        &&(instruction[23:21]==3'h0));
                                        &&(instruction[23:21]==3'h0));
`else
`else
                                // Don't write flags except for multiplies
                                // Don't write flags except for multiplies
                                dcdF_wr <= (instruction[27:25] != 3'h7);
                                dcdF_wr <= (instruction[27:25] != 3'h7);
`endif
`endif
                                r_dcdI <= { 8'h00, instruction[15:0] };
                                r_dcdI <= { 8'h00, instruction[15:0] };
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                                dcd_zI <= (instruction[15:0] == 0);
                                dcd_zI <= (instruction[15:0] == 0);
`endif
`endif
                                if (instruction[27:24] == 4'he)
                                if (instruction[27:24] == 4'he)
                                begin
                                begin
                                        // NOOP instruction
                                        // NOOP instruction
                                        dcdA_wr <= 1'b0;
                                        dcdA_wr <= 1'b0;
                                        dcdA_rd <= 1'b0;
                                        dcdA_rd <= 1'b0;
                                        dcdB_rd <= 1'b0;
                                        dcdB_rd <= 1'b0;
                                        dcdOp <= 4'h2;
                                        dcdOp <= 4'h2;
                                        // Might also be a break.  Big
                                        // Might also be a break.  Big
                                        // instruction set hole here.
                                        // instruction set hole here.
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
                                        dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
                                        dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
`endif
`endif
                                end else if (instruction[27:24] == 4'hf)
                                end else if (instruction[27:24] == 4'hf)
                                begin // Load partial immediate(s)
                                begin // Load partial immediate(s)
                                        dcdA_wr <= 1'b1;
                                        dcdA_wr <= 1'b1;
                                        dcdA_rd <= 1'b1;
                                        dcdA_rd <= 1'b1;
                                        dcdB_rd <= 1'b0;
                                        dcdB_rd <= 1'b0;
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
                                        dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
                                        dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
                                        dcdOp <= { 3'h3, instruction[20] };
                                        dcdOp <= { 3'h3, instruction[20] };
                                end else begin
                                end else begin
                                        // Actual multiply instruction
                                        // Actual multiply instruction
                                        r_dcdI <= { 8'h00, instruction[15:0] };
                                        r_dcdI <= { 8'h00, instruction[15:0] };
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                                        dcd_zI <= (instruction[15:0] == 0);
                                        dcd_zI <= (instruction[15:0] == 0);
`endif
`endif
                                        dcdA_rd <= 1'b1;
                                        dcdA_rd <= 1'b1;
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
                                end end
                                end end
                        4'b011?: begin // LOD/STO or Load/Store
                        4'b011?: begin // LOD/STO or Load/Store
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdA_wr <= (~instruction[28]); // Write on loads
                                dcdA_wr <= (~instruction[28]); // Write on loads
                                dcdA_rd <= (instruction[28]); // Read on stores
                                dcdA_rd <= (instruction[28]); // Read on stores
                                dcdB_rd <= instruction[20];
                                dcdB_rd <= instruction[20];
                                if (instruction[20])
                                if (instruction[20])
                                begin
                                begin
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                                        dcd_zI <= (instruction[15:0] == 0);
                                        dcd_zI <= (instruction[15:0] == 0);
`endif
`endif
                                end else begin
                                end else begin
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                                        dcd_zI <= (instruction[19:0] == 0);
                                        dcd_zI <= (instruction[19:0] == 0);
`endif
`endif
                                end
                                end
                                dcdM <= 1'b1; // Memory operation
                                dcdM <= 1'b1; // Memory operation
`ifdef  OPT_PRECLEAR_BUS
`ifdef  OPT_PRECLEAR_BUS
                                dcd_clear_bus <= (instruction[23:21]==3'h0);
                                dcd_clear_bus <= (instruction[23:21]==3'h0);
`endif
`endif
                                end
                                end
                        default: begin
                        default: begin
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
                                dcdA_rd <= 1'b1;
                                dcdA_rd <= 1'b1;
                                dcdB_rd <= instruction[20];
                                dcdB_rd <= instruction[20];
                                if (instruction[20])
                                if (instruction[20])
                                begin
                                begin
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                                        dcd_zI <= (instruction[15:0] == 0);
                                        dcd_zI <= (instruction[15:0] == 0);
`endif
`endif
                                end else begin
                                end else begin
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                                        dcd_zI <= (instruction[19:0] == 0);
                                        dcd_zI <= (instruction[19:0] == 0);
`endif
`endif
                                end end
                                end end
                        endcase
                        endcase
 
 
 
 
                        dcd_gie <= instruction_gie;
                        dcd_gie <= instruction_gie;
                end
                end
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (dcd_ce)
                if (dcd_ce)
                        dcd_break <= (instruction[31:0] == 32'h4e000001);
                        dcd_break <= (instruction[31:0] == 32'h4e000001);
                else if ((clear_pipeline)||(~dcdvalid)) // SHOULDNT THIS BE ||op_ce?
                else if ((clear_pipeline)||(~dcdvalid)) // SHOULDNT THIS BE ||op_ce?
                        dcd_break <= 1'b0;
                        dcd_break <= 1'b0;
 
 
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
        reg     [23:0]   r_opI;
        reg     [23:0]   r_opI;
        reg     [4:0]    op_B;
        reg     [4:0]    op_B;
        reg             op_pipe;
        reg             op_pipe;
 
 
        initial op_pipe = 1'b0;
        initial op_pipe = 1'b0;
        // To be a pipeable operation, there must be 
        // To be a pipeable operation, there must be 
        //      two valid adjacent instructions
        //      two valid adjacent instructions
        //      Both must be memory instructions
        //      Both must be memory instructions
        //      Both must be writes, or both must be reads
        //      Both must be writes, or both must be reads
        //      Both operations must be to the same identical address,
        //      Both operations must be to the same identical address,
        //              or at least a single (one) increment above that address
        //              or at least a single (one) increment above that address
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
                        op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
                                &&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
                                &&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
                                &&(dcdB == op_B) // Same address register
                                &&(dcdB == op_B) // Same address register
                                &&(dcdF[2:0] == opF_cp) // Same condition
                                &&((dcdF[2:0] == opF_cp) // Same condition
 
                                        ||(opF_cp == 3'h0)) // or no prev condition
                                &&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
                                &&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                        r_opI <= r_dcdI;
                        r_opI <= r_dcdI;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                        op_B <= dcdB;
                        op_B <= dcdB;
`endif
`endif
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
        //
        //
        //
        //
        assign  w_opA = regset[dcdA];
        assign  w_opA = regset[dcdA];
        assign  w_opB = regset[dcdB];
        assign  w_opB = regset[dcdB];
 
 
        wire    [31:0]   w_pcA_v;
        wire    [31:0]   w_pcA_v;
        generate
        generate
        if (AW < 32)
        if (AW < 32)
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
        else
        else
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
        endgenerate
        endgenerate
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                begin
                begin
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
                                r_opA <= wr_reg_vl;
                                r_opA <= wr_reg_vl;
                        else if (dcdA_pc)
                        else if (dcdA_pc)
                                r_opA <= w_pcA_v;
                                r_opA <= w_pcA_v;
                        else if (dcdA_cc)
                        else if (dcdA_cc)
                                r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
                                r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
                        else
                        else
                                r_opA <= w_opA;
                                r_opA <= w_opA;
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                end else if (opvalid)
                end else if (opvalid)
                begin // We were going to pick these up when they became valid,
                begin // We were going to pick these up when they became valid,
                        // but for some reason we're stuck here as they became
                        // but for some reason we're stuck here as they became
                        // valid.  Pick them up now anyway
                        // valid.  Pick them up now anyway
                        if (((opA_alu)&&(alu_valid)&&(alu_wr))||((opA_mem)&&(mem_valid)))
                        if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
                                r_opA <= wr_reg_vl;
                                r_opA <= wr_reg_vl;
`endif
`endif
                end
                end
 
 
        wire    [31:0]   dcdI, w_opBnI, w_pcB_v;
        wire    [31:0]   dcdI, w_opBnI, w_pcB_v;
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
        generate
        generate
        if (AW < 32)
        if (AW < 32)
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
        else
        else
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
        endgenerate
        endgenerate
 
 
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
                : ((dcdB_pc) ? w_pcB_v
                : ((dcdB_pc) ? w_pcB_v
                : ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
                : ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
                : w_opB)));
                : w_opB)));
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                        r_opB <= w_opBnI + dcdI;
                        r_opB <= w_opBnI + dcdI;
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                else if ((opvalid)&&(
                else if ((opvalid)&&(
                                ((opB_alu)&&(alu_valid)&&(alu_wr))
                                ((opB_alu)&&(alu_wr))
                                ||((opB_mem)&&(mem_valid))))
                                ||((opB_mem)&&(mem_valid))))
                        r_opB <= wr_reg_vl;
                        r_opB <= wr_reg_vl;
`endif
`endif
 
 
        // The logic here has become more complex than it should be, no thanks
        // The logic here has become more complex than it should be, no thanks
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
        // be two sets of four bits: the top bits specify what bits matter, the
        // be two sets of four bits: the top bits specify what bits matter, the
        // bottom specify what those top bits must equal.  However, two of
        // bottom specify what those top bits must equal.  However, two of
        // conditions check whether bits are on, and those are the only two
        // conditions check whether bits are on, and those are the only two
        // conditions checking those bits.  Therefore, Vivado complains that
        // conditions checking those bits.  Therefore, Vivado complains that
        // these two bits are redundant.  Hence the convoluted expression
        // these two bits are redundant.  Hence the convoluted expression
        // below, arriving at what we finally want in the (now wire net)
        // below, arriving at what we finally want in the (now wire net)
        // opF.
        // opF.
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
                        case(dcdF[2:0])
                        case(dcdF[2:0])
                        3'h0:   r_opF <= 6'h00; // Always
                        3'h0:   r_opF <= 6'h00; // Always
                        3'h1:   r_opF <= 6'h11; // Z
                        3'h1:   r_opF <= 6'h11; // Z
                        3'h2:   r_opF <= 6'h10; // NE
                        3'h2:   r_opF <= 6'h10; // NE
                        3'h3:   r_opF <= 6'h20; // GE (!N)
                        3'h3:   r_opF <= 6'h20; // GE (!N)
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
                        3'h5:   r_opF <= 6'h24; // LT
                        3'h5:   r_opF <= 6'h24; // LT
                        3'h6:   r_opF <= 6'h02; // C
                        3'h6:   r_opF <= 6'h02; // C
                        3'h7:   r_opF <= 6'h08; // V
                        3'h7:   r_opF <= 6'h08; // V
                        endcase
                        endcase
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opF_cp[2:0] <= dcdF[2:0];
                        opF_cp[2:0] <= dcdF[2:0];
 
 
        initial opvalid     = 1'b0;
        initial opvalid     = 1'b0;
        initial opvalid_alu = 1'b0;
        initial opvalid_alu = 1'b0;
        initial opvalid_mem = 1'b0;
        initial opvalid_mem = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                begin
                begin
                        opvalid     <= 1'b0;
                        opvalid     <= 1'b0;
                        opvalid_alu <= 1'b0;
                        opvalid_alu <= 1'b0;
                        opvalid_mem <= 1'b0;
                        opvalid_mem <= 1'b0;
                end else if (op_ce)
                end else if (op_ce)
                begin
                begin
                        // Do we have a valid instruction?
                        // Do we have a valid instruction?
                        //   The decoder may vote to stall one of its
                        //   The decoder may vote to stall one of its
                        //   instructions based upon something we currently
                        //   instructions based upon something we currently
                        //   have in our queue.  This instruction must then
                        //   have in our queue.  This instruction must then
                        //   move forward, and get a stall cycle inserted.
                        //   move forward, and get a stall cycle inserted.
                        //   Hence, the test on dcd_stalled here.  If we must
                        //   Hence, the test on dcd_stalled here.  If we must
                        //   wait until our operands are valid, then we aren't
                        //   wait until our operands are valid, then we aren't
                        //   valid yet until then.
                        //   valid yet until then.
                        opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
`else
`else
                        opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
`endif
`endif
                end else if ((~op_stall)||(clear_pipeline))
                end else if ((~op_stall)||(clear_pipeline))
                begin
                begin
                        opvalid     <= 1'b0;
                        opvalid     <= 1'b0;
                        opvalid_alu <= 1'b0;
                        opvalid_alu <= 1'b0;
                        opvalid_mem <= 1'b0;
                        opvalid_mem <= 1'b0;
                end
                end
 
 
        // Here's part of our debug interface.  When we recognize a break
        // Here's part of our debug interface.  When we recognize a break
        // instruction, we set the op_break flag.  That'll prevent this
        // instruction, we set the op_break flag.  That'll prevent this
        // instruction from entering the ALU, and cause an interrupt before
        // instruction from entering the ALU, and cause an interrupt before
        // this instruction.  Thus, returning to this code will cause the
        // this instruction.  Thus, returning to this code will cause the
        // break to repeat and continue upon return.  To get out of this
        // break to repeat and continue upon return.  To get out of this
        // condition, replace the break instruction with what it is supposed
        // condition, replace the break instruction with what it is supposed
        // to be, step through it, and then replace it back.  In this fashion,
        // to be, step through it, and then replace it back.  In this fashion,
        // a debugger can step through code.
        // a debugger can step through code.
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
        initial op_break = 1'b0;
        initial op_break = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)      op_break <= 1'b0;
                if (i_rst)      op_break <= 1'b0;
                else if (op_ce) op_break <= (dcd_break);
                else if (op_ce) op_break <= (dcd_break);
                else if ((clear_pipeline)||(~opvalid))
                else if ((clear_pipeline)||(~opvalid))
                                op_break <= 1'b0;
                                op_break <= 1'b0;
 
 
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        always @(posedge i_clk)
        always @(posedge i_clk)
                if(op_ce)
                if(op_ce)
                        op_illegal <= dcd_illegal;
                        op_illegal <= dcd_illegal;
`endif
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                begin
                begin
                        opn    <= dcdOp;        // Which ALU operation?
                        opn    <= dcdOp;        // Which ALU operation?
                        // opM  <= dcdM;        // Is this a memory operation?
                        // opM  <= dcdM;        // Is this a memory operation?
`ifdef  OPT_EARLY_BRANCHING
`ifdef  OPT_EARLY_BRANCHING
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
                        opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
                        opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
`else
`else
                        // Will we write the flags/CC Register with our result?
                        // Will we write the flags/CC Register with our result?
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
                        // Will we be writing our results into a register?
                        // Will we be writing our results into a register?
                        opR_wr <= dcdA_wr;
                        opR_wr <= dcdA_wr;
`endif
`endif
                        // What register will these results be written into?
                        // What register will these results be written into?
                        opR    <= dcdA;
                        opR    <= dcdA;
                        opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
                        opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
                        // User level (1), vs supervisor (0)/interrupts disabled
                        // User level (1), vs supervisor (0)/interrupts disabled
                        op_gie <= dcd_gie;
                        op_gie <= dcd_gie;
 
 
                        //
                        //
`ifdef  OPT_EARLY_BRANCHING
`ifdef  OPT_EARLY_BRANCHING
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
`else
`else
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
`endif
`endif
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
                        // op_pc  <= dcd_pc;
                        // op_pc  <= dcd_pc;
 
 
`ifdef  OPT_PRECLEAR_BUS
`ifdef  OPT_PRECLEAR_BUS
                        op_clear_bus <= dcd_clear_bus;
                        op_clear_bus <= dcd_clear_bus;
`endif
`endif
                end
                end
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
 
 
        // This is tricky.  First, the PC and Flags registers aren't kept in
        // This is tricky.  First, the PC and Flags registers aren't kept in
        // register set but in special registers of their own.  So step one
        // register set but in special registers of their own.  So step one
        // is to select the right register.  Step to is to replace that
        // is to select the right register.  Step to is to replace that
        // register with the results of an ALU or memory operation, if such
        // register with the results of an ALU or memory operation, if such
        // results are now available.  Otherwise, we'd need to insert a wait
        // results are now available.  Otherwise, we'd need to insert a wait
        // state of some type.
        // state of some type.
        //
        //
        // The alternative approach would be to define some sort of
        // The alternative approach would be to define some sort of
        // op_stall wire, which would stall any upstream stage.
        // op_stall wire, which would stall any upstream stage.
        // We'll create a flag here to start our coordination.  Once we
        // We'll create a flag here to start our coordination.  Once we
        // define this flag to something other than just plain zero, then
        // define this flag to something other than just plain zero, then
        // the stalls will already be in place.
        // the stalls will already be in place.
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
        initial opA_alu = 1'b0;
        initial opA_alu = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(opR_wr)&&(dcdA_rd);
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(opR_wr)&&(dcdA_rd);
                else if ((opvalid)&&(opA_alu)&&(alu_valid))
                else if ((opvalid)&&(opA_alu)&&(alu_valid))
                        opA_alu <= 1'b0;
                        opA_alu <= 1'b0;
        initial opA_mem = 1'b0;
        initial opA_mem = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opA_mem <= ((opvalid_mem)&&(opR == dcdA)&&(dcdA_rd)&&(~opn[0]))
                        opA_mem <= ((opvalid_mem)&&(opR == dcdA)&&(dcdA_rd)&&(~opn[0]))
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
                                        &&(mem_last_reg == dcdA)&&(dcdA_rd));
                                        &&(mem_last_reg == dcdA)&&(dcdA_rd));
                else if ((opvalid)&&(opA_mem)&&(mem_valid))
                else if ((opvalid)&&(opA_mem)&&(mem_valid))
                        opA_mem <= 1'b0;
                        opA_mem <= 1'b0;
`endif
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (mem_ce)
                if (mem_ce)
                        mem_last_reg <= opR;
                        mem_last_reg <= opR;
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
        assign  opA = ((opA_alu)&&(alu_valid)&&(alu_wr)) ? alu_result
        assign  opA = ((opA_alu)&&(alu_wr)) ? alu_result
                        : ( ((opA_mem)&&(mem_valid))?mem_result
                        : ( ((opA_mem)&&(mem_valid))?mem_result
                        : r_opA );
                        : r_opA );
`else
`else
        assign  opA = r_opA;
        assign  opA = r_opA;
`endif
`endif
 
 
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                // Skip the requirement on writing back opA
                // Skip the requirement on writing back opA
                // Stall on memory, since we'll always need to stall for a 
                // Stall on memory, since we'll always need to stall for a 
                // memory access anyway
                // memory access anyway
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
`else
`else
                                ((opvalid)&&(opR_wr)&&(opR == dcdA))
                                ((opvalid)&&(opR_wr)&&(opR == dcdA))
                                ||((opvalid_alu)&&(opF_wr)&&(dcdA_cc))
                                ||((opvalid_alu)&&(opF_wr)&&(dcdA_cc))
                                ||((mem_rdbusy)&&(mem_last_reg == dcdA))
                                ||((mem_rdbusy)&&(mem_last_reg == dcdA))
                                );
                                );
`endif
`endif
 
 
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opB_mem <= (dcd_zI)&&(dcdB_rd)&&(
                        opB_mem <= (dcd_zI)&&(dcdB_rd)&&(
                                ((opvalid_mem)&&(opR == dcdB)&&(~opn[0]))
                                ((opvalid_mem)&&(opR == dcdB)&&(~opn[0]))
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
                                        &&(mem_last_reg == dcdB)));
                                        &&(mem_last_reg == dcdB)));
                else if ((opvalid)&&(opB_mem)&&(mem_valid))
                else if ((opvalid)&&(opB_mem)&&(mem_valid))
                        opB_mem <= 1'b0;
                        opB_mem <= 1'b0;
        assign  opB = ((opB_alu)&&(alu_valid)&&(alu_wr)) ? alu_result
        assign  opB = ((opB_alu)&&(alu_wr)) ? alu_result
                        : ( ((opB_mem)&&(mem_valid))?mem_result
                        : ( ((opB_mem)&&(mem_valid))?mem_result
                        : r_opB );
                        : r_opB );
`else
`else
        assign  opB = r_opB;
        assign  opB = r_opB;
`endif
`endif
 
 
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_SINGLE_CYCLE
                                // Stall on memory ops writing to my register
                                // Stall on memory ops writing to my register
                                //      (i.e. loads), or on any write to my
                                //      (i.e. loads), or on any write to my
                                //      register if I have an immediate offset
                                //      register if I have an immediate offset
                                // Note the exception for writing to the PC:
                                // Note the exception for writing to the PC:
                                //      if I write to the PC, the whole next
                                //      if I write to the PC, the whole next
                                //      instruction is invalid, not just the
                                //      instruction is invalid, not just the
                                //      operand.  That'll get wiped in the
                                //      operand.  That'll get wiped in the
                                //      next operation anyway, so don't stall
                                //      next operation anyway, so don't stall
                                //      here.
                                //      here.
                                ((opvalid)&&(opR_wr)&&(opR == dcdB)
                                ((opvalid)&&(opR_wr)&&(opR == dcdB)
                                        &&(opR != { op_gie, `CPU_PC_REG} )
                                        &&(opR != { op_gie, `CPU_PC_REG} )
                                        &&(~dcd_zI))
                                        &&(~dcd_zI))
                                // Stall on any write to the flags register,
                                // Stall on any write to the flags register,
                                // if we're going to need the flags value for
                                // if we're going to need the flags value for
                                // opB.
                                // opB.
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
                                // Stall on any ongoing memory operation that
                                // Stall on any ongoing memory operation that
                                // will write to opB
                                // will write to opB
                                ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
                                ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
`else
`else
                                ((opvalid)&&(opR_wr)&&(opR == dcdB))
                                ((opvalid)&&(opR_wr)&&(opR == dcdB))
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
                                ||((mem_rdbusy)&&(mem_last_reg == dcdB))
                                ||((mem_rdbusy)&&(mem_last_reg == dcdB))
                                );
                                );
`endif
`endif
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
                                        &&(opvalid)&&(opR_cc);
                                        &&(opvalid)&&(opR_cc);
        //
        //
        //
        //
        //      PIPELINE STAGE #4 :: Apply Instruction
        //      PIPELINE STAGE #4 :: Apply Instruction
        //
        //
        //
        //
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
                        (opvalid_alu), opn, opA, opB,
                        (opvalid_alu), opn, opA, opB,
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
 
 
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
        initial alF_wr   = 1'b0;
        initial alF_wr   = 1'b0;
        initial alu_wr   = 1'b0;
        initial alu_wr   = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                begin
                begin
                        alu_wr   <= 1'b0;
                        alu_wr   <= 1'b0;
                        alF_wr   <= 1'b0;
                        alF_wr   <= 1'b0;
                end else if (alu_ce)
                end else if (alu_ce)
                begin
                begin
                        alu_reg <= opR;
                        // alu_reg <= opR;
                        alu_wr  <= (opR_wr)&&(set_cond);
                        alu_wr  <= (opR_wr)&&(set_cond);
                        alF_wr  <= (opF_wr)&&(set_cond);
                        alF_wr  <= (opF_wr)&&(set_cond);
                end else begin
                end else begin
                        // These are strobe signals, so clear them if not
                        // These are strobe signals, so clear them if not
                        // set for any particular clock
                        // set for any particular clock
                        alu_wr <= 1'b0;
                        alu_wr <= (i_halt)&&(i_dbg_we);
                        alF_wr <= 1'b0;
                        alF_wr <= 1'b0;
                end
                end
        always @(posedge i_clk)
        always @(posedge i_clk)
 
                if (alu_ce)
 
                        alu_reg <= opR;
 
                else if ((i_halt)&&(i_dbg_we))
 
                        alu_reg <= i_dbg_reg;
 
        reg     [31:0]   dbg_val;
 
        reg             dbgv;
 
        always @(posedge i_clk)
 
                dbg_val <= i_dbg_data;
 
        initial dbgv = 1'b0;
 
        always @(posedge i_clk)
 
                dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we));
 
        always @(posedge i_clk)
                if ((alu_ce)||(mem_ce))
                if ((alu_ce)||(mem_ce))
                        alu_gie  <= op_gie;
                        alu_gie  <= op_gie;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((alu_ce)||(mem_ce))
                if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
 
                                &&(~mem_stalled)))
                        alu_pc  <= op_pc;
                        alu_pc  <= op_pc;
 
 
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        reg     r_alu_illegal;
        reg     r_alu_illegal;
        initial r_alu_illegal = 0;
        initial r_alu_illegal = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((alu_ce)||(mem_ce))
                if ((alu_ce)||(mem_ce))
                        r_alu_illegal <= op_illegal;
                        r_alu_illegal <= op_illegal;
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
`endif
`endif
 
 
 
        // This _almost_ is equal to (alu_ce)||(mem_ce).  The only
 
        // problem is that mem_ce is gated by the set_cond, and
 
        // the PC will be valid independent of the set condition.  Hence, this
 
        // equals (alu_ce)||(everything in mem_ce but the set condition)
        initial alu_pc_valid = 1'b0;
        initial alu_pc_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(~mem_rdbusy)&&(opvalid)&&(~clear_pipeline)
                alu_pc_valid <= ((alu_ce)
                                        &&((opvalid_alu)||(~mem_stalled));
                        ||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)&&(~mem_stalled)));
 
 
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
        pipemem #(AW) domem(i_clk, i_rst, mem_ce,
        pipemem #(AW) domem(i_clk, i_rst, mem_ce,
                                (opn[0]), opB, opA, opR,
                                (opn[0]), opB, opA, opR,
                                mem_busy, mem_pipe_stalled,
                                mem_busy, mem_pipe_stalled,
                                mem_valid, bus_err, mem_wreg, mem_result,
                                mem_valid, bus_err, mem_wreg, mem_result,
                        mem_cyc_gbl, mem_cyc_lcl,
                        mem_cyc_gbl, mem_cyc_lcl,
                                mem_stb_gbl, mem_stb_lcl,
                                mem_stb_gbl, mem_stb_lcl,
                                mem_we, mem_addr, mem_data,
                                mem_we, mem_addr, mem_data,
                                mem_ack, mem_stall, mem_err, i_wb_data);
                                mem_ack, mem_stall, mem_err, i_wb_data);
 
 
`else // PIPELINED_BUS_ACCESS
`else // PIPELINED_BUS_ACCESS
        memops  #(AW) domem(i_clk, i_rst, mem_ce,
        memops  #(AW) domem(i_clk, i_rst, mem_ce,
                                (opn[0]), opB, opA, opR,
                                (opn[0]), opB, opA, opR,
                                mem_busy,
                                mem_busy,
                                mem_valid, bus_err, mem_wreg, mem_result,
                                mem_valid, bus_err, mem_wreg, mem_result,
                        mem_cyc_gbl, mem_cyc_lcl,
                        mem_cyc_gbl, mem_cyc_lcl,
                                mem_stb_gbl, mem_stb_lcl,
                                mem_stb_gbl, mem_stb_lcl,
                                mem_we, mem_addr, mem_data,
                                mem_we, mem_addr, mem_data,
                                mem_ack, mem_stall, mem_err, i_wb_data);
                                mem_ack, mem_stall, mem_err, i_wb_data);
`endif // PIPELINED_BUS_ACCESS
`endif // PIPELINED_BUS_ACCESS
        assign  mem_rdbusy = (((mem_cyc_gbl)||(mem_cyc_lcl))&&(~mem_we));
        assign  mem_rdbusy = ((mem_busy)&&(~mem_we));
 
 
        // Either the prefetch or the instruction gets the memory bus, but 
        // Either the prefetch or the instruction gets the memory bus, but 
        // never both.
        // never both.
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
                // Memory access to the arbiter, priority position
                // Memory access to the arbiter, priority position
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
                // Prefetch access to the arbiter
                // Prefetch access to the arbiter
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
                        pf_ack, pf_stall, pf_err,
                        pf_ack, pf_stall, pf_err,
                // Common wires, in and out, of the arbiter
                // Common wires, in and out, of the arbiter
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
                        o_wb_we, o_wb_addr, o_wb_data,
                        o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_err);
                        i_wb_ack, i_wb_stall, i_wb_err);
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #5 :: Write-back results
        //      PIPELINE STAGE #5 :: Write-back results
        //
        //
        //
        //
        // This stage is not allowed to stall.  If results are ready to be
        // This stage is not allowed to stall.  If results are ready to be
        // written back, they are written back at all cost.  Sleepy CPU's
        // written back, they are written back at all cost.  Sleepy CPU's
        // won't prevent write back, nor debug modes, halting the CPU, nor
        // won't prevent write back, nor debug modes, halting the CPU, nor
        // anything else.  Indeed, the (master_ce) bit is only as relevant
        // anything else.  Indeed, the (master_ce) bit is only as relevant
        // as knowinig something is available for writeback.
        // as knowinig something is available for writeback.
 
 
        //
        //
        // Write back to our generic register set ...
        // Write back to our generic register set ...
        // When shall we write back?  On one of two conditions
        // When shall we write back?  On one of two conditions
        //      Note that the flags needed to be checked before issuing the
        //      Note that the flags needed to be checked before issuing the
        //      bus instruction, so they don't need to be checked here.
        //      bus instruction, so they don't need to be checked here.
        //      Further, alu_wr includes (set_cond), so we don't need to
        //      Further, alu_wr includes (set_cond), so we don't need to
        //      check for that here either.
        //      check for that here either.
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        assign  wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
        assign  wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(~clear_pipeline))||(mem_valid);
`else
`else
        assign  wr_reg_ce = ((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
        assign  wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid);
`endif
`endif
        // Which register shall be written?
        // Which register shall be written?
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
        //              One or PC, one for CC, and one for GIE match
        //              One or PC, one for CC, and one for GIE match
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
        // Are we writing to the CC register?
        // Are we writing to the CC register?
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
        // Are we writing to the PC?
        // Are we writing to the PC?
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
        // What value to write?
        // What value to write?
        assign  wr_reg_vl = (alu_wr)?alu_result:mem_result;
        assign  wr_reg_vl = (alu_wr)?((dbgv)?dbg_val: alu_result) :mem_result;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (wr_reg_ce)
                if (wr_reg_ce)
                        regset[wr_reg_id] <= wr_reg_vl;
                        regset[wr_reg_id] <= wr_reg_vl;
                else if ((i_halt)&&(i_dbg_we))
 
                        regset[i_dbg_reg] <= i_dbg_data[31:0];
 
 
 
        //
        //
        // Write back to the condition codes/flags register ...
        // Write back to the condition codes/flags register ...
        // When shall we write to our flags register?  alF_wr already
        // When shall we write to our flags register?  alF_wr already
        // includes the set condition ...
        // includes the set condition ...
        assign  wr_flags_ce = (alF_wr)&&(alu_valid)&&(~clear_pipeline)&&(~alu_illegal);
        assign  wr_flags_ce = (alF_wr)&&(~clear_pipeline)&&(~alu_illegal);
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        assign  w_uflags = { bus_err_flag, trap, ill_err,    1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
        assign  w_uflags = { ubus_err_flag, trap, ill_err_u,    1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
        assign  w_iflags = { bus_err_flag, trap, ill_err,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
        assign  w_iflags = { ibus_err_flag, trap, ill_err_i,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
`else
`else
        assign  w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
        assign  w_uflags = { ubus_err_flag, trap, ill_err_u,     1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
        assign  w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
        assign  w_iflags = { ibus_err_flag, trap, ill_err_i, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
`endif
`endif
        // What value to write?
        // What value to write?
        always @(posedge i_clk)
        always @(posedge i_clk)
                // If explicitly writing the register itself
                // If explicitly writing the register itself
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
                        flags <= wr_reg_vl[3:0];
                        flags <= wr_reg_vl[3:0];
                // Otherwise if we're setting the flags from an ALU operation
                // Otherwise if we're setting the flags from an ALU operation
                else if ((wr_flags_ce)&&(alu_gie))
                else if ((wr_flags_ce)&&(alu_gie))
                        flags <= alu_flags;
                        flags <= alu_flags;
                else if ((i_halt)&&(i_dbg_we)
 
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
 
                        flags <= i_dbg_data[3:0];
 
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                        iflags <= wr_reg_vl[3:0];
                        iflags <= wr_reg_vl[3:0];
                else if ((wr_flags_ce)&&(~alu_gie))
                else if ((wr_flags_ce)&&(~alu_gie))
                        iflags <= alu_flags;
                        iflags <= alu_flags;
                else if ((i_halt)&&(i_dbg_we)
 
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
 
                        iflags <= i_dbg_data[3:0];
 
 
 
        // The 'break' enable  bit.  This bit can only be set from supervisor
        // The 'break' enable  bit.  This bit can only be set from supervisor
        // mode.  It control what the CPU does upon encountering a break
        // mode.  It control what the CPU does upon encountering a break
        // instruction.
        // instruction.
        //
        //
        // The goal, upon encountering a break is that the CPU should stop and
        // The goal, upon encountering a break is that the CPU should stop and
        // not execute the break instruction, choosing instead to enter into
        // not execute the break instruction, choosing instead to enter into
        // either interrupt mode or halt first.  
        // either interrupt mode or halt first.  
        //      if ((break_en) AND (break_instruction)) // user mode or not
        //      if ((break_en) AND (break_instruction)) // user mode or not
        //              HALT CPU
        //              HALT CPU
        //      else if (break_instruction) // only in user mode
        //      else if (break_instruction) // only in user mode
        //              set an interrupt flag, go to supervisor mode
        //              set an interrupt flag, go to supervisor mode
        //              allow supervisor to step the CPU.
        //              allow supervisor to step the CPU.
        //      Upon a CPU halt, any break condition will be reset.  The
        //      Upon a CPU halt, any break condition will be reset.  The
        //      external debugger will then need to deal with whatever
        //      external debugger will then need to deal with whatever
        //      condition has taken place.
        //      condition has taken place.
        initial break_en = 1'b0;
        initial break_en = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_halt))
                if ((i_rst)||(i_halt))
                        break_en <= 1'b0;
                        break_en <= 1'b0;
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
                else if ((i_halt)&&(i_dbg_we)
 
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
 
                        break_en <= i_dbg_data[`CPU_BREAK_BIT];
 
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
                                &&(~clear_pipeline)
                                &&(~clear_pipeline)
                        ||((~alu_gie)&&(bus_err))
                        ||((~alu_gie)&&(bus_err))
                        ||((~alu_gie)&&(alu_valid)&&(alu_illegal));
                        ||((~alu_gie)&&(alu_valid)&&(alu_illegal));
`else
`else
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
                                &&(~clear_pipeline))
                                &&(~clear_pipeline))
                        ||((~alu_gie)&&(bus_err));
                        ||((~alu_gie)&&(bus_err));
`endif
`endif
 
 
 
 
        // The sleep register.  Setting the sleep register causes the CPU to
        // The sleep register.  Setting the sleep register causes the CPU to
        // sleep until the next interrupt.  Setting the sleep register within
        // sleep until the next interrupt.  Setting the sleep register within
        // interrupt mode causes the processor to halt until a reset.  This is
        // interrupt mode causes the processor to halt until a reset.  This is
        // a panic/fault halt.  The trick is that you cannot be allowed to
        // a panic/fault halt.  The trick is that you cannot be allowed to
        // set the sleep bit and switch to supervisor mode in the same 
        // set the sleep bit and switch to supervisor mode in the same 
        // instruction: users are not allowed to halt the CPU.
        // instruction: users are not allowed to halt the CPU.
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||((i_interrupt)&&(gie)))
                if ((i_rst)||((i_interrupt)&&(gie)))
                        sleep <= 1'b0;
                        sleep <= 1'b0;
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
                        // In supervisor mode, we have no protections.  The
                        // In supervisor mode, we have no protections.  The
                        // supervisor can set the sleep bit however he wants.
                        // supervisor can set the sleep bit however he wants.
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
                        // In user mode, however, you can only set the sleep
                        // In user mode, however, you can only set the sleep
                        // mode while remaining in user mode.  You can't switch
                        // mode while remaining in user mode.  You can't switch
                        // to sleep mode *and* supervisor mode at the same
                        // to sleep mode *and* supervisor mode at the same
                        // time, lest you halt the CPU.
                        // time, lest you halt the CPU.
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
                else if ((i_halt)&&(i_dbg_we)
 
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
 
                        sleep <= i_dbg_data[`CPU_SLEEP_BIT];
 
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(w_switch_to_interrupt))
                if ((i_rst)||(w_switch_to_interrupt))
                        step <= 1'b0;
                        step <= 1'b0;
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
                        step <= wr_reg_vl[`CPU_STEP_BIT];
                        step <= wr_reg_vl[`CPU_STEP_BIT];
                else if ((i_halt)&&(i_dbg_we)
 
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
 
                        step <= i_dbg_data[`CPU_STEP_BIT];
 
                else if ((alu_pc_valid)&&(step)&&(gie))
                else if ((alu_pc_valid)&&(step)&&(gie))
                        step <= 1'b0;
                        step <= 1'b0;
 
 
        // The GIE register.  Only interrupts can disable the interrupt register
        // The GIE register.  Only interrupts can disable the interrupt register
        assign  w_switch_to_interrupt = (gie)&&(
        assign  w_switch_to_interrupt = (gie)&&(
                        // On interrupt (obviously)
                        // On interrupt (obviously)
                        (i_interrupt)
                        (i_interrupt)
                        // If we are stepping the CPU
                        // If we are stepping the CPU
                        ||((alu_pc_valid)&&(step))
                        ||((alu_pc_valid)&&(step))
                        // If we encounter a break instruction, if the break
                        // If we encounter a break instruction, if the break
                        //      enable isn't set.
                        //      enable isn't set.
                        ||((master_ce)&&(~mem_rdbusy)&&(op_break)&&(~break_en))
                        ||((master_ce)&&(~mem_rdbusy)&&(op_break)&&(~break_en))
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
                        // On an illegal instruction
                        // On an illegal instruction
                        ||((alu_valid)&&(alu_illegal))
                        ||((alu_valid)&&(alu_illegal))
`endif
`endif
                        // If we write to the CC register
                        // If we write to the CC register
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                                &&(wr_reg_id[4])&&(wr_write_cc))
                                &&(wr_reg_id[4])&&(wr_write_cc))
                        // Or if, in debug mode, we write to the CC register
 
                        ||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
 
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
 
                        );
                        );
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
                        // Then if we write the CC register
                        // Then if we write the CC register
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
                                &&(~wr_reg_id[4])&&(wr_write_cc))
                                &&(~wr_reg_id[4])&&(wr_write_cc))
                        // Or if, in debug mode, we write the CC register
 
                          ||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
 
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
 
                        );
                        );
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        gie <= 1'b0;
                        gie <= 1'b0;
                else if (w_switch_to_interrupt)
                else if (w_switch_to_interrupt)
                        gie <= 1'b0;
                        gie <= 1'b0;
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        gie <= 1'b1;
                        gie <= 1'b1;
 
 
        initial trap = 1'b0;
        initial trap = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        trap <= 1'b0;
                        trap <= 1'b0;
                else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                                &&(wr_reg_id[4])&&(wr_write_cc))
                                &&(wr_reg_id[4])&&(wr_write_cc))
                        trap <= 1'b1;
                        trap <= 1'b1;
                else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
                // else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
                                &&(~i_dbg_data[`CPU_GIE_BIT]))
                                // &&(~i_dbg_data[`CPU_GIE_BIT]))
                        trap <= i_dbg_data[`CPU_TRAP_BIT];
                        // trap <= i_dbg_data[`CPU_TRAP_BIT];
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        trap <= 1'b0;
                        trap <= 1'b0;
 
 
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        initial ill_err = 1'b0;
        initial ill_err_i = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        ill_err <= 1'b0;
                        ill_err_i <= 1'b0;
 
                // The debug interface can clear this bit
 
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
 
                                &&(~wr_reg_vl[`CPU_ILL_BIT]))
 
                        ill_err_i <= 1'b0;
 
                else if ((alu_valid)&&(alu_illegal)&&(~alu_gie))
 
                        ill_err_i <= 1'b1;
 
        initial ill_err_u = 1'b0;
 
        always @(posedge i_clk)
 
                if (i_rst)
 
                        ill_err_u <= 1'b0;
 
                // The bit is automatically cleared on release from interrupt
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        ill_err <= 1'b0;
                        ill_err_u <= 1'b0;
 
                // If the supervisor writes to this register, clearing the
 
                // bit, then clear it
 
                else if (((~alu_gie)||(dbgv))
 
                                &&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT])
 
                                &&(wr_reg_id[4])&&(wr_write_cc))
 
                        ill_err_u <= 1'b0;
                else if ((alu_valid)&&(alu_illegal)&&(gie))
                else if ((alu_valid)&&(alu_illegal)&&(gie))
                        ill_err <= 1'b1;
                        ill_err_u <= 1'b1;
`else
`else
        assign ill_err = 1'b0;
        assign ill_err_u = 1'b0;
 
        assign ill_err_i = 1'b0;
`endif
`endif
        initial bus_err_flag = 1'b0;
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
 
        // ever set.
 
        initial ibus_err_flag = 1'b0;
 
        always @(posedge i_clk)
 
                if (i_rst)
 
                        ibus_err_flag <= 1'b0;
 
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
 
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT]))
 
                        ibus_err_flag <= 1'b0;
 
                else if ((bus_err)&&(~alu_gie))
 
                        ibus_err_flag <= 1'b1;
 
        // User bus error flag -- if ever set, it will cause an interrupt to
 
        // supervisor mode.  
 
        initial ubus_err_flag = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        bus_err_flag <= 1'b0;
                        ubus_err_flag <= 1'b0;
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        bus_err_flag <= 1'b0;
                        ubus_err_flag <= 1'b0;
 
                // else if ((i_halt)&&(i_dbg_we)&&(~i_dbg_reg[4])
 
                                // &&(i_dbg_reg == {1'b1, `CPU_CC_REG})
 
                                // &&(~i_dbg_data[`CPU_BUSERR_BIT]))
 
                        // ubus_err_flag <= 1'b0;
 
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
 
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT])
 
                                &&(wr_reg_id[4])&&(wr_write_cc))
 
                        ubus_err_flag <= 1'b0;
                else if ((bus_err)&&(alu_gie))
                else if ((bus_err)&&(alu_gie))
                        bus_err_flag <= 1'b1;
                        ubus_err_flag <= 1'b1;
 
 
        //
        //
        // Write backs to the PC register, and general increments of it
        // Write backs to the PC register, and general increments of it
        //      We support two: upc and ipc.  If the instruction is normal,
        //      We support two: upc and ipc.  If the instruction is normal,
        // we increment upc, if interrupt level we increment ipc.  If
        // we increment upc, if interrupt level we increment ipc.  If
        // the instruction writes the PC, we write whichever PC is appropriate.
        // the instruction writes the PC, we write whichever PC is appropriate.
        //
        //
        // Do we need to all our partial results from the pipeline?
        // Do we need to all our partial results from the pipeline?
        // What happens when the pipeline has gie and ~gie instructions within
        // What happens when the pipeline has gie and ~gie instructions within
        // it?  Do we clear both?  What if a gie instruction tries to clear
        // it?  Do we clear both?  What if a gie instruction tries to clear
        // a non-gie instruction?
        // a non-gie instruction?
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
                        upc <= wr_reg_vl[(AW-1):0];
                        upc <= wr_reg_vl[(AW-1):0];
                else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
                else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
                        upc <= alu_pc;
                        upc <= alu_pc;
                else if ((i_halt)&&(i_dbg_we)
 
                                &&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
 
                        upc <= i_dbg_data[(AW-1):0];
 
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        ipc <= RESET_ADDRESS;
                        ipc <= RESET_ADDRESS;
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
                        ipc <= wr_reg_vl[(AW-1):0];
                        ipc <= wr_reg_vl[(AW-1):0];
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
                        ipc <= alu_pc;
                        ipc <= alu_pc;
                else if ((i_halt)&&(i_dbg_we)
 
                                &&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
 
                        ipc <= i_dbg_data[(AW-1):0];
 
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        pf_pc <= RESET_ADDRESS;
                        pf_pc <= RESET_ADDRESS;
                else if (w_switch_to_interrupt)
                else if (w_switch_to_interrupt)
                        pf_pc <= ipc;
                        pf_pc <= ipc;
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        pf_pc <= upc;
                        pf_pc <= upc;
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                        pf_pc <= wr_reg_vl[(AW-1):0];
                        pf_pc <= wr_reg_vl[(AW-1):0];
                else if ((i_halt)&&(i_dbg_we)
 
                                &&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
 
                        pf_pc <= i_dbg_data[(AW-1):0];
 
                else if (dcd_ce)
                else if (dcd_ce)
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
 
 
        initial new_pc = 1'b1;
        initial new_pc = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_pf_cache))
                if ((i_rst)||(i_clear_pf_cache))
                        new_pc <= 1'b1;
                        new_pc <= 1'b1;
                else if (w_switch_to_interrupt)
                else if (w_switch_to_interrupt)
                        new_pc <= 1'b1;
                        new_pc <= 1'b1;
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        new_pc <= 1'b1;
                        new_pc <= 1'b1;
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                        new_pc <= 1'b1;
                        new_pc <= 1'b1;
                else if ((i_halt)&&(i_dbg_we)
 
                                &&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
 
                        new_pc <= 1'b1;
 
                else
                else
                        new_pc <= 1'b0;
                        new_pc <= 1'b0;
 
 
        //
        //
        // The debug interface
        // The debug interface
        generate
        generate
        if (AW<32)
        if (AW<32)
        begin
        begin
                always @(posedge i_clk)
                always @(posedge i_clk)
                begin
                begin
                        o_dbg_reg <= regset[i_dbg_reg];
                        o_dbg_reg <= regset[i_dbg_reg];
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
                        begin
                        begin
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
                        end
                        end
                end
                end
        end else begin
        end else begin
                always @(posedge i_clk)
                always @(posedge i_clk)
                begin
                begin
                        o_dbg_reg <= regset[i_dbg_reg];
                        o_dbg_reg <= regset[i_dbg_reg];
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
                        begin
                        begin
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
                        end
                        end
                end
                end
        end endgenerate
        end endgenerate
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_dbg_stall <= (i_halt)&&(
                o_dbg_stall <= (i_halt)&&(
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
                        ||((~opvalid)&&(~i_rst))
                        ||((~opvalid)&&(~i_rst))
                        ||((~dcdvalid)&&(~i_rst)));
                        ||((~dcdvalid)&&(~i_rst)));
 
 
        //
        //
        //
        //
        // Produce accounting outputs: Account for any CPU stalls, so we can
        // Produce accounting outputs: Account for any CPU stalls, so we can
        // later evaluate how well we are doing.
        // later evaluate how well we are doing.
        //
        //
        //
        //
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
 
 
 
`ifdef  DEBUG_SCOPE
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_debug <= {
                o_debug <= {
                        pf_pc[7:0],
                        pf_pc[7:0],
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
                        op_ce, alu_ce, mem_ce,
                        op_ce, alu_ce, mem_ce,
                        opA[23:20], opA[3:0],
                        //
                        wr_reg_vl[7:0]
                        master_ce, opvalid_alu, opvalid_mem,
 
                        //
 
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
 
                        mem_we,
 
                        // ((opvalid_alu)&&(alu_stall))
 
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
 
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
 
                        // opA[23:20], opA[3:0],
 
                        gie, sleep,
 
                        wr_reg_vl[5:0]
                        };
                        };
 
`endif
 
 
endmodule
endmodule
 
 

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