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[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Diff between revs 65 and 69

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Line 30... Line 30...
//      found in the spec.pdf file.  (The documentation within this file
//      found in the spec.pdf file.  (The documentation within this file
//      had become out of date and out of sync with the spec.pdf, so look
//      had become out of date and out of sync with the spec.pdf, so look
//      to the spec.pdf for accurate and up to date information.)
//      to the spec.pdf for accurate and up to date information.)
//
//
//
//
 
//      In general, the pipelining is controlled by three pieces of logic
 
//      per stage: _ce, _stall, and _valid.  _valid means that the stage
 
//      holds a valid instruction.  _ce means that the instruction from the
 
//      previous stage is to move into this one, and _stall means that the
 
//      instruction from the previous stage may not move into this one.
 
//      The difference between these control signals allows individual stages
 
//      to propagate instructions independently.  In general, the logic works
 
//      as:
 
//
 
//
 
//      assign  (n)_ce = (n-1)_valid && (~(n)_stall)
 
//
 
//
 
//      always @(posedge i_clk)
 
//              if ((i_rst)||(clear_pipeline))
 
//                      (n)_valid = 0
 
//              else if (n)_ce
 
//                      (n)_valid = 1
 
//              else if (n+1)_ce
 
//                      (n)_valid = 0
 
//
 
//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )
 
//                      || (  (n)_valid && (n+1)_stall );
 
//
 
//      and ...
 
//
 
//      always @(posedge i_clk)
 
//              if (n)_ce
 
//                      (n)_variable = ... whatever logic for this stage
 
//
 
//      Note that a stage can stall even if no instruction is loaded into
 
//      it.
 
//
 
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
Line 67... Line 101...
//
//
//
//
//
//
`define CPU_CC_REG      4'he
`define CPU_CC_REG      4'he
`define CPU_PC_REG      4'hf
`define CPU_PC_REG      4'hf
`define CPU_BUSERR_BIT  10
`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error
`define CPU_TRAP_BIT    9
`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero
`define CPU_ILL_BIT     8
`define CPU_BUSERR_BIT  10      // Bus error flag, set on error
 
`define CPU_TRAP_BIT    9       // User TRAP has taken place
 
`define CPU_ILL_BIT     8       // Illegal instruction
`define CPU_BREAK_BIT   7
`define CPU_BREAK_BIT   7
`define CPU_STEP_BIT    6
`define CPU_STEP_BIT    6       // Will step one or two (VLIW) instructions
`define CPU_GIE_BIT     5
`define CPU_GIE_BIT     5
`define CPU_SLEEP_BIT   4
`define CPU_SLEEP_BIT   4
// Compile time defines
// Compile time defines
//
//
`include "cpudefs.v"
`include "cpudefs.v"
//
//
//
//
//
 
// `define      DEBUG_SCOPE
 
//
 
//
 
//
 
module  zipcpu(i_clk, i_rst, i_interrupt,
module  zipcpu(i_clk, i_rst, i_interrupt,
                // Debug interface
                // Debug interface
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
                        o_break,
                        o_break,
Line 102... Line 133...
`ifdef  DEBUG_SCOPE
`ifdef  DEBUG_SCOPE
                , o_debug
                , o_debug
`endif
`endif
                );
                );
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
                        LGICACHE=6, AW=ADDRESS_WIDTH;
                        LGICACHE=6;
`ifdef  OPT_MULTIPLY
`ifdef  OPT_MULTIPLY
        parameter       IMPLEMENT_MPY = 1;
        parameter       IMPLEMENT_MPY = 1;
`else
`else
        parameter       IMPLEMENT_MPY = 0;
        parameter       IMPLEMENT_MPY = 0;
`endif
`endif
 
        parameter       IMPLEMENT_DIVIDE = 1, IMPLEMENT_FPU = 0,
 
                        IMPLEMENT_LOCK=1;
 
`ifdef  OPT_EARLY_BRANCHING
 
        parameter       EARLY_BRANCHING = 1;
 
`else
 
        parameter       EARLY_BRANCHING = 0;
 
`endif
 
        parameter       AW=ADDRESS_WIDTH;
        input                   i_clk, i_rst, i_interrupt;
        input                   i_clk, i_rst, i_interrupt;
        // Debug interface -- inputs
        // Debug interface -- inputs
        input                   i_halt, i_clear_pf_cache;
        input                   i_halt, i_clear_pf_cache;
        input           [4:0]    i_dbg_reg;
        input           [4:0]    i_dbg_reg;
        input                   i_dbg_we;
        input                   i_dbg_we;
Line 153... Line 192...
        reg     [31:0]   regset [0:31];
        reg     [31:0]   regset [0:31];
 
 
        // Condition codes
        // Condition codes
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
        reg     [3:0]    flags, iflags;
        reg     [3:0]    flags, iflags;
        wire    [10:0]   w_uflags, w_iflags;
        wire    [12:0]   w_uflags, w_iflags;
        reg             trap, break_en, step, gie, sleep;
        reg             trap, break_en, step, gie, sleep;
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        reg             ill_err_u, ill_err_i;
        reg             ill_err_u, ill_err_i;
`else
`else
        wire            ill_err_u, ill_err_i;
        wire            ill_err_u, ill_err_i;
`endif
`endif
        reg             ibus_err_flag, ubus_err_flag;
        reg             ibus_err_flag, ubus_err_flag;
 
        wire            idiv_err_flag, udiv_err_flag;
 
        wire            ifpu_err_flag, ufpu_err_flag;
 
        wire            ihalt_phase, uhalt_phase;
 
 
        // The master chip enable
        // The master chip enable
        wire            master_ce;
        wire            master_ce;
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #1 :: Prefetch
        //      PIPELINE STAGE #1 :: Prefetch
        //              Variable declarations
        //              Variable declarations
        //
        //
        reg     [(AW-1):0]       pf_pc;
        reg     [(AW-1):0]       pf_pc;
        reg             new_pc, op_break;
        reg     new_pc;
        wire    clear_pipeline;
        wire    clear_pipeline;
        assign  clear_pipeline = new_pc || i_clear_pf_cache; //  || op_break;
        assign  clear_pipeline = new_pc || i_clear_pf_cache;
 
 
        wire            dcd_stalled;
        wire            dcd_stalled;
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
        wire    [(AW-1):0]       pf_addr;
        wire    [(AW-1):0]       pf_addr;
        wire    [31:0]           pf_data;
        wire    [31:0]           pf_data;
Line 190... Line 232...
        //      PIPELINE STAGE #2 :: Instruction Decode
        //      PIPELINE STAGE #2 :: Instruction Decode
        //              Variable declarations
        //              Variable declarations
        //
        //
        //
        //
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
        wire            op_stall, dcd_ce;
        reg             opvalid_div, opvalid_fpu;
        reg     [3:0]    dcdOp;
        wire            op_stall, dcd_ce, dcd_phase;
        reg     [4:0]    dcdA, dcdB;
        wire    [3:0]    dcdOp;
        reg             dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
        wire    [4:0]    dcdA, dcdB, dcdR;
        reg     [3:0]    dcdF;
        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
        wire    [3:0]    dcdF;
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
        wire            dcdR_wr, dcdA_rd, dcdB_rd,
        reg     [(AW-1):0]       dcd_pc;
                                dcdALU, dcdM, dcdDV, dcdFP,
        reg     [23:0]   r_dcdI;
                                dcdF_wr, dcd_gie, dcd_break, dcd_lock;
`ifdef  OPT_SINGLE_CYCLE
        reg             r_dcdvalid;
        reg             dcd_zI; // true if dcdI == 0
        wire            dcdvalid;
`endif
        wire    [(AW-1):0]       dcd_pc;
 
        wire    [31:0]   dcdI;
 
        wire            dcd_zI; // true if dcdI == 0
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
 
 
`ifdef  OPT_PRECLEAR_BUS
        wire    dcd_illegal;
        reg     dcd_clear_bus;
        wire                    dcd_early_branch;
`endif
 
`ifdef  OPT_ILLEGAL_INSTRUCTION
 
        reg     dcd_illegal;
 
`endif
 
`ifdef  OPT_EARLY_BRANCHING
 
        reg                     dcd_early_branch_stb, dcd_early_branch;
 
        reg     [(AW-1):0]       dcd_branch_pc;
 
`else
 
        wire                    dcd_early_branch_stb, dcd_early_branch;
 
        wire    [(AW-1):0]       dcd_branch_pc;
        wire    [(AW-1):0]       dcd_branch_pc;
`endif
 
 
 
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #3 :: Read Operands
        //      PIPELINE STAGE #3 :: Read Operands
Line 235... Line 269...
        reg     [31:0]   r_opA, r_opB;
        reg     [31:0]   r_opA, r_opB;
        reg     [(AW-1):0]       op_pc;
        reg     [(AW-1):0]       op_pc;
        wire    [31:0]   w_opA, w_opB;
        wire    [31:0]   w_opA, w_opB;
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        reg             opR_wr, opR_cc, opF_wr, op_gie;
        reg             opR_wr, opR_cc, opF_wr, op_gie;
        wire    [10:0]   opFl;
        wire    [12:0]   opFl;
        reg     [5:0]    r_opF;
        reg     [5:0]    r_opF;
        wire    [7:0]    opF;
        wire    [7:0]    opF;
        reg     [2:0]    opF_cp;
        reg     [2:0]    opF_cp;
        wire            op_ce;
        wire            op_ce, op_phase;
        // Some pipeline control wires
        // Some pipeline control wires
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_PIPELINED
        reg     opA_alu, opA_mem;
        reg     opA_alu, opA_mem;
        reg     opB_alu, opB_mem;
        reg     opB_alu, opB_mem;
`endif
`endif
`ifdef  OPT_PRECLEAR_BUS
 
        reg     op_clear_bus;
 
`endif
 
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        reg     op_illegal;
        reg     op_illegal;
`endif
`endif
 
        reg     op_break;
 
        wire    op_lock;
 
 
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #4 :: ALU / Memory
        //      PIPELINE STAGE #4 :: ALU / Memory
        //              Variable declarations
        //              Variable declarations
        //
        //
        //
        //
        reg     [(AW-1):0]       alu_pc;
        reg     [(AW-1):0]       alu_pc;
        reg             alu_pc_valid;;
        reg             alu_pc_valid;
 
        wire            alu_phase;
        wire            alu_ce, alu_stall;
        wire            alu_ce, alu_stall;
        wire    [31:0]   alu_result;
        wire    [31:0]   alu_result;
        wire    [3:0]    alu_flags;
        wire    [3:0]    alu_flags;
        wire            alu_valid;
        wire            alu_valid;
        wire            set_cond;
        wire            set_cond;
Line 285... Line 319...
        wire                    mem_busy, mem_rdbusy;
        wire                    mem_busy, mem_rdbusy;
        wire    [(AW-1):0]       mem_addr;
        wire    [(AW-1):0]       mem_addr;
        wire    [31:0]           mem_data, mem_result;
        wire    [31:0]           mem_data, mem_result;
        reg     [4:0]            mem_last_reg; // Last register result to go in
        reg     [4:0]            mem_last_reg; // Last register result to go in
 
 
 
        wire    div_ce, div_error, div_busy, div_valid;
 
        wire    [31:0]   div_result;
 
        wire    [3:0]    div_flags;
 
 
 
        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
 
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
 
                                &&(set_cond);
 
 
 
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
 
        wire    [31:0]   fpu_result;
 
        wire    [3:0]    fpu_flags;
 
 
 
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
 
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
 
                                &&(set_cond);
 
 
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #5 :: Write-back
        //      PIPELINE STAGE #5 :: Write-back
Line 316... Line 365...
        //
        //
 
 
        //
        //
        //      PIPELINE STAGE #2 :: Instruction Decode
        //      PIPELINE STAGE #2 :: Instruction Decode
        //              Calculate stall conditions
        //              Calculate stall conditions
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
`ifdef  OPT_PIPELINED
        assign          dcd_stalled = (dcdvalid)&&(
        assign          dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
                                        (op_stall)
`else
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
        assign          dcd_ce = 1'b1;
                                        ||((opvalid_mem)&&(op_wr_pc))
`endif
                                        ||((opvalid_mem)&&(opR_cc)));
`ifdef  OPT_PIPELINED
 
        assign          dcd_stalled = (dcdvalid)&&(op_stall);
 
`else
 
        // If not pipelined, there will be no opvalid_ anything, and the
 
        // op_stall will be false, dcdX_stall will be false, thus we can simply
 
        // do a ...
 
        assign          dcd_stalled = 1'b0;
 
`endif
        //
        //
        //      PIPELINE STAGE #3 :: Read Operands
        //      PIPELINE STAGE #3 :: Read Operands
        //              Calculate stall conditions
        //              Calculate stall conditions
        assign  op_stall = ((opvalid)&&(~master_ce))||(
        wire    op_lock_stall;
 
`ifdef  OPT_PIPELINED
 
        assign  op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
 
                        // Stall if we're stopped, and not allowed to execute
 
                        // an instruction
 
                        // (~master_ce)         // Already captured in alu_stall
 
                        //
                        // Stall if going into the ALU and the ALU is stalled
                        // Stall if going into the ALU and the ALU is stalled
                        //      i.e. if the memory is busy, or we are single
                        //      i.e. if the memory is busy, or we are single
                        //      stepping
                        //      stepping.  This also includes our stalls for
                        ((opvalid_alu)&&(alu_stall))
                        //      op_break and op_lock, so we don't need to
 
                        //      include those as well here.
 
                        ((opvalid)&&(alu_stall))
 
                        // Stall if the divide is busy, since we can't have
 
                        // two parallel stages writing back at the same time
 
                        ||(div_busy)
 
                        // Same for the floating point unit
 
                        ||(fpu_busy)
                        //
                        //
                        // ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
                        // ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
                        // Stall if we are going into memory with an operation
                        // Stall if we are going into memory with an operation
                        //      that cannot be pipelined, and the memory is
                        //      that cannot be pipelined, and the memory is
                        //      already busy
                        //      already busy
`ifdef  OPT_PIPELINED_BUS_ACCESS
                        ||((opvalid_mem)&&(mem_stalled))
                        ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
                        )
                        //
                        ||(dcdvalid)&&(
                        // Stall if we are going into memory with a pipeable
                                // Stall if we've got a read going with an
                        //      operation, but the memory unit declares it is
                                // unknown output (known w/in the memory module)
                        //      not going to accept any more pipeline operations
                                (mem_rdbusy)
                        ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))
                                // Or if we need to wait for an operand A
 
                                // to be ready to read
 
                                ||(dcdA_stall)
 
                                // Likewise for B, also includes logic
 
                                // regarding immediate offset (register must
 
                                // be in register file if we need to add to
 
                                // an immediate)
 
                                ||(dcdB_stall)
 
                                // Or if we need to wait on flags to work on the
 
                                // CC register
 
                                ||(dcdF_stall)
 
                        );
 
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall))&&(~clear_pipeline);
`else
`else
                        ||((opvalid_mem)&&(mem_busy))
        assign  op_stall = (opvalid)&&(~master_ce);
 
        assign  op_ce = (dcdvalid);
`endif
`endif
                        );
 
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
 
 
 
        //
        //
        //      PIPELINE STAGE #4 :: ALU / Memory
        //      PIPELINE STAGE #4 :: ALU / Memory
        //              Calculate stall conditions
        //              Calculate stall conditions
        //
        //
Line 361... Line 441...
        // 3. Stall if someone on the other end is writing the CC register,
        // 3. Stall if someone on the other end is writing the CC register,
        //      since we don't know if it'll put us to sleep or not.
        //      since we don't know if it'll put us to sleep or not.
        // 4. Last case: Stall if we would otherwise move a break instruction
        // 4. Last case: Stall if we would otherwise move a break instruction
        //      through the ALU.  Break instructions are not allowed through
        //      through the ALU.  Break instructions are not allowed through
        //      the ALU.
        //      the ALU.
 
`ifdef  OPT_PIPELINED
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
                        // Old case #3--this isn't an ALU stall though ...
                        // Old case #3--this isn't an ALU stall though ...
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                                &&(wr_write_cc)) // Case 3
                                &&(wr_write_cc)) // Case 3
                        ||((opvalid_alu)&&(op_break)); // Case 3
                        ||((opvalid)&&(op_lock)&&(op_lock_stall))
        assign  alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
                        ||((opvalid)&&(op_break))
 
                        ||(div_busy)||(fpu_busy);
 
        assign  alu_ce = (master_ce)&&(opvalid_alu)
 
                                &&(~alu_stall)
 
                                &&(~clear_pipeline);
 
`else
 
        assign  alu_stall = ((~master_ce)&&(opvalid_alu))
 
                                ||((opvalid_alu)&&(op_break));
 
        assign  alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall);
 
`endif
        //
        //
 
 
        //
        //
        // Note: if you change the conditions for mem_ce, you must also change
        // Note: if you change the conditions for mem_ce, you must also change
        // alu_pc_valid.
        // alu_pc_valid.
        //
        //
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
`ifdef  OPT_PIPELINED
 
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
 
                        &&(~clear_pipeline)&&(set_cond);
 
`else
 
        // If we aren't pipelined, then no one will be changing what's in the
 
        // pipeline (i.e. clear_pipeline), while our only instruction goes
 
        // through the ... pipeline.
 
        assign  mem_ce = (master_ce)&&(opvalid_mem)
                        &&(set_cond)&&(~mem_stalled);
                        &&(set_cond)&&(~mem_stalled);
 
`endif
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
        assign  mem_stalled = (~master_ce)||((opvalid_mem)&&(
        assign  mem_stalled = (~master_ce)||((opvalid_mem)&&(
                                (mem_pipe_stalled)
                                (mem_pipe_stalled)
                                ||((~op_pipe)&&(mem_busy))
                                ||((~op_pipe)&&(mem_busy))
 
                                ||(div_busy)
 
                                ||(fpu_busy)
                                // Stall waiting for flags to be valid
                                // Stall waiting for flags to be valid
                                // Or waiting for a write to the PC register
                                // Or waiting for a write to the PC register
                                // Or CC register, since that can change the
                                // Or CC register, since that can change the
                                //  PC as well
                                //  PC as well
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                                        &&((wr_write_pc)||(wr_write_cc)))));
                                        &&((wr_write_pc)||(wr_write_cc)))));
`else
`else
 
`ifdef  OPT_PIPELINED
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
                                (~master_ce)
                                (~master_ce)
                                // Stall waiting for flags to be valid
                                // Stall waiting for flags to be valid
                                // Or waiting for a write to the PC register
                                // Or waiting for a write to the PC register
                                // Or CC register, since that can change the
                                // Or CC register, since that can change the
                                //  PC as well
                                //  PC as well
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
 
`else
 
        assign  mem_stalled = (opvalid_mem)&&(~master_ce);
 
`endif
`endif
`endif
 
 
 
 
        //
        //
        //
        //
Line 404... Line 508...
        //
        //
        //
        //
`ifdef  OPT_SINGLE_FETCH
`ifdef  OPT_SINGLE_FETCH
        wire            pf_ce;
        wire            pf_ce;
 
 
        assign          pf_ce = (~dcd_stalled);
        assign          pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
        prefetch        #(ADDRESS_WIDTH)
        prefetch        #(ADDRESS_WIDTH)
                        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
                        pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie,
                                instruction, instruction_pc, instruction_gie,
                                instruction, instruction_pc, instruction_gie,
                                        pf_valid, pf_illegal,
                                        pf_valid, pf_illegal,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_ack, pf_stall, pf_err, i_wb_data);
                                pf_ack, pf_stall, pf_err, i_wb_data);
 
 
 
        initial r_dcdvalid = 1'b0;
 
        always @(posedge i_clk)
 
                if (i_rst)
 
                        r_dcdvalid <= 1'b0;
 
                else if (dcd_ce)
 
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
 
                else if ((op_ce)||(clear_pipeline))
 
                        r_dcdvalid <= 1'b0;
 
        assign  dcdvalid = r_dcdvalid;
 
 
`else // Pipe fetch
`else // Pipe fetch
 
 
 
`ifdef  OPT_TRADITIONAL_PFCACHE
 
        pfcache #(LGICACHE, ADDRESS_WIDTH)
 
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
 
                                        i_clear_pf_cache,
 
                                // dcd_pc,
 
                                ~dcd_stalled,
 
                                ((dcd_early_branch)&&(dcdvalid)&&(~new_pc))
 
                                        ? dcd_branch_pc:pf_pc,
 
                                instruction, instruction_pc, pf_valid,
 
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
 
                                        pf_ack, pf_stall, pf_err, i_wb_data,
 
                                pf_illegal);
 
`else
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
                        pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
                        pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
                                        i_clear_pf_cache, ~dcd_stalled,
                                        i_clear_pf_cache, ~dcd_stalled,
                                        (new_pc)?pf_pc:dcd_branch_pc,
                                        (new_pc)?pf_pc:dcd_branch_pc,
                                        instruction, instruction_pc, pf_valid,
                                        instruction, instruction_pc, pf_valid,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
`ifdef  OPT_PRECLEAR_BUS
//`ifdef        OPT_PRECLEAR_BUS
                                ((dcd_clear_bus)&&(dcdvalid))
                                //((dcd_clear_bus)&&(dcdvalid))
                                ||((op_clear_bus)&&(opvalid))
                                //||((op_clear_bus)&&(opvalid))
                                ||
                                //||
`endif
//`endif
                                (mem_cyc_lcl)||(mem_cyc_gbl),
                                (mem_cyc_lcl)||(mem_cyc_gbl),
                                pf_illegal);
                                pf_illegal);
        assign  instruction_gie = gie;
 
`endif
`endif
 
        assign  instruction_gie = gie;
 
 
        initial dcdvalid = 1'b0;
        initial r_dcdvalid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if ((i_rst)||(clear_pipeline))
                        dcdvalid <= 1'b0;
                        r_dcdvalid <= 1'b0;
                else if (dcd_ce)
                else if (dcd_ce)
                        dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
                else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
                else if (op_ce)
                        dcdvalid <= 1'b0;
                        r_dcdvalid <= 1'b0;
 
        assign  dcdvalid = r_dcdvalid;
`ifdef  OPT_EARLY_BRANCHING
`endif
        always @(posedge i_clk)
 
                if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(master_ce))
`ifdef  OPT_NEW_INSTRUCTION_SET
                begin
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
                        dcd_early_branch <= 1'b0;
                        IMPLEMENT_FPU)
                        // First case, a move to PC instruction
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
                        if ((instruction[31:28] == 4'h2)
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
                                // Offsets of the PC register *only*
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
                                &&(instruction[19:16] == `CPU_PC_REG)
                        dcd_illegal, dcd_pc, dcd_gie,
                                &&((instruction_gie)
                        { dcdR_cc, dcdR_pc, dcdR },
                                        ||((~instruction[20])&&(~instruction[15])))
                        { dcdA_cc, dcdA_pc, dcdA },
                                &&(instruction[23:21]==3'h0)) // Unconditional
                        { dcdB_cc, dcdB_pc, dcdB },
                        begin
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
                                dcd_early_branch_stb <= 1'b1;
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
                                dcd_early_branch <= 1'b1;
                        dcdR_wr,dcdA_rd, dcdB_rd,
                                // r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
                        dcd_early_branch,
 
                        dcd_branch_pc);
                        end else // Next case, an Add Imm -> PC instruction
 
                        if ((instruction[31:28] == 4'ha) // Add
 
                                &&(~instruction[20]) // Immediate
 
                                &&(instruction[23:21]==3'h0)) // Always
 
                        begin
 
                                dcd_early_branch_stb <= 1'b1;
 
                                dcd_early_branch <= 1'b1;
 
                                // r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
 
                        end else // Next case: load Immediate to PC
 
                        if (instruction[31:28] == 4'h3)
 
                        begin
 
                                dcd_early_branch_stb <= 1'b1;
 
                                dcd_early_branch <= 1'b1;
 
                                // r_dcdI <= { instruction[23:0] };
 
                        end
 
                end else
 
                begin
 
                        if (dcd_ce) dcd_early_branch <= 1'b0;
 
                        dcd_early_branch_stb <= 1'b0;
 
                end
 
        generate
 
        if (AW == 24)
 
        begin
 
                always @(posedge i_clk)
 
                if (dcd_ce)
 
                begin
 
                        if (instruction[31]) // Add
 
                        begin
 
                                dcd_branch_pc <= instruction_pc
 
                                                + { {(AW-20){instruction[19]}}, instruction[19:0] }
 
                                                + {{(AW-1){1'b0}},1'b1};
 
                        end else if (~instruction[28]) // 4'h2 = MOV
 
                                dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
 
                        else // if (instruction[28]) // 4'h3 = LDI
 
                                dcd_branch_pc <= instruction_pc+{ instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
 
                end
 
        end else begin
 
                always @(posedge i_clk)
 
                if (dcd_ce)
 
                begin
 
                        if (instruction[31]) // Add
 
                        begin
 
                                dcd_branch_pc <= instruction_pc
 
                                                        + { {(AW-20){instruction[19]}}, instruction[19:0] }
 
                                                        + {{(AW-1){1'b0}},1'b1};
 
                        end else if (~instruction[28]) // 4'h2 = MOV
 
                        begin
 
                                        dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
 
                        end else // if (instruction[28]) // 4'h3 = LDI
 
                        begin
 
                                dcd_branch_pc <= instruction_pc+{ {(AW-24){instruction[23]}}, instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
 
                        end
 
                end
 
        end endgenerate
 
`else   //      OPT_EARLY_BRANCHING
 
        assign  dcd_early_branch_stb = 1'b0;
 
        assign  dcd_early_branch     = 1'b0;
 
        assign  dcd_branch_pc        = {(AW){1'b0}};
 
`endif  //      OPT_EARLY_BRANCHING
 
 
 
        always @(posedge i_clk)
 
                if (dcd_ce)
 
                begin
 
                        dcd_pc <= instruction_pc
 
                                +{{(AW-1){1'b0}},1'b1}; // i.e. dcd_pc+1
 
 
 
                        // Record what operation we are doing
 
                        dcdOp <= instruction[31:28];
 
 
 
                        // Default values
 
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
 
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
 
                        dcdA_cc <=  (instruction[27:24] == `CPU_CC_REG);
 
                        dcdB_cc <=  (instruction[19:16] == `CPU_CC_REG);
 
                        dcdA_pc <=  (instruction[27:24] == `CPU_PC_REG);
 
                        dcdB_pc <=  (instruction[19:16] == `CPU_PC_REG);
 
                        dcdM    <= 1'b0;
 
`ifdef  OPT_CONDITIONAL_FLAGS
 
                        // Don't change the flags on conditional instructions,
 
                        // UNLESS: the conditional instruction was a CMP
 
                        // or TST instruction.
 
                        dcdF_wr <= ((instruction[23:21]==3'h0)
 
                                        ||(instruction[31:29] == 3'h0));
 
`else
`else
                        dcdF_wr <= 1'b1;
        idecode_deprecated
`endif
                #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
`ifdef  OPT_PRECLEAR_BUS
                        IMPLEMENT_FPU)
                        dcd_clear_bus <= 1'b0;
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
`endif
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
`ifdef  OPT_ILLEGAL_INSTRUCTION
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
                        dcd_illegal <= pf_illegal;
                        dcd_illegal, dcd_pc, dcd_gie,
 
                        { dcdR_cc, dcdR_pc, dcdR },
 
                        { dcdA_cc, dcdA_pc, dcdA },
 
                        { dcdB_cc, dcdB_pc, dcdB },
 
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
 
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
 
                        dcdR_wr,dcdA_rd, dcdB_rd,
 
                        dcd_early_branch,
 
                        dcd_branch_pc);
`endif
`endif
 
 
                        // Set the condition under which we do this operation
 
                        // The top four bits are a mask, the bottom four the
 
                        // value the flags must equal once anded with the mask
 
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
 
                        casez(instruction[31:28])
 
                        4'h2: begin // Move instruction
 
                                if (~instruction_gie)
 
                                begin
 
                                        dcdA[4] <= instruction[20];
 
                                        dcdB[4] <= instruction[15];
 
                                end
 
                                dcdA_wr <= 1'b1;
 
                                dcdA_rd <= 1'b0;
 
                                dcdB_rd <= 1'b1;
 
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
 
`ifdef  OPT_SINGLE_CYCLE
 
                                dcd_zI <= (instruction[14:0] == 0);
 
`endif
 
                                dcdF_wr <= 1'b0; // Don't write flags
 
                                end
 
                        4'h3: begin // Load immediate
 
                                dcdA_wr <= 1'b1;
 
                                dcdA_rd <= 1'b0;
 
                                dcdB_rd <= 1'b0;
 
                                r_dcdI <= { instruction[23:0] };
 
`ifdef  OPT_SINGLE_CYCLE
 
                                dcd_zI <= (instruction[23:0] == 0);
 
`endif
 
                                dcdF_wr <= 1'b0; // Don't write flags
 
                                dcdF    <= 4'h8; // This is unconditional
 
                                dcdOp <= 4'h2;
 
                                end
 
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
 
`ifdef  OPT_CONDITIONAL_FLAGS
 
                                // Don't write flags except for multiplies
 
                                //   and then only if they are unconditional
 
                                dcdF_wr <= ((instruction[27:25] != 3'h7)
 
                                        &&(instruction[23:21]==3'h0));
 
`else
 
                                // Don't write flags except for multiplies
 
                                dcdF_wr <= (instruction[27:25] != 3'h7);
 
`endif
 
                                r_dcdI <= { 8'h00, instruction[15:0] };
 
`ifdef  OPT_SINGLE_CYCLE
 
                                dcd_zI <= (instruction[15:0] == 0);
 
`endif
 
                                if (instruction[27:24] == 4'he)
 
                                begin
 
                                        // NOOP instruction
 
                                        dcdA_wr <= 1'b0;
 
                                        dcdA_rd <= 1'b0;
 
                                        dcdB_rd <= 1'b0;
 
                                        dcdOp <= 4'h2;
 
                                        // Might also be a break.  Big
 
                                        // instruction set hole here.
 
`ifdef  OPT_ILLEGAL_INSTRUCTION
 
                                        dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
 
`endif
 
                                end else if (instruction[27:24] == 4'hf)
 
                                begin // Load partial immediate(s)
 
                                        dcdA_wr <= 1'b1;
 
                                        dcdA_rd <= 1'b1;
 
                                        dcdB_rd <= 1'b0;
 
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
 
                                        dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
 
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
 
                                        dcdOp <= { 3'h3, instruction[20] };
 
                                end else begin
 
                                        // Actual multiply instruction
 
                                        r_dcdI <= { 8'h00, instruction[15:0] };
 
`ifdef  OPT_SINGLE_CYCLE
 
                                        dcd_zI <= (instruction[15:0] == 0);
 
`endif
 
                                        dcdA_rd <= 1'b1;
 
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
 
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
 
                                end end
 
                        4'b011?: begin // LOD/STO or Load/Store
 
                                dcdF_wr <= 1'b0; // Don't write flags
 
                                dcdA_wr <= (~instruction[28]); // Write on loads
 
                                dcdA_rd <= (instruction[28]); // Read on stores
 
                                dcdB_rd <= instruction[20];
 
                                if (instruction[20])
 
                                begin
 
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
 
`ifdef  OPT_SINGLE_CYCLE
 
                                        dcd_zI <= (instruction[15:0] == 0);
 
`endif
 
                                end else begin
 
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
 
`ifdef  OPT_SINGLE_CYCLE
 
                                        dcd_zI <= (instruction[19:0] == 0);
 
`endif
 
                                end
 
                                dcdM <= 1'b1; // Memory operation
 
`ifdef  OPT_PRECLEAR_BUS
 
                                dcd_clear_bus <= (instruction[23:21]==3'h0);
 
`endif
 
                                end
 
                        default: begin
 
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
 
                                dcdA_rd <= 1'b1;
 
                                dcdB_rd <= instruction[20];
 
                                if (instruction[20])
 
                                begin
 
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
 
`ifdef  OPT_SINGLE_CYCLE
 
                                        dcd_zI <= (instruction[15:0] == 0);
 
`endif
 
                                end else begin
 
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
 
`ifdef  OPT_SINGLE_CYCLE
 
                                        dcd_zI <= (instruction[19:0] == 0);
 
`endif
 
                                end end
 
                        endcase
 
 
 
 
 
                        dcd_gie <= instruction_gie;
 
                end
 
        always @(posedge i_clk)
 
                if (dcd_ce)
 
                        dcd_break <= (instruction[31:0] == 32'h4e000001);
 
                else if ((clear_pipeline)||(~dcdvalid)) // SHOULDNT THIS BE ||op_ce?
 
                        dcd_break <= 1'b0;
 
 
 
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
        reg     [23:0]   r_opI;
        reg     [23:0]   r_opI;
        reg     [4:0]    op_B;
        reg     [4:0]    op_B;
        reg             op_pipe;
        reg             op_pipe;
 
 
Line 693... Line 621...
                        op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
                        op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
                                &&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
                                &&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
                                &&(dcdB == op_B) // Same address register
                                &&(dcdB == op_B) // Same address register
                                &&((dcdF[2:0] == opF_cp) // Same condition
                                &&((dcdF[2:0] == opF_cp) // Same condition
                                        ||(opF_cp == 3'h0)) // or no prev condition
                                        ||(opF_cp == 3'h0)) // or no prev condition
                                &&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
                                &&((dcdI[23:0] == r_opI)||(dcdI[23:0]==r_opI+24'h1));
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                        r_opI <= r_dcdI;
                        r_opI <= dcdI[23:0];
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                        op_B <= dcdB;
                        op_B <= dcdB;
`endif
`endif
 
 
Line 725... Line 653...
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
                                r_opA <= wr_reg_vl;
                                r_opA <= wr_reg_vl;
                        else if (dcdA_pc)
                        else if (dcdA_pc)
                                r_opA <= w_pcA_v;
                                r_opA <= w_pcA_v;
                        else if (dcdA_cc)
                        else if (dcdA_cc)
                                r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
                                r_opA <= { w_opA[31:13], (dcdA[4])?w_uflags:w_iflags };
                        else
                        else
                                r_opA <= w_opA;
                                r_opA <= w_opA;
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_PIPELINED
                end else if (opvalid)
                end else if (opvalid)
                begin // We were going to pick these up when they became valid,
                begin // We were going to pick these up when they became valid,
                        // but for some reason we're stuck here as they became
                        // but for some reason we're stuck here as they became
                        // valid.  Pick them up now anyway
                        // valid.  Pick them up now anyway
                        if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
                        if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
                                r_opA <= wr_reg_vl;
                                r_opA <= wr_reg_vl;
`endif
`endif
                end
                end
 
 
        wire    [31:0]   dcdI, w_opBnI, w_pcB_v;
        wire    [31:0]   w_opBnI, w_pcB_v;
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
 
        generate
        generate
        if (AW < 32)
        if (AW < 32)
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
        else
        else
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
        endgenerate
        endgenerate
 
 
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
                : ((dcdB_pc) ? w_pcB_v
                : ((dcdB_pc) ? w_pcB_v
                : ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
                : ((dcdB_cc) ? { w_opB[31:13], (dcdB[4])?w_uflags:w_iflags}
                : w_opB)));
                : w_opB)));
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                        r_opB <= w_opBnI + dcdI;
                        r_opB <= w_opBnI + dcdI;
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_PIPELINED
                else if ((opvalid)&&(
                else if ((opvalid)&&(
                                ((opB_alu)&&(alu_wr))
                                ((opB_alu)&&(alu_wr))
                                ||((opB_mem)&&(mem_valid))))
                                ||((opB_mem)&&(mem_valid))))
                        r_opB <= wr_reg_vl;
                        r_opB <= wr_reg_vl;
`endif
`endif
Line 777... Line 704...
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
                        case(dcdF[2:0])
                        case(dcdF[2:0])
                        3'h0:   r_opF <= 6'h00; // Always
                        3'h0:   r_opF <= 6'h00; // Always
 
`ifdef  OPT_NEW_INSTRUCTION_SET
 
                        // These were remapped as part of the new instruction
 
                        // set in order to make certain that the low order
 
                        // two bits contained the most commonly used 
 
                        // conditions: Always, LT, Z, and NZ.
 
                        3'h1:   r_opF <= 6'h24; // LT
 
                        3'h2:   r_opF <= 6'h11; // Z
 
                        3'h3:   r_opF <= 6'h10; // NE
 
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
 
                        3'h5:   r_opF <= 6'h20; // GE (!N)
 
`else
                        3'h1:   r_opF <= 6'h11; // Z
                        3'h1:   r_opF <= 6'h11; // Z
                        3'h2:   r_opF <= 6'h10; // NE
                        3'h2:   r_opF <= 6'h10; // NE
                        3'h3:   r_opF <= 6'h20; // GE (!N)
                        3'h3:   r_opF <= 6'h20; // GE (!N)
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
                        3'h5:   r_opF <= 6'h24; // LT
                        3'h5:   r_opF <= 6'h24; // LT
 
`endif
                        3'h6:   r_opF <= 6'h02; // C
                        3'h6:   r_opF <= 6'h02; // C
                        3'h7:   r_opF <= 6'h08; // V
                        3'h7:   r_opF <= 6'h08; // V
                        endcase
                        endcase
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opF_cp[2:0] <= dcdF[2:0];
                        opF_cp[2:0] <= dcdF[2:0];
 
 
 
        wire    w_opvalid;
 
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid);
        initial opvalid     = 1'b0;
        initial opvalid     = 1'b0;
        initial opvalid_alu = 1'b0;
        initial opvalid_alu = 1'b0;
        initial opvalid_mem = 1'b0;
        initial opvalid_mem = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
Line 810... Line 751...
                        //   have in our queue.  This instruction must then
                        //   have in our queue.  This instruction must then
                        //   move forward, and get a stall cycle inserted.
                        //   move forward, and get a stall cycle inserted.
                        //   Hence, the test on dcd_stalled here.  If we must
                        //   Hence, the test on dcd_stalled here.  If we must
                        //   wait until our operands are valid, then we aren't
                        //   wait until our operands are valid, then we aren't
                        //   valid yet until then.
                        //   valid yet until then.
                        opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid<= w_opvalid;
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid);
                        opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
 
                        opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
 
                        opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
`else
`else
                        opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid_alu <= (dcdALU)&&(w_opvalid);
                        opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid_mem <= (dcdM)&&(w_opvalid);
 
                        opvalid_div <= (dcdDV)&&(w_opvalid);
 
                        opvalid_fpu <= (dcdFP)&&(w_opvalid);
`endif
`endif
                end else if ((~op_stall)||(clear_pipeline))
                end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
                begin
                begin
                        opvalid     <= 1'b0;
                        opvalid     <= 1'b0;
                        opvalid_alu <= 1'b0;
                        opvalid_alu <= 1'b0;
                        opvalid_mem <= 1'b0;
                        opvalid_mem <= 1'b0;
 
                        opvalid_div <= 1'b0;
 
                        opvalid_fpu <= 1'b0;
                end
                end
 
 
        // Here's part of our debug interface.  When we recognize a break
        // Here's part of our debug interface.  When we recognize a break
        // instruction, we set the op_break flag.  That'll prevent this
        // instruction, we set the op_break flag.  That'll prevent this
        // instruction from entering the ALU, and cause an interrupt before
        // instruction from entering the ALU, and cause an interrupt before
Line 841... Line 788...
                if (i_rst)      op_break <= 1'b0;
                if (i_rst)      op_break <= 1'b0;
                else if (op_ce) op_break <= (dcd_break);
                else if (op_ce) op_break <= (dcd_break);
                else if ((clear_pipeline)||(~opvalid))
                else if ((clear_pipeline)||(~opvalid))
                                op_break <= 1'b0;
                                op_break <= 1'b0;
 
 
 
`ifdef  OPT_PIPELINED
 
        generate
 
        if (IMPLEMENT_LOCK != 0)
 
        begin
 
                reg     r_op_lock, r_op_lock_stall;
 
 
 
                initial r_op_lock_stall = 1'b0;
 
                always @(posedge i_clk)
 
                        if (i_rst)
 
                                r_op_lock_stall <= 1'b0;
 
                        else
 
                                r_op_lock_stall <= (~opvalid)||(~op_lock)
 
                                                ||(~dcdvalid)||(~pf_valid);
 
 
 
                assign  op_lock_stall = r_op_lock_stall;
 
 
 
                initial r_op_lock = 1'b0;
 
                always @(posedge i_clk)
 
                        if (i_rst)
 
                                r_op_lock <= 1'b0;
 
                        else if ((op_ce)&&(dcd_lock))
 
                                r_op_lock <= 1'b1;
 
                        else if ((op_ce)||(clear_pipeline))
 
                                r_op_lock <= 1'b0;
 
                assign  op_lock = r_op_lock;
 
 
 
        end else begin
 
                assign  op_lock_stall = 1'b0;
 
                assign  op_lock = 1'b0;
 
        end endgenerate
 
 
 
`else
 
        assign op_lock_stall = 1'b0;
 
        assign op_lock       = 1'b0;
 
`endif
 
 
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        always @(posedge i_clk)
        always @(posedge i_clk)
                if(op_ce)
                if(op_ce)
                        op_illegal <= dcd_illegal;
`ifdef  OPT_PIPELINED
 
                        op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0));
 
`else
 
                        op_illegal <= (dcd_illegal)||(dcd_lock);
 
`endif
`endif
`endif
 
 
 
        generate
 
        if (EARLY_BRANCHING > 0)
 
        begin
 
                always @(posedge i_clk)
 
                        if (op_ce)
 
                        begin
 
                                opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))&&(~dcd_early_branch);
 
                                opR_wr <= (dcdR_wr)&&(~dcd_early_branch);
 
                                op_wr_pc <= ((dcdR_wr)&&(dcdR_pc)
 
                                                &&(dcdR[4] == dcd_gie))
 
                                                &&(~dcd_early_branch);
 
                        end
 
        end else begin
 
                always @(posedge i_clk)
 
                        if (op_ce)
 
                        begin
 
                                // Will we write the flags/CC Register with
 
                                // our result?
 
                                opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr));
 
                                // Will we be writing our results into a
 
                                // register?
 
                                opR_wr <= dcdR_wr;
 
                                op_wr_pc <= ((dcdR_wr)&&(dcdR_pc)
 
                                                &&(dcdR[4] == dcd_gie));
 
                        end
 
        end endgenerate
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                begin
                begin
                        opn    <= dcdOp;        // Which ALU operation?
                        opn    <= dcdOp;        // Which ALU operation?
                        // opM  <= dcdM;        // Is this a memory operation?
                        // opM  <= dcdM;        // Is this a memory operation?
`ifdef  OPT_EARLY_BRANCHING
 
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
 
                        opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
 
`else
 
                        // Will we write the flags/CC Register with our result?
 
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
 
                        // Will we be writing our results into a register?
 
                        opR_wr <= dcdA_wr;
 
`endif
 
                        // What register will these results be written into?
                        // What register will these results be written into?
                        opR    <= dcdA;
                        opR    <= dcdR;
                        opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
                        opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
                        // User level (1), vs supervisor (0)/interrupts disabled
                        // User level (1), vs supervisor (0)/interrupts disabled
                        op_gie <= dcd_gie;
                        op_gie <= dcd_gie;
 
 
 
 
                        //
                        //
`ifdef  OPT_EARLY_BRANCHING
 
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
 
`else
 
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
 
`endif
 
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
                        // op_pc  <= dcd_pc;
 
 
 
`ifdef  OPT_PRECLEAR_BUS
 
                        op_clear_bus <= dcd_clear_bus;
 
`endif
 
                end
                end
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
 
 
 
`ifdef  OPT_VLIW
 
        reg     r_op_phase;
 
        initial r_op_phase = 1'b0;
 
        always @(posedge i_clk)
 
                if ((i_rst)||(clear_pipeline))
 
                        r_op_phase <= 1'b0;
 
                else if (op_ce)
 
                        r_op_phase <= dcd_phase;
 
        assign  op_phase = r_op_phase;
 
`else
 
        assign  op_phase = 1'b0;
 
`endif
 
 
        // This is tricky.  First, the PC and Flags registers aren't kept in
        // This is tricky.  First, the PC and Flags registers aren't kept in
        // register set but in special registers of their own.  So step one
        // register set but in special registers of their own.  So step one
        // is to select the right register.  Step to is to replace that
        // is to select the right register.  Step to is to replace that
        // register with the results of an ALU or memory operation, if such
        // register with the results of an ALU or memory operation, if such
        // results are now available.  Otherwise, we'd need to insert a wait
        // results are now available.  Otherwise, we'd need to insert a wait
Line 894... Line 903...
        // The alternative approach would be to define some sort of
        // The alternative approach would be to define some sort of
        // op_stall wire, which would stall any upstream stage.
        // op_stall wire, which would stall any upstream stage.
        // We'll create a flag here to start our coordination.  Once we
        // We'll create a flag here to start our coordination.  Once we
        // define this flag to something other than just plain zero, then
        // define this flag to something other than just plain zero, then
        // the stalls will already be in place.
        // the stalls will already be in place.
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_PIPELINED
        initial opA_alu = 1'b0;
        initial opA_alu = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(opR_wr)&&(dcdA_rd);
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(opR_wr)&&(dcdA_rd);
                else if ((opvalid)&&(opA_alu)&&(alu_valid))
                else if ((opvalid)&&(opA_alu)&&(alu_valid))
Line 914... Line 923...
`endif
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (mem_ce)
                if (mem_ce)
                        mem_last_reg <= opR;
                        mem_last_reg <= opR;
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_PIPELINED
        assign  opA = ((opA_alu)&&(alu_wr)) ? alu_result
        assign  opA = ((opA_alu)&&(alu_wr)) ? alu_result
                        : ( ((opA_mem)&&(mem_valid))?mem_result
                        : ( ((opA_mem)&&(mem_valid))?mem_result
                        : r_opA );
                        : r_opA );
`else
`else
        assign  opA = r_opA;
        assign  opA = r_opA;
`endif
`endif
 
 
 
`ifdef  OPT_PIPELINED
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
`ifdef  OPT_SINGLE_CYCLE
 
                // Skip the requirement on writing back opA
 
                // Stall on memory, since we'll always need to stall for a 
 
                // memory access anyway
 
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
`else
`else
                                ((opvalid)&&(opR_wr)&&(opR == dcdA))
        // There are no pipeline hazards, if we aren't pipelined
                                ||((opvalid_alu)&&(opF_wr)&&(dcdA_cc))
        assign  dcdA_stall = 1'b0;
                                ||((mem_rdbusy)&&(mem_last_reg == dcdA))
 
                                );
 
`endif
`endif
 
 
`ifdef  OPT_SINGLE_CYCLE
`ifdef  OPT_PIPELINED
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
Line 954... Line 958...
                        : r_opB );
                        : r_opB );
`else
`else
        assign  opB = r_opB;
        assign  opB = r_opB;
`endif
`endif
 
 
 
`ifdef  OPT_PIPELINED
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
`ifdef  OPT_SINGLE_CYCLE
 
                                // Stall on memory ops writing to my register
                                // Stall on memory ops writing to my register
                                //      (i.e. loads), or on any write to my
                                //      (i.e. loads), or on any write to my
                                //      register if I have an immediate offset
                                //      register if I have an immediate offset
                                // Note the exception for writing to the PC:
                                // Note the exception for writing to the PC:
                                //      if I write to the PC, the whole next
                                //      if I write to the PC, the whole next
Line 976... Line 980...
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
                                // Stall on any ongoing memory operation that
                                // Stall on any ongoing memory operation that
                                // will write to opB
                                // will write to opB
                                ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
                                ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
`else
`else
                                ((opvalid)&&(opR_wr)&&(opR == dcdB))
        // No stalls without pipelining, 'cause how can you have a pipeline
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
        // hazard without the pipeline?
                                ||((mem_rdbusy)&&(mem_last_reg == dcdB))
        assign  dcdB_stall = 1'b0;
                                );
`endif
`endif
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
                                        ||((dcdA_rd)&&(dcdA_cc))
 
                                        ||((dcdB_rd)&&(dcdB_cc)))
                                        &&(opvalid)&&(opR_cc);
                                        &&(opvalid)&&(opR_cc);
        //
        //
        //
        //
        //      PIPELINE STAGE #4 :: Apply Instruction
        //      PIPELINE STAGE #4 :: Apply Instruction
        //
        //
        //
        //
 
`ifdef  OPT_NEW_INSTRUCTION_SET
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
                        (opvalid_alu), opn, opA, opB,
                        (opvalid_alu), opn, opA, opB,
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
 
`else
 
        cpuops_deprecated       #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
 
                        (opvalid_alu), opn, opA, opB,
 
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
 
`endif
 
 
 
        generate
 
        if (IMPLEMENT_DIVIDE != 0)
 
        begin
 
                div thedivide(i_clk, i_rst, div_ce, opn[0],
 
                        opA, opB, div_busy, div_valid, div_error, div_result,
 
                        div_flags);
 
        end else begin
 
                assign  div_error = 1'b1;
 
                assign  div_busy  = 1'b0;
 
                assign  div_valid = 1'b0;
 
                assign  div_result= 32'h00;
 
                assign  div_flags = 4'h0;
 
        end endgenerate
 
 
 
        generate
 
        if (IMPLEMENT_FPU != 0)
 
        begin
 
                //
 
                // sfpu thefpu(i_clk, i_rst, fpu_ce,
 
                //      opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
 
                //      fpu_flags);
 
                //
 
                assign  fpu_error = 1'b1;
 
                assign  fpu_busy  = 1'b0;
 
                assign  fpu_valid = 1'b0;
 
                assign  fpu_result= 32'h00;
 
                assign  fpu_flags = 4'h0;
 
        end else begin
 
                assign  fpu_error = 1'b1;
 
                assign  fpu_busy  = 1'b0;
 
                assign  fpu_valid = 1'b0;
 
                assign  fpu_result= 32'h00;
 
                assign  fpu_flags = 4'h0;
 
        end endgenerate
 
 
 
 
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
        initial alF_wr   = 1'b0;
        initial alF_wr   = 1'b0;
        initial alu_wr   = 1'b0;
        initial alu_wr   = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
Line 1011... Line 1058...
                        // These are strobe signals, so clear them if not
                        // These are strobe signals, so clear them if not
                        // set for any particular clock
                        // set for any particular clock
                        alu_wr <= (i_halt)&&(i_dbg_we);
                        alu_wr <= (i_halt)&&(i_dbg_we);
                        alF_wr <= 1'b0;
                        alF_wr <= 1'b0;
                end
                end
 
 
 
`ifdef  OPT_VLIW
 
        reg     r_alu_phase;
 
        initial r_alu_phase = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (alu_ce)
                if (i_rst)
 
                        r_alu_phase <= 1'b0;
 
                else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
 
                        r_alu_phase <= op_phase;
 
        assign  alu_phase = r_alu_phase;
 
`else
 
        assign  alu_phase = 1'b0;
 
`endif
 
 
 
        always @(posedge i_clk)
 
                if ((alu_ce)||(div_ce)||(fpu_ce))
                        alu_reg <= opR;
                        alu_reg <= opR;
                else if ((i_halt)&&(i_dbg_we))
                else if ((i_halt)&&(i_dbg_we))
                        alu_reg <= i_dbg_reg;
                        alu_reg <= i_dbg_reg;
 
 
        reg     [31:0]   dbg_val;
        reg     [31:0]   dbg_val;
        reg             dbgv;
        reg             dbgv;
        always @(posedge i_clk)
        always @(posedge i_clk)
                dbg_val <= i_dbg_data;
                dbg_val <= i_dbg_data;
        initial dbgv = 1'b0;
        initial dbgv = 1'b0;
Line 1049... Line 1111...
        initial alu_pc_valid = 1'b0;
        initial alu_pc_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                alu_pc_valid <= ((alu_ce)
                alu_pc_valid <= ((alu_ce)
                        ||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)&&(~mem_stalled)));
                        ||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)&&(~mem_stalled)));
 
 
 
        wire    bus_lock;
 
`ifdef  OPT_PIPELINED
 
        generate
 
        if (IMPLEMENT_LOCK != 0)
 
        begin
 
                reg     r_bus_lock;
 
                initial r_bus_lock = 1'b0;
 
                always @(posedge i_clk)
 
                        if (i_rst)
 
                                r_bus_lock <= 1'b0;
 
                        else if ((op_ce)&&(op_lock))
 
                                r_bus_lock <= 1'b1;
 
                        else if (~opvalid_mem)
 
                                r_bus_lock <= 1'b0;
 
                assign  bus_lock = r_bus_lock;
 
        end else begin
 
                assign  bus_lock = 1'b0;
 
        end endgenerate
 
`else
 
        assign  bus_lock = 1'b0;
 
`endif
 
 
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
        pipemem #(AW) domem(i_clk, i_rst, mem_ce,
        pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst, mem_ce, bus_lock,
                                (opn[0]), opB, opA, opR,
                                (opn[0]), opB, opA, opR,
                                mem_busy, mem_pipe_stalled,
                                mem_busy, mem_pipe_stalled,
                                mem_valid, bus_err, mem_wreg, mem_result,
                                mem_valid, bus_err, mem_wreg, mem_result,
                        mem_cyc_gbl, mem_cyc_lcl,
                        mem_cyc_gbl, mem_cyc_lcl,
                                mem_stb_gbl, mem_stb_lcl,
                                mem_stb_gbl, mem_stb_lcl,
                                mem_we, mem_addr, mem_data,
                                mem_we, mem_addr, mem_data,
                                mem_ack, mem_stall, mem_err, i_wb_data);
                                mem_ack, mem_stall, mem_err, i_wb_data);
 
 
`else // PIPELINED_BUS_ACCESS
`else // PIPELINED_BUS_ACCESS
        memops  #(AW) domem(i_clk, i_rst, mem_ce,
        memops  #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst, mem_ce, bus_lock,
                                (opn[0]), opB, opA, opR,
                                (opn[0]), opB, opA, opR,
                                mem_busy,
                                mem_busy,
                                mem_valid, bus_err, mem_wreg, mem_result,
                                mem_valid, bus_err, mem_wreg, mem_result,
                        mem_cyc_gbl, mem_cyc_lcl,
                        mem_cyc_gbl, mem_cyc_lcl,
                                mem_stb_gbl, mem_stb_lcl,
                                mem_stb_gbl, mem_stb_lcl,
Line 1104... Line 1188...
        //      Note that the flags needed to be checked before issuing the
        //      Note that the flags needed to be checked before issuing the
        //      bus instruction, so they don't need to be checked here.
        //      bus instruction, so they don't need to be checked here.
        //      Further, alu_wr includes (set_cond), so we don't need to
        //      Further, alu_wr includes (set_cond), so we don't need to
        //      check for that here either.
        //      check for that here either.
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        assign  wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(~clear_pipeline))||(mem_valid);
        assign  wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
`else
`else
        assign  wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid);
        assign  wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
`endif
`endif
        // Which register shall be written?
        // Which register shall be written?
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
        //              One or PC, one for CC, and one for GIE match
        //              One or PC, one for CC, and one for GIE match
 
        //      Note that the alu_reg is the register to write on a divide or
 
        //      FPU operation.
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
        // Are we writing to the CC register?
        // Are we writing to the CC register?
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
        // Are we writing to the PC?
        // Are we writing to the PC?
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
        // What value to write?
        // What value to write?
        assign  wr_reg_vl = (alu_wr)?((dbgv)?dbg_val: alu_result) :mem_result;
        assign  wr_reg_vl = (alu_wr)?((dbgv)?dbg_val: alu_result)
 
                                :((mem_valid) ? mem_result
 
                                :((div_valid) ? div_result
 
                                :fpu_result));
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (wr_reg_ce)
                if (wr_reg_ce)
                        regset[wr_reg_id] <= wr_reg_vl;
                        regset[wr_reg_id] <= wr_reg_vl;
 
 
        //
        //
        // Write back to the condition codes/flags register ...
        // Write back to the condition codes/flags register ...
        // When shall we write to our flags register?  alF_wr already
        // When shall we write to our flags register?  alF_wr already
        // includes the set condition ...
        // includes the set condition ...
        assign  wr_flags_ce = (alF_wr)&&(~clear_pipeline)&&(~alu_illegal);
        assign  wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
`ifdef  OPT_ILLEGAL_INSTRUCTION
        assign  w_uflags = { ufpu_err_flag, udiv_err_flag, ubus_err_flag, trap, ill_err_u,    1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
        assign  w_uflags = { ubus_err_flag, trap, ill_err_u,    1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
        assign  w_iflags = { ifpu_err_flag, idiv_err_flag, ibus_err_flag, trap, ill_err_i,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
        assign  w_iflags = { ibus_err_flag, trap, ill_err_i,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
 
`else
 
        assign  w_uflags = { ubus_err_flag, trap, ill_err_u,     1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
 
        assign  w_iflags = { ibus_err_flag, trap, ill_err_i, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
 
`endif
 
        // What value to write?
        // What value to write?
        always @(posedge i_clk)
        always @(posedge i_clk)
                // If explicitly writing the register itself
                // If explicitly writing the register itself
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
                        flags <= wr_reg_vl[3:0];
                        flags <= wr_reg_vl[3:0];
                // Otherwise if we're setting the flags from an ALU operation
                // Otherwise if we're setting the flags from an ALU operation
                else if ((wr_flags_ce)&&(alu_gie))
                else if ((wr_flags_ce)&&(alu_gie))
                        flags <= alu_flags;
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
 
                                : alu_flags);
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                        iflags <= wr_reg_vl[3:0];
                        iflags <= wr_reg_vl[3:0];
                else if ((wr_flags_ce)&&(~alu_gie))
                else if ((wr_flags_ce)&&(~alu_gie))
                        iflags <= alu_flags;
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
 
                                : alu_flags);
 
 
        // The 'break' enable  bit.  This bit can only be set from supervisor
        // The 'break' enable  bit.  This bit can only be set from supervisor
        // mode.  It control what the CPU does upon encountering a break
        // mode.  It control what the CPU does upon encountering a break
        // instruction.
        // instruction.
        //
        //
Line 1173... Line 1261...
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
 
                                &&(~div_busy)&&(~fpu_busy)
                                &&(~clear_pipeline)
                                &&(~clear_pipeline)
                        ||((~alu_gie)&&(bus_err))
                        ||((~alu_gie)&&(bus_err))
 
                        ||((~alu_gie)&&(div_valid)&&(div_error))
 
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error))
                        ||((~alu_gie)&&(alu_valid)&&(alu_illegal));
                        ||((~alu_gie)&&(alu_valid)&&(alu_illegal));
`else
`else
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
                                &&(~clear_pipeline))
                                &&(~clear_pipeline))
Line 1191... Line 1282...
        // interrupt mode causes the processor to halt until a reset.  This is
        // interrupt mode causes the processor to halt until a reset.  This is
        // a panic/fault halt.  The trick is that you cannot be allowed to
        // a panic/fault halt.  The trick is that you cannot be allowed to
        // set the sleep bit and switch to supervisor mode in the same 
        // set the sleep bit and switch to supervisor mode in the same 
        // instruction: users are not allowed to halt the CPU.
        // instruction: users are not allowed to halt the CPU.
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||((i_interrupt)&&(gie)))
                if ((i_rst)||(w_switch_to_interrupt))
                        sleep <= 1'b0;
                        sleep <= 1'b0;
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
                        // In supervisor mode, we have no protections.  The
                        // In supervisor mode, we have no protections.  The
                        // supervisor can set the sleep bit however he wants.
                        // supervisor can set the sleep bit however he wants.
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
                        // Well ... not quite.  Switching to user mode and
 
                        // sleep mode shouold only be possible if the interrupt
 
                        // flag isn't set.
 
                        //      Thus: if (i_interrupt)&&(wr_reg_vl[GIE])
 
                        //              don't set the sleep bit
 
                        //      otherwise however it would o.w. be set
 
                        sleep <= (wr_reg_vl[`CPU_SLEEP_BIT])
 
                                &&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT]));
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
                        // In user mode, however, you can only set the sleep
                        // In user mode, however, you can only set the sleep
                        // mode while remaining in user mode.  You can't switch
                        // mode while remaining in user mode.  You can't switch
                        // to sleep mode *and* supervisor mode at the same
                        // to sleep mode *and* supervisor mode at the same
                        // time, lest you halt the CPU.
                        // time, lest you halt the CPU.
Line 1215... Line 1313...
                        step <= 1'b0;
                        step <= 1'b0;
 
 
        // The GIE register.  Only interrupts can disable the interrupt register
        // The GIE register.  Only interrupts can disable the interrupt register
        assign  w_switch_to_interrupt = (gie)&&(
        assign  w_switch_to_interrupt = (gie)&&(
                        // On interrupt (obviously)
                        // On interrupt (obviously)
                        (i_interrupt)
                        ((i_interrupt)&&(~alu_phase)&&(~bus_lock))
                        // If we are stepping the CPU
                        // If we are stepping the CPU
                        ||((alu_pc_valid)&&(step))
                        ||((alu_pc_valid)&&(step)&&(~alu_phase)&&(~bus_lock))
                        // If we encounter a break instruction, if the break
                        // If we encounter a break instruction, if the break
                        //      enable isn't set.
                        //      enable isn't set.
                        ||((master_ce)&&(~mem_rdbusy)&&(op_break)&&(~break_en))
                        ||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
 
                                &&(op_break)&&(~break_en))
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
                        // On an illegal instruction
                        // On an illegal instruction
                        ||((alu_valid)&&(alu_illegal))
                        ||((alu_valid)&&(alu_illegal))
`endif
`endif
 
                        ||((div_valid)&&(div_error))
 
                        ||((fpu_valid)&&(fpu_error))
 
                        ||(bus_err)
                        // If we write to the CC register
                        // If we write to the CC register
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                                &&(wr_reg_id[4])&&(wr_write_cc))
                                &&(wr_reg_id[4])&&(wr_write_cc))
                        );
                        );
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
Line 1246... Line 1348...
 
 
        initial trap = 1'b0;
        initial trap = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        trap <= 1'b0;
                        trap <= 1'b0;
                else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                                &&(wr_reg_id[4])&&(wr_write_cc))
                                &&(wr_write_cc)) // &&(wr_reg_id[4]) implied
                        trap <= 1'b1;
                        trap <= 1'b1;
                // else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
 
                                // &&(~i_dbg_data[`CPU_GIE_BIT]))
 
                        // trap <= i_dbg_data[`CPU_TRAP_BIT];
 
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        trap <= 1'b0;
                        trap <= 1'b0;
 
 
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        initial ill_err_i = 1'b0;
        initial ill_err_i = 1'b0;
Line 1315... Line 1414...
                                &&(wr_reg_id[4])&&(wr_write_cc))
                                &&(wr_reg_id[4])&&(wr_write_cc))
                        ubus_err_flag <= 1'b0;
                        ubus_err_flag <= 1'b0;
                else if ((bus_err)&&(alu_gie))
                else if ((bus_err)&&(alu_gie))
                        ubus_err_flag <= 1'b1;
                        ubus_err_flag <= 1'b1;
 
 
 
        generate
 
        if (IMPLEMENT_DIVIDE != 0)
 
        begin
 
                reg     r_idiv_err_flag, r_udiv_err_flag;
 
 
 
                // Supervisor/interrupt divide (by zero) error flag -- this will
 
                // crash the CPU if ever set.  This bit is thus available for us
 
                // to be able to tell if/why the CPU crashed.
 
                initial r_idiv_err_flag = 1'b0;
 
                always @(posedge i_clk)
 
                        if (i_rst)
 
                                r_idiv_err_flag <= 1'b0;
 
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
 
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT]))
 
                                r_idiv_err_flag <= 1'b0;
 
                        else if ((div_error)&&(div_valid)&&(~alu_gie))
 
                                r_idiv_err_flag <= 1'b1;
 
                // User divide (by zero) error flag -- if ever set, it will
 
                // cause a sudden switch interrupt to supervisor mode.  
 
                initial r_udiv_err_flag = 1'b0;
 
                always @(posedge i_clk)
 
                        if (i_rst)
 
                                r_udiv_err_flag <= 1'b0;
 
                        else if (w_release_from_interrupt)
 
                                r_udiv_err_flag <= 1'b0;
 
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
 
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT])
 
                                        &&(wr_reg_id[4])&&(wr_write_cc))
 
                                r_udiv_err_flag <= 1'b0;
 
                        else if ((div_error)&&(alu_gie)&&(div_valid))
 
                                r_udiv_err_flag <= 1'b1;
 
 
 
                assign  idiv_err_flag = r_idiv_err_flag;
 
                assign  udiv_err_flag = r_udiv_err_flag;
 
        end else begin
 
                assign  idiv_err_flag = 1'b0;
 
                assign  udiv_err_flag = 1'b0;
 
        end endgenerate
 
 
 
        generate
 
        if (IMPLEMENT_FPU !=0)
 
        begin
 
                // Supervisor/interrupt floating point error flag -- this will
 
                // crash the CPU if ever set.
 
                reg             r_ifpu_err_flag, r_ufpu_err_flag;
 
                initial r_ifpu_err_flag = 1'b0;
 
                always @(posedge i_clk)
 
                        if (i_rst)
 
                                r_ifpu_err_flag <= 1'b0;
 
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
 
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT]))
 
                                r_ifpu_err_flag <= 1'b0;
 
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
 
                                r_ifpu_err_flag <= 1'b1;
 
                // User floating point error flag -- if ever set, it will cause
 
                // a sudden switch interrupt to supervisor mode.  
 
                initial r_ufpu_err_flag = 1'b0;
 
                always @(posedge i_clk)
 
                        if (i_rst)
 
                                r_ufpu_err_flag <= 1'b0;
 
                        else if (w_release_from_interrupt)
 
                                r_ufpu_err_flag <= 1'b0;
 
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
 
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT])
 
                                        &&(wr_reg_id[4])&&(wr_write_cc))
 
                                r_ufpu_err_flag <= 1'b0;
 
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
 
                                r_ufpu_err_flag <= 1'b1;
 
 
 
                assign  ifpu_err_flag = r_ifpu_err_flag;
 
                assign  ufpu_err_flag = r_ufpu_err_flag;
 
        end else begin
 
                assign  ifpu_err_flag = 1'b0;
 
                assign  ufpu_err_flag = 1'b0;
 
        end endgenerate
 
 
 
`ifdef  OPT_VLIW
 
        reg             r_ihalt_phase, r_uhalt_phase;
 
 
 
        initial r_ihalt_phase = 0;
 
        initial r_uhalt_phase = 0;
 
        always @(posedge i_clk)
 
                if (~alu_gie)
 
                        r_ihalt_phase <= alu_phase;
 
        always @(posedge i_clk)
 
                if (alu_gie)
 
                        r_uhalt_phase <= alu_phase;
 
                else if (w_release_from_interrupt)
 
                        r_uhalt_phase <= 1'b0;
 
 
 
        assign  ihalt_phase = r_ihalt_phase;
 
        assign  uhalt_phase = r_uhalt_phase;
 
`else
 
        assign  ihalt_phase = 1'b0;
 
        assign  uhalt_phase = 1'b0;
 
`endif
 
 
        //
        //
        // Write backs to the PC register, and general increments of it
        // Write backs to the PC register, and general increments of it
        //      We support two: upc and ipc.  If the instruction is normal,
        //      We support two: upc and ipc.  If the instruction is normal,
        // we increment upc, if interrupt level we increment ipc.  If
        // we increment upc, if interrupt level we increment ipc.  If
        // the instruction writes the PC, we write whichever PC is appropriate.
        // the instruction writes the PC, we write whichever PC is appropriate.
Line 1348... Line 1544...
                        pf_pc <= ipc;
                        pf_pc <= ipc;
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        pf_pc <= upc;
                        pf_pc <= upc;
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                        pf_pc <= wr_reg_vl[(AW-1):0];
                        pf_pc <= wr_reg_vl[(AW-1):0];
                else if (dcd_ce)
`ifdef  OPT_PIPELINED
 
                else if ((~new_pc)&&((dcd_early_branch)&&(dcdvalid)))
 
                        pf_pc <= dcd_branch_pc + 1;
 
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
 
`else
 
                else if ((alu_pc_valid)&&(~clear_pipeline))
 
                        pf_pc <= alu_pc;
 
`endif
 
 
        initial new_pc = 1'b1;
        initial new_pc = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_pf_cache))
                if ((i_rst)||(i_clear_pf_cache))
                        new_pc <= 1'b1;
                        new_pc <= 1'b1;
Line 1376... Line 1579...
                        o_dbg_reg <= regset[i_dbg_reg];
                        o_dbg_reg <= regset[i_dbg_reg];
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
                        begin
                        begin
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
                                o_dbg_reg[12:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
                        end
                        end
                end
                end
        end else begin
        end else begin
                always @(posedge i_clk)
                always @(posedge i_clk)
Line 1388... Line 1591...
                        o_dbg_reg <= regset[i_dbg_reg];
                        o_dbg_reg <= regset[i_dbg_reg];
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
                        begin
                        begin
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
                                o_dbg_reg[12:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
                        end
                        end
                end
                end
        end endgenerate
        end endgenerate
 
 
Line 1416... Line 1619...
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
 
 
`ifdef  DEBUG_SCOPE
`ifdef  DEBUG_SCOPE
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_debug <= {
                o_debug <= {
                        pf_pc[7:0],
                /*
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
                        pf_pc[3:0], flags,
                        op_ce, alu_ce, mem_ce,
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
                        //
                        op_ce, alu_ce, mem_ce,
                        master_ce, opvalid_alu, opvalid_mem,
                        //
                        //
                        master_ce, opvalid_alu, opvalid_mem,
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
                        //
                        mem_we,
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
                        // ((opvalid_alu)&&(alu_stall))
                        mem_we,
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
                        // ((opvalid_alu)&&(alu_stall))
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
                        // opA[23:20], opA[3:0],
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
                        gie, sleep,
                        // opA[23:20], opA[3:0],
                        wr_reg_vl[5:0]
                        gie, sleep,
 
                        wr_reg_vl[5:0]
 
                */
 
                        i_rst, master_ce, (new_pc),
 
                        ((dcd_early_branch)&&(dcdvalid)),
 
                        pf_valid, pf_illegal,
 
                        op_ce, dcd_ce, dcdvalid, dcd_stalled,
 
                        pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
 
                        pf_pc[7:0], pf_addr[7:0]
                        };
                        };
`endif
`endif
 
 
endmodule
endmodule
 
 
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