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[/] [zipcpu/] [trunk/] [rtl/] [cpudefs.v] - Diff between revs 205 and 209

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// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
// Copyright (C) 2015-2019, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
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//
//
// The first couple options control the Zip CPU instruction set, and how
// The first couple options control the Zip CPU instruction set, and how
// it handles various instructions within the set:
// it handles various instructions within the set:
//
//
//
//
// OPT_ILLEGAL_INSTRUCTION is part of a new section of code that is supposed
 
// to recognize illegal instructions and interrupt the CPU whenever one such
 
// instruction is encountered.  The goal is to create a soft floating point
 
// unit via this approach, that can then be replaced with a true floating point
 
// unit.  As I'm not there yet, it just catches illegal instructions and
 
// interrupts the CPU on any such instruction--when defined.  Otherwise,
 
// illegal instructions are quietly ignored and their behaviour is ...
 
// undefined. (Many get treated like NOOPs ...)
 
//
 
// I recommend setting this flag so highly, that I'm likely going to remove
 
// the option to turn this off in future versions of this CPU.
 
//
 
`define OPT_ILLEGAL_INSTRUCTION
 
//
 
//
 
//
//
// OPT_MULTIPLY controls whether or not the multiply is built and included
// OPT_MULTIPLY controls whether or not the multiply is built and included
// in the ALU by default.  Set this option and a parameter will be set that
// in the ALU by default.  Set this option and a parameter will be set that
// includes the multiply.  (This parameter may still be overridden, as with
// includes the multiply.  (This parameter may still be overridden, as with
// any parameter ...)  If the multiply is not included and
// any parameter ...)  If the multiply is not included and
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`define OPT_TRADITIONAL_PFCACHE
`define OPT_TRADITIONAL_PFCACHE
//
//
//
//
//
//
//
//
 
// OPT_DCACHE enables a CPU data cache for (hopefully) better performance
 
// in terms of speed.  It requires telling the CPU which parts of memory
 
// can be cachable in terms of three separate address regions: one for the
 
// SDRAM, one for the flash, and another for the block RAM.
 
//
 
`define OPT_DCACHE
 
//
 
//
 
//
// OPT_PIPELINED_BUS_ACCESS controls whether or not LOD/STO instructions
// OPT_PIPELINED_BUS_ACCESS controls whether or not LOD/STO instructions
// can take advantaged of pipelined bus instructions.  To be eligible, the
// can take advantaged of pipelined bus instructions.  To be eligible, the
// operations must be identical (cannot pipeline loads and stores, just loads
// operations must be identical (cannot pipeline loads and stores, just loads
// only or stores only), and the addresses must either be identical or one up
// only or stores only), and the addresses must either be identical or one up
// from the previous address.  Further, the load/store string must all have
// from the previous address.  Further, the load/store string must all have
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//
//
`endif  // OPT_DOUBLE_FETCH
`endif  // OPT_DOUBLE_FETCH
`endif  // OPT_SINGLE_FETCH
`endif  // OPT_SINGLE_FETCH
//
//
//
//
 
// [EXPERIMENTAL--and not (yet) finished]
 
// OPT_MMU determines whether or not an MMU will be included in the ZipSystem
 
// containing the ZipCPU.  When set, the ZipCPU will route all memory accesses
 
// through the MMU as an address translator, creating a form of Virtual memory.
 
//
 
// `define      OPT_MMU
//
//
// Now let's talk about peripherals for a moment.  These next two defines
// Now let's talk about peripherals for a moment.  These next two defines
// control whether the DMA controller is included in the Zip System, and
// control whether the DMA controller is included in the Zip System, and
// whether or not the 8 accounting timers are also included.  Set these to
// whether or not the 8 accounting timers are also included.  Set these to
// include the respective peripherals, comment them out not to.
// include the respective peripherals, comment them out not to.

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