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Line 148... |
// speed isn't as important. Otherwise, just leave this undefined.
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// speed isn't as important. Otherwise, just leave this undefined.
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//
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//
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// `define OPT_SINGLE_FETCH
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// `define OPT_SINGLE_FETCH
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//
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//
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//
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//
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// OPT_DOUBLE_FETCH is an alternative to OPT_SINGLE_FETCH. It is designed to
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// increase performance primarily when using an instruction memory which has
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// one cost for a random access, and a second (lower) cost for sequential
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// access. The driving example behind this implementation was flash memory
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// with 34 clocks for an initial access and 16 clocks for any subsequent access,
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// but SDRAM memory with 27 clocks for an initial access and 1 clock for a
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// subsequent access is also a good example. Even block RAM might be a good
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// example, if there were any bus delays in getting to the RAM device. Using
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// OPT_DOUBLE_FETCH also increases the pipeline speed, as it allows CIS
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// instructions and therefore partial pipelining. (No work is done to resolve
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// pipeline conflicts past the decode stage, as is the case with full pipeline
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// mode.
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//
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// Do not define OPT_DOUBLE_FETCH if you wish to fully pipeline the CPU. Do
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// not define both OPT_DOUBLE_FETCH and OPT_SINGLE_FETCH (the ifndef below
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// should prevent that).
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//
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//
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`ifndef OPT_SINGLE_FETCH
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// `define OPT_DOUBLE_FETCH
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`endif
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//
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//
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//
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// The ZipCPU ISA defines an optional compressed instruction set (CIS)
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// complement. This compressed instruction format allows two instructions to
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// be packed into the same instruction word. Some instructions can be so
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// compressed, although not all. Compressed instructions take the same time to
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// complete--they are just compressed within memory to spare troubles with the
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// prefetch. Set OPT_CIS to include these compressed instructions as part of
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// the instruction set.
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//
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`define OPT_CIS // COST: about 87 LUTs
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//
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//
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//
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//
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// OPT_EARLY_BRANCHING is an attempt to execute a BRA statement as early
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// as possible, to avoid as many pipeline stalls on a branch as possible.
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// With the OPT_TRADITIONAL_PFCACHE, BRA instructions cost only a single
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// extra stall cycle, while LJMP instructions cost two (assuming the target is
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// in the cache). Indeed, the result is that a BRA instruction can be used as
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// the compiler's branch prediction optimizer: BRA's barely stall, while
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// conditional branches will always suffer about 4 stall cycles or so.
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//
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// I recommend setting this flag, so as to turn early branching on---if you
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// have the LUTs available to afford it.
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//
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`define OPT_EARLY_BRANCHING
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//
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//
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//
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//
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//
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// The next several options are pipeline optimization options. They make no
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// The next several options are pipeline optimization options. They make no
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// sense in a single instruction fetch mode, hence we #ifndef them so they
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// sense in a single instruction fetch mode, hence we #ifndef them so they
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// are only defined if we are in a full pipelined mode (i.e. OPT_SINGLE_FETCH
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// are only defined if we are in a full pipelined mode (i.e. OPT_SINGLE_FETCH
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// is not defined).
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// is not defined).
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//
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//
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`ifndef OPT_SINGLE_FETCH
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`ifndef OPT_SINGLE_FETCH
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`ifndef OPT_DOUBLE_FETCH
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//
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//
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//
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//
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//
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//
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// OPT_PIPELINED is the natural result and opposite of using the single
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// OPT_PIPELINED is the natural result and opposite of using the single
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// instruction fetch unit. If you are not using that unit, the ZipCPU will
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// instruction fetch unit. If you are not using that unit, the ZipCPU will
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| Line 183... |
Line 236... |
//
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//
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`define OPT_TRADITIONAL_PFCACHE
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`define OPT_TRADITIONAL_PFCACHE
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//
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//
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//
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//
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//
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//
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// OPT_EARLY_BRANCHING is an attempt to execute a BRA statement as early
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// as possible, to avoid as many pipeline stalls on a branch as possible.
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// It's not tremendously successful yet--BRA's still suffer stalls,
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// but I intend to keep working on this approach until the number of stalls
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// gets down to one or (ideally) zero. (With the OPT_TRADITIONAL_PFCACHE, this
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// gets down to a single stall cycle ...) That way a "BRA" can be used as the
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// compiler's branch prediction optimizer: BRA's barely stall, while branches
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// on conditions will always suffer about 4 stall cycles or so.
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//
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// I recommend setting this flag, so as to turn early branching on.
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//
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`define OPT_EARLY_BRANCHING
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//
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//
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//
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//
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// OPT_PIPELINED_BUS_ACCESS controls whether or not LOD/STO instructions
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// OPT_PIPELINED_BUS_ACCESS controls whether or not LOD/STO instructions
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// can take advantaged of pipelined bus instructions. To be eligible, the
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// can take advantaged of pipelined bus instructions. To be eligible, the
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// operations must be identical (cannot pipeline loads and stores, just loads
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// operations must be identical (cannot pipeline loads and stores, just loads
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// only or stores only), and the addresses must either be identical or one up
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// only or stores only), and the addresses must either be identical or one up
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| Line 216... |
Line 255... |
//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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// The instruction set defines an optional compressed instruction set (CIS)
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`endif // OPT_DOUBLE_FETCH
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// complement. These were at one time erroneously called Very Long Instruction
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// Words. They are more appropriately referred to as compressed instructions.
|
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// The compressed instruction format allows two instructions to be packed into
|
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// the same instruction word. Some instructions can be compressed, not all.
|
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// Compressed instructions take the same time to complete. Set OPT_CIS to
|
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// include these double instructions as part of the instruction set. These
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// instructions are designed to get more code density from the instruction set,
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// and to hopefully take some pain off of the performance of the pre-fetch and
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// instruction cache.
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//
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// These new instructions, however, also necessitate a change in the Zip
|
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// CPU--the Zip CPU can no longer execute instructions atomically. It must
|
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// now execute non-CIS instructions, or CIS instruction pairs, atomically.
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// This logic has been added into the ZipCPU, but it has not (yet) been
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// tested thoroughly.
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//
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//
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`define OPT_CIS
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//
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//
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//
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`endif // OPT_SINGLE_FETCH
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`endif // OPT_SINGLE_FETCH
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//
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//
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//
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//
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//
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//
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// Now let's talk about peripherals for a moment. These next two defines
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// Now let's talk about peripherals for a moment. These next two defines
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