| Line 8... |
Line 8... |
// nearly 24 clock cycles per read, this 'cache' module
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// nearly 24 clock cycles per read, this 'cache' module
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// is offered to minimize the effect. The CPU may now request
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// is offered to minimize the effect. The CPU may now request
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// some amount of flash to be copied into this on-chip RAM,
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// some amount of flash to be copied into this on-chip RAM,
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// and then access it with nearly zero latency.
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// and then access it with nearly zero latency.
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//
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//
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|
// Status: This file is no longer being used as an active file within
|
|
// the ZipCPU project. It's an older file from an idea that
|
|
// never really caught traction.
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//
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// Interface:
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// Interface:
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// FlashCache sits on the Wishbone bus as both a slave and a master.
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// FlashCache sits on the Wishbone bus as both a slave and a master.
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// Slave requests for memory will get mapped to a local RAM, from which
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// Slave requests for memory will get mapped to a local RAM, from which
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// reads and writes may take place.
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// reads and writes may take place.
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//
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//
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| Line 33... |
Line 37... |
// the value if read address is less than the current copy
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// the value if read address is less than the current copy
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// address, or else they will stall until the read address is
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// address, or else they will stall until the read address is
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// less than the copy address.
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// less than the copy address.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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