///////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Filename: flashcache.v
|
// Filename: flashcache.v
|
//
|
//
|
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
//
|
//
|
// Purpose: Since my Zip CPU has primary access to a flash, which requires
|
// Purpose: Since my Zip CPU has primary access to a flash, which requires
|
// nearly 24 clock cycles per read, this 'cache' module
|
// nearly 24 clock cycles per read, this 'cache' module
|
// is offered to minimize the effect. The CPU may now request
|
// is offered to minimize the effect. The CPU may now request
|
// some amount of flash to be copied into this on-chip RAM,
|
// some amount of flash to be copied into this on-chip RAM,
|
// and then access it with nearly zero latency.
|
// and then access it with nearly zero latency.
|
//
|
//
|
// Status: This file is no longer being used as an active file within
|
// Status: This file is no longer being used as an active file within
|
// the ZipCPU project. It's an older file from an idea that
|
// the ZipCPU project. It's an older file from an idea that
|
// never really caught traction.
|
// never really caught traction.
|
//
|
//
|
// Interface:
|
// Interface:
|
// FlashCache sits on the Wishbone bus as both a slave and a master.
|
// FlashCache sits on the Wishbone bus as both a slave and a master.
|
// Slave requests for memory will get mapped to a local RAM, from which
|
// Slave requests for memory will get mapped to a local RAM, from which
|
// reads and writes may take place.
|
// reads and writes may take place.
|
//
|
//
|
// This cache supports a single control register: the base wishbone address
|
// This cache supports a single control register: the base wishbone address
|
// of the device to copy memory from. The bottom bit if this address must
|
// of the device to copy memory from. The bottom bit if this address must
|
// be zero (or it will be silently rendered as zero). When read, this
|
// be zero (or it will be silently rendered as zero). When read, this
|
// bottom bit will indicate 1) that the controller is still loading memory
|
// bottom bit will indicate 1) that the controller is still loading memory
|
// into the cache, or 0) that the cache is ready to be used.
|
// into the cache, or 0) that the cache is ready to be used.
|
//
|
//
|
// Writing to this register will initiate a memory copy from the (new)
|
// Writing to this register will initiate a memory copy from the (new)
|
// address. Once done, the loading bit will be cleared and an interrupt
|
// address. Once done, the loading bit will be cleared and an interrupt
|
// generated.
|
// generated.
|
//
|
//
|
// Where this memory is placed on the wishbone bus is entirely up to the
|
// Where this memory is placed on the wishbone bus is entirely up to the
|
// wishbone bus control logic. Setting the memory base to an
|
// wishbone bus control logic. Setting the memory base to an
|
// address controlled by this flashcache will produce unusable
|
// address controlled by this flashcache will produce unusable
|
// results, and may well hang the bus.
|
// results, and may well hang the bus.
|
// Reads from the memory before complete will return immediately with
|
// Reads from the memory before complete will return immediately with
|
// the value if read address is less than the current copy
|
// the value if read address is less than the current copy
|
// address, or else they will stall until the read address is
|
// address, or else they will stall until the read address is
|
// less than the copy address.
|
// less than the copy address.
|
//
|
//
|
// Creator: Dan Gisselquist, Ph.D.
|
// Creator: Dan Gisselquist, Ph.D.
|
// Gisselquist Technology, LLC
|
// Gisselquist Technology, LLC
|
//
|
//
|
///////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2015, Gisselquist Technology, LLC
|
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
|
//
|
//
|
// This program is free software (firmware): you can redistribute it and/or
|
// This program is free software (firmware): you can redistribute it and/or
|
// modify it under the terms of the GNU General Public License as published
|
// modify it under the terms of the GNU General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// your option) any later version.
|
// your option) any later version.
|
//
|
//
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// for more details.
|
// for more details.
|
//
|
//
|
|
// You should have received a copy of the GNU General Public License along
|
|
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
|
|
// target there if the PDF file isn't present.) If not, see
|
|
// <http://www.gnu.org/licenses/> for a copy.
|
|
//
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// http://www.gnu.org/licenses/gpl.html
|
// http://www.gnu.org/licenses/gpl.html
|
//
|
//
|
//
|
//
|
///////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
|
//
|
//
|
//
|
module flashcache(i_clk,
|
module flashcache(i_clk,
|
// Wishbone contrl interface
|
// Wishbone contrl interface
|
i_wb_cyc, i_wb_stb,i_wb_ctrl_stb, i_wb_we, i_wb_addr, i_wb_data,
|
i_wb_cyc, i_wb_stb,i_wb_ctrl_stb, i_wb_we, i_wb_addr, i_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
// Wishbone copy interface
|
// Wishbone copy interface
|
o_cp_cyc, o_cp_stb, o_cp_we, o_cp_addr, o_cp_data,
|
o_cp_cyc, o_cp_stb, o_cp_we, o_cp_addr, o_cp_data,
|
i_cp_ack, i_cp_stall, i_cp_data,
|
i_cp_ack, i_cp_stall, i_cp_data,
|
o_int);
|
o_int);
|
parameter LGCACHELEN=10; // 4 kB
|
parameter LGCACHELEN=10; // 4 kB
|
input i_clk;
|
input i_clk;
|
// Control interface, CPU interface to cache
|
// Control interface, CPU interface to cache
|
input i_wb_cyc, i_wb_stb,i_wb_ctrl_stb, i_wb_we;
|
input i_wb_cyc, i_wb_stb,i_wb_ctrl_stb, i_wb_we;
|
input [(LGCACHELEN-1):0] i_wb_addr;
|
input [(LGCACHELEN-1):0] i_wb_addr;
|
input [31:0] i_wb_data;
|
input [31:0] i_wb_data;
|
output reg o_wb_ack;
|
output reg o_wb_ack;
|
output wire o_wb_stall;
|
output wire o_wb_stall;
|
output wire [31:0] o_wb_data;
|
output wire [31:0] o_wb_data;
|
// Interface to peripheral bus, including flash
|
// Interface to peripheral bus, including flash
|
output reg o_cp_cyc, o_cp_stb;
|
output reg o_cp_cyc, o_cp_stb;
|
output wire o_cp_we;
|
output wire o_cp_we;
|
output reg [31:0] o_cp_addr;
|
output reg [31:0] o_cp_addr;
|
output wire [31:0] o_cp_data;
|
output wire [31:0] o_cp_data;
|
input i_cp_ack, i_cp_stall;
|
input i_cp_ack, i_cp_stall;
|
input [31:0] i_cp_data;
|
input [31:0] i_cp_data;
|
// And an interrupt to send once we complete
|
// And an interrupt to send once we complete
|
output reg o_int;
|
output reg o_int;
|
|
|
reg loading;
|
reg loading;
|
reg [31:0] cache_base;
|
reg [31:0] cache_base;
|
reg [31:0] cache [0:((1<<LGCACHELEN)-1)];
|
reg [31:0] cache [0:((1<<LGCACHELEN)-1)];
|
|
|
// Decouple writing the cache base from the highly delayed bus lines
|
// Decouple writing the cache base from the highly delayed bus lines
|
reg wr_cache_base_flag;
|
reg wr_cache_base_flag;
|
reg [31:0] wr_cache_base_value;
|
reg [31:0] wr_cache_base_value;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
wr_cache_base_flag <= ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we));
|
wr_cache_base_flag <= ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we));
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
wr_cache_base_value<= { i_wb_data[31:1], 1'b0 };
|
wr_cache_base_value<= { i_wb_data[31:1], 1'b0 };
|
|
|
initial cache_base = 32'hffffffff;
|
initial cache_base = 32'hffffffff;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wr_cache_base_flag)
|
if (wr_cache_base_flag)
|
cache_base <= wr_cache_base_value;
|
cache_base <= wr_cache_base_value;
|
|
|
reg new_cache_base;
|
reg new_cache_base;
|
initial new_cache_base = 1'b0;
|
initial new_cache_base = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wr_cache_base_flag)&&(cache_base != wr_cache_base_value))
|
if ((wr_cache_base_flag)&&(cache_base != wr_cache_base_value))
|
new_cache_base <= 1'b1;
|
new_cache_base <= 1'b1;
|
else
|
else
|
new_cache_base <= 1'b0;
|
new_cache_base <= 1'b0;
|
|
|
reg [(LGCACHELEN-1):0] rdaddr;
|
reg [(LGCACHELEN-1):0] rdaddr;
|
initial loading = 1'b0;
|
initial loading = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (new_cache_base)
|
if (new_cache_base)
|
begin
|
begin
|
loading <= 1'b1;
|
loading <= 1'b1;
|
o_cp_cyc <= 1'b0;
|
o_cp_cyc <= 1'b0;
|
end else if ((~o_cp_cyc)&&(loading))
|
end else if ((~o_cp_cyc)&&(loading))
|
begin
|
begin
|
o_cp_cyc <= 1'b1;
|
o_cp_cyc <= 1'b1;
|
end else if (o_cp_cyc)
|
end else if (o_cp_cyc)
|
begin
|
begin
|
// Handle the ack/read line
|
// Handle the ack/read line
|
if (i_cp_ack)
|
if (i_cp_ack)
|
begin
|
begin
|
if (&rdaddr)
|
if (&rdaddr)
|
begin
|
begin
|
o_cp_cyc <= 1'b0;
|
o_cp_cyc <= 1'b0;
|
loading <= 1'b0;
|
loading <= 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (~o_cp_cyc)
|
if (~o_cp_cyc)
|
o_cp_addr <= cache_base;
|
o_cp_addr <= cache_base;
|
else if ((o_cp_cyc)&&(o_cp_stb)&&(~i_cp_stall))
|
else if ((o_cp_cyc)&&(o_cp_stb)&&(~i_cp_stall))
|
o_cp_addr <= o_cp_addr + 1;;
|
o_cp_addr <= o_cp_addr + 1;;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((~o_cp_cyc)&&(loading))
|
if ((~o_cp_cyc)&&(loading))
|
o_cp_stb <= 1'b1;
|
o_cp_stb <= 1'b1;
|
else if ((o_cp_cyc)&&(o_cp_stb)&&(~i_cp_stall))
|
else if ((o_cp_cyc)&&(o_cp_stb)&&(~i_cp_stall))
|
begin
|
begin
|
// We've made our last request
|
// We've made our last request
|
if (o_cp_addr >= cache_base + { {(32-LGCACHELEN-1){1'b0}}, 1'b1, {(LGCACHELEN){1'b0}}})
|
if (o_cp_addr >= cache_base + { {(32-LGCACHELEN-1){1'b0}}, 1'b1, {(LGCACHELEN){1'b0}}})
|
o_cp_stb <= 1'b0;
|
o_cp_stb <= 1'b0;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (~loading)
|
if (~loading)
|
rdaddr <= 0;
|
rdaddr <= 0;
|
else if ((o_cp_cyc)&&(i_cp_ack))
|
else if ((o_cp_cyc)&&(i_cp_ack))
|
rdaddr <= rdaddr + 1;
|
rdaddr <= rdaddr + 1;
|
|
|
initial o_int = 1'b0;
|
initial o_int = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((o_cp_cyc)&&(i_cp_ack)&&(&rdaddr))
|
if ((o_cp_cyc)&&(i_cp_ack)&&(&rdaddr))
|
o_int <= 1'b1;
|
o_int <= 1'b1;
|
else
|
else
|
o_int <= 1'b0;
|
o_int <= 1'b0;
|
|
|
assign o_cp_we = 1'b0;
|
assign o_cp_we = 1'b0;
|
assign o_cp_data = 32'h00;
|
assign o_cp_data = 32'h00;
|
|
|
|
|
//
|
//
|
// Writes to our cache ... always delayed by a clock.
|
// Writes to our cache ... always delayed by a clock.
|
// Clock 0 : Write request
|
// Clock 0 : Write request
|
// Clock 1 : Write takes place
|
// Clock 1 : Write takes place
|
// Clock 2 : Available for reading
|
// Clock 2 : Available for reading
|
//
|
//
|
reg we;
|
reg we;
|
reg [(LGCACHELEN-1):0] waddr;
|
reg [(LGCACHELEN-1):0] waddr;
|
reg [31:0] wval;
|
reg [31:0] wval;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
we <= (loading)?((o_cp_cyc)&&(i_cp_ack)):(i_wb_cyc)&&(i_wb_stb)&&(i_wb_we);
|
we <= (loading)?((o_cp_cyc)&&(i_cp_ack)):(i_wb_cyc)&&(i_wb_stb)&&(i_wb_we);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
waddr <= (loading)?rdaddr:i_wb_addr;
|
waddr <= (loading)?rdaddr:i_wb_addr;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
wval <= (loading)?i_cp_data:i_wb_data;
|
wval <= (loading)?i_cp_data:i_wb_data;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (we)
|
if (we)
|
cache[waddr] <= wval;
|
cache[waddr] <= wval;
|
|
|
reg [31:0] cache_data;
|
reg [31:0] cache_data;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_wb_cyc)&&(i_wb_stb))
|
if ((i_wb_cyc)&&(i_wb_stb))
|
cache_data <= cache[i_wb_addr];
|
cache_data <= cache[i_wb_addr];
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_wb_ack <= (i_wb_cyc)&&(
|
o_wb_ack <= (i_wb_cyc)&&(
|
((i_wb_stb)&&(~loading))
|
((i_wb_stb)&&(~loading))
|
||(i_wb_ctrl_stb));
|
||(i_wb_ctrl_stb));
|
reg ctrl;
|
reg ctrl;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
ctrl <= i_wb_ctrl_stb;
|
ctrl <= i_wb_ctrl_stb;
|
assign o_wb_data = (ctrl)?({cache_base[31:1],loading}):cache_data;
|
assign o_wb_data = (ctrl)?({cache_base[31:1],loading}):cache_data;
|
assign o_wb_stall = (loading)&&(~o_wb_ack);
|
assign o_wb_stall = (loading)&&(~o_wb_ack);
|
|
|
endmodule
|
endmodule
|
|
|
