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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [wbdmac.v] - Diff between revs 36 and 48

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Rev 36 Rev 48
Line 111... Line 111...
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
                i_dev_ints,
                i_dev_ints,
                o_interrupt,
                o_interrupt,
                i_other_busmaster_requests_bus);
                i_other_busmaster_requests_bus);
        parameter       LGMEMLEN = 10, DW=32, LGDV=5;
        parameter       ADDRESS_WIDTH=32, LGMEMLEN = 10,
 
                        DW=32, LGDV=5,AW=ADDRESS_WIDTH;
        input                   i_clk;
        input                   i_clk;
        // Slave/control wishbone inputs
        // Slave/control wishbone inputs
        input                   i_swb_cyc, i_swb_stb, i_swb_we;
        input                   i_swb_cyc, i_swb_stb, i_swb_we;
        input   [1:0]            i_swb_addr;
        input   [1:0]            i_swb_addr;
        input   [(DW-1):0]       i_swb_data;
        input   [(DW-1):0]       i_swb_data;
Line 123... Line 124...
        output  reg             o_swb_ack;
        output  reg             o_swb_ack;
        output  wire            o_swb_stall;
        output  wire            o_swb_stall;
        output  reg [(DW-1):0]   o_swb_data;
        output  reg [(DW-1):0]   o_swb_data;
        // Master/DMA wishbone control
        // Master/DMA wishbone control
        output  reg             o_mwb_cyc, o_mwb_stb, o_mwb_we;
        output  reg             o_mwb_cyc, o_mwb_stb, o_mwb_we;
        output  reg [(DW-1):0]   o_mwb_addr, o_mwb_data;
        output  reg [(AW-1):0]   o_mwb_addr;
 
        output  reg [(DW-1):0]   o_mwb_data;
        // Master/DMA wishbone responses from the bus
        // Master/DMA wishbone responses from the bus
        input                   i_mwb_ack, i_mwb_stall;
        input                   i_mwb_ack, i_mwb_stall;
        input   [(DW-1):0]       i_mwb_data;
        input   [(DW-1):0]       i_mwb_data;
        input                   i_mwb_err;
        input                   i_mwb_err;
        // The interrupt device interrupt lines
        // The interrupt device interrupt lines
Line 138... Line 140...
        input                   i_other_busmaster_requests_bus;
        input                   i_other_busmaster_requests_bus;
 
 
 
 
        reg                     cfg_wp; // Write protect
        reg                     cfg_wp; // Write protect
        reg                     cfg_err;
        reg                     cfg_err;
        reg     [(DW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
        reg     [(AW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
        reg [(LGMEMLEN-1):0]     cfg_blocklen_sub_one;
        reg [(LGMEMLEN-1):0]     cfg_blocklen_sub_one;
        reg                     cfg_incs, cfg_incd;
        reg                     cfg_incs, cfg_incd;
        reg     [(LGDV-1):0]     cfg_dev_trigger;
        reg     [(LGDV-1):0]     cfg_dev_trigger;
        reg                     cfg_on_dev_trigger;
        reg                     cfg_on_dev_trigger;
 
 
        // Single block operations: We'll read, then write, up to a single
        // Single block operations: We'll read, then write, up to a single
        // memory block here.
        // memory block here.
 
 
        reg     [(DW-1):0]       dma_mem [0:(((1<<LGMEMLEN))-1)];
        reg     [(DW-1):0]       dma_mem [0:(((1<<LGMEMLEN))-1)];
        reg     [(LGMEMLEN):0]   nread, nwritten, nacks;
        reg     [(LGMEMLEN):0]   nread, nwritten, nacks;
        wire    [(DW-1):0]       bus_nacks;
        wire    [(AW-1):0]       bus_nacks;
        assign  bus_nacks = { {(DW-LGMEMLEN-1){1'b0}}, nacks };
        assign  bus_nacks = { {(AW-LGMEMLEN-1){1'b0}}, nacks };
 
 
        initial o_interrupt = 1'b0;
        initial o_interrupt = 1'b0;
        initial o_mwb_cyc   = 1'b0;
        initial o_mwb_cyc   = 1'b0;
        initial cfg_err     = 1'b0;
        initial cfg_err     = 1'b0;
        initial cfg_wp      = 1'b0;
        initial cfg_wp      = 1'b0;
        initial cfg_len     = 32'h00;
        initial cfg_len     = {(AW){1'b0}};
        initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
        initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
        initial cfg_on_dev_trigger = 1'b0;
        initial cfg_on_dev_trigger = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
                if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
                begin
                begin
Line 269... Line 271...
                                        cfg_on_dev_trigger <= i_swb_data[15];
                                        cfg_on_dev_trigger <= i_swb_data[15];
                                        cfg_incs  <= ~i_swb_data[29];
                                        cfg_incs  <= ~i_swb_data[29];
                                        cfg_incd  <= ~i_swb_data[28];
                                        cfg_incd  <= ~i_swb_data[28];
                                        cfg_err   <= 1'b0;
                                        cfg_err   <= 1'b0;
                                        end
                                        end
                                2'b01: cfg_len   <=  i_swb_data;
                                2'b01: cfg_len   <=  i_swb_data[(AW-1):0];
                                2'b10: cfg_raddr <=  i_swb_data;
                                2'b10: cfg_raddr <=  i_swb_data[(AW-1):0];
                                2'b11: cfg_waddr <=  i_swb_data;
                                2'b11: cfg_waddr <=  i_swb_data[(AW-1):0];
                                endcase
                                endcase
                        end
                        end
                end
                end
 
 
        //
        //
Line 309... Line 311...
                                        ~cfg_incs, ~cfg_incd,
                                        ~cfg_incs, ~cfg_incd,
                                        1'b0, nread,
                                        1'b0, nread,
                                        cfg_on_dev_trigger, cfg_dev_trigger,
                                        cfg_on_dev_trigger, cfg_dev_trigger,
                                        cfg_blocklen_sub_one
                                        cfg_blocklen_sub_one
                                        };
                                        };
                2'b01: o_swb_data <= cfg_len;
                2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len  };
                2'b10: o_swb_data <= cfg_raddr;
                2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr};
                2'b11: o_swb_data <= cfg_waddr;
                2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr};
                endcase
                endcase
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_swb_cyc)&&(i_swb_stb)) // &&(~i_swb_we))
                if ((i_swb_cyc)&&(i_swb_stb)) // &&(~i_swb_we))
                        o_swb_ack <= 1'b1;
                        o_swb_ack <= 1'b1;

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