| Line 111... |
Line 111... |
o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
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o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
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i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
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i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
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i_dev_ints,
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i_dev_ints,
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o_interrupt,
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o_interrupt,
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i_other_busmaster_requests_bus);
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i_other_busmaster_requests_bus);
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parameter LGMEMLEN = 10, DW=32, LGDV=5;
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parameter ADDRESS_WIDTH=32, LGMEMLEN = 10,
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DW=32, LGDV=5,AW=ADDRESS_WIDTH;
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input i_clk;
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input i_clk;
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// Slave/control wishbone inputs
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// Slave/control wishbone inputs
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input i_swb_cyc, i_swb_stb, i_swb_we;
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input i_swb_cyc, i_swb_stb, i_swb_we;
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input [1:0] i_swb_addr;
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input [1:0] i_swb_addr;
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input [(DW-1):0] i_swb_data;
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input [(DW-1):0] i_swb_data;
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| Line 123... |
Line 124... |
output reg o_swb_ack;
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output reg o_swb_ack;
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output wire o_swb_stall;
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output wire o_swb_stall;
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output reg [(DW-1):0] o_swb_data;
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output reg [(DW-1):0] o_swb_data;
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// Master/DMA wishbone control
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// Master/DMA wishbone control
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output reg o_mwb_cyc, o_mwb_stb, o_mwb_we;
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output reg o_mwb_cyc, o_mwb_stb, o_mwb_we;
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output reg [(DW-1):0] o_mwb_addr, o_mwb_data;
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output reg [(AW-1):0] o_mwb_addr;
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output reg [(DW-1):0] o_mwb_data;
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// Master/DMA wishbone responses from the bus
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// Master/DMA wishbone responses from the bus
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input i_mwb_ack, i_mwb_stall;
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input i_mwb_ack, i_mwb_stall;
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input [(DW-1):0] i_mwb_data;
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input [(DW-1):0] i_mwb_data;
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input i_mwb_err;
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input i_mwb_err;
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// The interrupt device interrupt lines
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// The interrupt device interrupt lines
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| Line 138... |
Line 140... |
input i_other_busmaster_requests_bus;
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input i_other_busmaster_requests_bus;
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reg cfg_wp; // Write protect
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reg cfg_wp; // Write protect
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reg cfg_err;
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reg cfg_err;
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reg [(DW-1):0] cfg_waddr, cfg_raddr, cfg_len;
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reg [(AW-1):0] cfg_waddr, cfg_raddr, cfg_len;
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reg [(LGMEMLEN-1):0] cfg_blocklen_sub_one;
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reg [(LGMEMLEN-1):0] cfg_blocklen_sub_one;
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reg cfg_incs, cfg_incd;
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reg cfg_incs, cfg_incd;
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reg [(LGDV-1):0] cfg_dev_trigger;
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reg [(LGDV-1):0] cfg_dev_trigger;
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reg cfg_on_dev_trigger;
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reg cfg_on_dev_trigger;
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// Single block operations: We'll read, then write, up to a single
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// Single block operations: We'll read, then write, up to a single
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// memory block here.
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// memory block here.
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reg [(DW-1):0] dma_mem [0:(((1<<LGMEMLEN))-1)];
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reg [(DW-1):0] dma_mem [0:(((1<<LGMEMLEN))-1)];
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reg [(LGMEMLEN):0] nread, nwritten, nacks;
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reg [(LGMEMLEN):0] nread, nwritten, nacks;
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wire [(DW-1):0] bus_nacks;
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wire [(AW-1):0] bus_nacks;
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assign bus_nacks = { {(DW-LGMEMLEN-1){1'b0}}, nacks };
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assign bus_nacks = { {(AW-LGMEMLEN-1){1'b0}}, nacks };
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initial o_interrupt = 1'b0;
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initial o_interrupt = 1'b0;
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initial o_mwb_cyc = 1'b0;
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initial o_mwb_cyc = 1'b0;
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initial cfg_err = 1'b0;
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initial cfg_err = 1'b0;
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initial cfg_wp = 1'b0;
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initial cfg_wp = 1'b0;
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initial cfg_len = 32'h00;
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initial cfg_len = {(AW){1'b0}};
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initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
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initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
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initial cfg_on_dev_trigger = 1'b0;
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initial cfg_on_dev_trigger = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
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if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
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begin
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begin
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| Line 269... |
Line 271... |
cfg_on_dev_trigger <= i_swb_data[15];
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cfg_on_dev_trigger <= i_swb_data[15];
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cfg_incs <= ~i_swb_data[29];
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cfg_incs <= ~i_swb_data[29];
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cfg_incd <= ~i_swb_data[28];
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cfg_incd <= ~i_swb_data[28];
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cfg_err <= 1'b0;
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cfg_err <= 1'b0;
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end
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end
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2'b01: cfg_len <= i_swb_data;
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2'b01: cfg_len <= i_swb_data[(AW-1):0];
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2'b10: cfg_raddr <= i_swb_data;
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2'b10: cfg_raddr <= i_swb_data[(AW-1):0];
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2'b11: cfg_waddr <= i_swb_data;
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2'b11: cfg_waddr <= i_swb_data[(AW-1):0];
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endcase
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endcase
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end
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end
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end
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end
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//
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//
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| Line 309... |
Line 311... |
~cfg_incs, ~cfg_incd,
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~cfg_incs, ~cfg_incd,
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1'b0, nread,
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1'b0, nread,
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cfg_on_dev_trigger, cfg_dev_trigger,
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cfg_on_dev_trigger, cfg_dev_trigger,
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cfg_blocklen_sub_one
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cfg_blocklen_sub_one
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};
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};
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2'b01: o_swb_data <= cfg_len;
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2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len };
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2'b10: o_swb_data <= cfg_raddr;
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2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr};
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2'b11: o_swb_data <= cfg_waddr;
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2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr};
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endcase
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endcase
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_swb_cyc)&&(i_swb_stb)) // &&(~i_swb_we))
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if ((i_swb_cyc)&&(i_swb_stb)) // &&(~i_swb_we))
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o_swb_ack <= 1'b1;
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o_swb_ack <= 1'b1;
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