OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [zipcounter.v] - Diff between revs 69 and 160

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 69 Rev 160
Line 25... Line 25...
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
Line 59... Line 59...
        output  wire                    o_wb_stall;
        output  wire                    o_wb_stall;
        output  reg     [(BW-1):0]       o_wb_data;
        output  reg     [(BW-1):0]       o_wb_data;
        // Interrupt line
        // Interrupt line
        output  reg                     o_int;
        output  reg                     o_int;
 
 
 
        initial o_int = 0;
        initial o_wb_data = 32'h00;
        initial o_wb_data = 32'h00;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
                        o_wb_data <= i_wb_data;
                        { o_int, o_wb_data } <= { 1'b0, i_wb_data };
                else if (i_ce)
                else if (i_ce)
                        o_wb_data <= o_wb_data + 1;
                        { o_int, o_wb_data } <= o_wb_data+{{(BW-1){1'b0}},1'b1};
 
 
        initial o_int = 0;
 
        always @(posedge i_clk)
 
                if (i_ce)
 
                        o_int <= &o_wb_data;
 
                else
                else
                        o_int <= 1'b0;
                        o_int <= 1'b0;
 
 
        initial o_wb_ack = 1'b0;
        initial o_wb_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.