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Line 25... |
// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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Line 59... |
output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [(BW-1):0] o_wb_data;
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output reg [(BW-1):0] o_wb_data;
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// Interrupt line
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// Interrupt line
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output reg o_int;
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output reg o_int;
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initial o_int = 0;
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initial o_wb_data = 32'h00;
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initial o_wb_data = 32'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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o_wb_data <= i_wb_data;
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{ o_int, o_wb_data } <= { 1'b0, i_wb_data };
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else if (i_ce)
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else if (i_ce)
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o_wb_data <= o_wb_data + 1;
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{ o_int, o_wb_data } <= o_wb_data+{{(BW-1){1'b0}},1'b1};
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initial o_int = 0;
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always @(posedge i_clk)
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if (i_ce)
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o_int <= &o_wb_data;
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else
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else
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o_int <= 1'b0;
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o_int <= 1'b0;
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initial o_wb_ack = 1'b0;
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initial o_wb_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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