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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [zipjiffies.v] - Diff between revs 69 and 160

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Rev 69 Rev 160
Line 43... Line 43...
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
Line 65... Line 65...
//
//
module  zipjiffies(i_clk, i_ce,
module  zipjiffies(i_clk, i_ce,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                o_int);
                o_int);
        parameter       BW = 32, VW = (BW-2);
        parameter       BW = 32;
        input                           i_clk, i_ce;
        input                           i_clk, i_ce;
        // Wishbone inputs
        // Wishbone inputs
        input                           i_wb_cyc, i_wb_stb, i_wb_we;
        input                           i_wb_cyc, i_wb_stb, i_wb_we;
        input           [(BW-1):0]       i_wb_data;
        input           [(BW-1):0]       i_wb_data;
        // Wishbone outputs
        // Wishbone outputs
Line 102... Line 102...
        assign  till_when = int_when-r_counter;
        assign  till_when = int_when-r_counter;
        assign  till_wb   = new_when-r_counter;
        assign  till_wb   = new_when-r_counter;
 
 
        initial new_set = 1'b0;
        initial new_set = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                // Delay things by a clock to simplify our logic
 
                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
 
                begin
                begin
                        new_set <= 1'b1;
                // Delay things by a clock to simplify our logic
 
                new_set <= ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
 
                // new_when is a don't care when new_set = 0, so don't worry
 
                // about setting it at all times.
                        new_when<= i_wb_data;
                        new_when<= i_wb_data;
                end else
        end
                        new_set <= 1'b0;
 
 
 
        initial o_int   = 1'b0;
        initial o_int   = 1'b0;
        initial int_set = 1'b0;
        initial int_set = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                o_int <= 1'b0;
                o_int <= 1'b0;
                if ((i_ce)&&(int_set)&&(r_counter == int_when))
                if ((i_ce)&&(int_set)&&(r_counter == int_when))
                begin // Interrupts are self-clearing
                        // Interrupts are self-clearing
                        o_int <= 1'b1;  // Set the interrupt flag
                        o_int <= 1'b1;  // Set the interrupt flag for one clock
                        int_set <= 1'b0;// Clear the interrupt
                else if ((new_set)&&(till_wb <= 0))
                end
                        o_int <= 1'b1;
 
 
 
                if ((new_set)&&(till_wb > 0))
 
                        int_set <= 1'b1;
 
                else if ((i_ce)&&(r_counter == int_when))
 
                        int_set <= 1'b0;
 
 
                if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
                if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
                begin
 
                        int_when <= new_when;
                        int_when <= new_when;
                        int_set <= ((int_set)||(till_wb>0));
 
                end
 
        end
        end
 
 
        //
        //
        // Acknowledge any wishbone accesses -- everything we did took only
        // Acknowledge any wishbone accesses -- everything we did took only
        // one clock anyway.
        // one clock anyway.

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