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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [zipjiffies.v] - Diff between revs 2 and 9

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Rev 2 Rev 9
Line 99... Line 99...
        reg                             int_set,  new_set;
        reg                             int_set,  new_set;
        reg             [(BW-1):0]       int_when, new_when;
        reg             [(BW-1):0]       int_when, new_when;
        wire    signed  [(BW-1):0]       till_when, till_wb;
        wire    signed  [(BW-1):0]       till_when, till_wb;
        assign  till_when = int_when-r_counter;
        assign  till_when = int_when-r_counter;
        assign  till_wb   = new_when-r_counter;
        assign  till_wb   = new_when-r_counter;
 
 
 
        initial new_set = 1'b0;
 
        always @(posedge i_clk)
 
                // Delay things by a clock to simplify our logic
 
                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
 
                begin
 
                        new_set <= 1'b1;
 
                        new_when<= i_wb_data;
 
                end else
 
                        new_set <= 1'b0;
 
 
        initial o_int   = 1'b0;
        initial o_int   = 1'b0;
        initial int_set = 1'b0;
        initial int_set = 1'b0;
        initial new_set = 1'b0;
 
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                o_int <= 1'b0;
                o_int <= 1'b0;
                if ((i_ce)&&(int_set)&&(r_counter == int_when))
                if ((i_ce)&&(int_set)&&(r_counter == int_when))
                begin // Interrupts are self-clearing
                begin // Interrupts are self-clearing
                        o_int <= 1'b1;  // Set the interrupt flag
                        o_int <= 1'b1;  // Set the interrupt flag
                        int_set <= 1'b0;// Clear the interrupt
                        int_set <= 1'b0;// Clear the interrupt
                end
                end
 
 
                new_set <= 1'b0;
 
                if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
                if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
                begin
                begin
                        int_when <= new_when;
                        int_when <= new_when;
                        int_set <= ((int_set)||(till_wb>0));
                        int_set <= ((int_set)||(till_wb>0));
                end
                end
 
 
                // Delay things by a clock to simplify our logic
 
                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
 
                begin
 
                        new_set <= 1'b1;
 
                        new_when<= i_wb_data;
 
                end
 
        end
        end
 
 
        //
        //
        // Acknowledge any wishbone accesses -- everything we did took only
        // Acknowledge any wishbone accesses -- everything we did took only
        // one clock anyway.
        // one clock anyway.
        //
        //
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
                o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
 
 
        assign  o_wb_data = r_counter;
        assign  o_wb_data = r_counter;
        assign  o_wb_stall = 1'b0;
        assign  o_wb_stall = 1'b0;
 
 
endmodule
endmodule
 
 
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