////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: zipjiffies.v
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// Filename: zipjiffies.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: This peripheral is motivated by the Linux use of 'jiffies'.
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// Purpose: This peripheral is motivated by the Linux use of 'jiffies'.
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// A process, in Linux, can request to be put to sleep until a certain
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// A process, in Linux, can request to be put to sleep until a certain
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// number of 'jiffies' have elapsed. Using this interface, the CPU can
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// number of 'jiffies' have elapsed. Using this interface, the CPU can
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// read the number of 'jiffies' from this peripheral (it only has the
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// read the number of 'jiffies' from this peripheral (it only has the
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// one location in address space), add the sleep length to it, and
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// one location in address space), add the sleep length to it, and
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// write the result back to the peripheral. The zipjiffies peripheral
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// write the result back to the peripheral. The zipjiffies peripheral
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// will record the value written to it only if it is nearer the current
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// will record the value written to it only if it is nearer the current
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// counter value than the last current waiting interrupt time. If no
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// counter value than the last current waiting interrupt time. If no
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// other interrupts are waiting, and this time is in the future, it will
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// other interrupts are waiting, and this time is in the future, it will
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// be enabled. (There is currrently no way to disable a jiffie interrupt
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// be enabled. (There is currrently no way to disable a jiffie interrupt
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// once set.) The processor may then place this sleep request into a
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// once set.) The processor may then place this sleep request into a
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// list among other sleep requests. Once the timer expires, it would
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// list among other sleep requests. Once the timer expires, it would
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// write the next jiffy request to the peripheral and wake up the process
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// write the next jiffy request to the peripheral and wake up the process
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// whose timer had expired.
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// whose timer had expired.
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//
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//
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// Quite elementary, really.
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// Quite elementary, really.
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//
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//
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// Interface:
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// Interface:
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// This peripheral contains one register: a counter. Reads from the
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// This peripheral contains one register: a counter. Reads from the
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// register return the current value of the counter. Writes within
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// register return the current value of the counter. Writes within
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// the (N-1) bit space following the current time set an interrupt.
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// the (N-1) bit space following the current time set an interrupt.
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// Writes of values that occurred in the last 2^(N-1) ticks will be
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// Writes of values that occurred in the last 2^(N-1) ticks will be
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// ignored. The timer then interrupts when it's value equals that time.
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// ignored. The timer then interrupts when it's value equals that time.
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// Multiple writes cause the jiffies timer to select the nearest possible
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// Multiple writes cause the jiffies timer to select the nearest possible
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// interrupt. Upon an interrupt, the next interrupt time/value is cleared
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// interrupt. Upon an interrupt, the next interrupt time/value is cleared
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// and will need to be reset if the CPU wants to get notified again. With
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// and will need to be reset if the CPU wants to get notified again. With
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// only the single interface, there is no way of knowing when the next
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// only the single interface, there is no way of knowing when the next
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// interrupt is scheduled for, neither is there any way to slow down the
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// interrupt is scheduled for, neither is there any way to slow down the
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// interrupt timer in case you don't want it overflowing as often and you
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// interrupt timer in case you don't want it overflowing as often and you
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// wish to wait more jiffies than it supports. Thus, currently, if you
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// wish to wait more jiffies than it supports. Thus, currently, if you
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// have a timer you wish to wait upon that is more than 2^31 into the
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// have a timer you wish to wait upon that is more than 2^31 into the
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// future, you would need to set timers along the way, wake up on those
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// future, you would need to set timers along the way, wake up on those
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// timers, and set further timer's until you finally get to your
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// timers, and set further timer's until you finally get to your
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// destination.
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// destination.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Tecnology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module zipjiffies(i_clk, i_ce,
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module zipjiffies(i_clk, i_ce,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_int);
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o_int);
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parameter BW = 32, VW = (BW-2);
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parameter BW = 32, VW = (BW-2);
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input i_clk, i_ce;
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input i_clk, i_ce;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [(BW-1):0] i_wb_data;
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input [(BW-1):0] i_wb_data;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output wire [(BW-1):0] o_wb_data;
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output wire [(BW-1):0] o_wb_data;
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// Interrupt line
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// Interrupt line
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output reg o_int;
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output reg o_int;
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//
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//
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// Our counter logic: The counter is always counting up--it cannot
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// Our counter logic: The counter is always counting up--it cannot
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// be stopped or altered. It's really quite simple. Okay, not quite.
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// be stopped or altered. It's really quite simple. Okay, not quite.
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// We still support the clock enable line. We do this in order to
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// We still support the clock enable line. We do this in order to
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// support debugging, so that if we get everything running inside a
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// support debugging, so that if we get everything running inside a
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// debugger, the timer's all slow down so that everything can be stepped
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// debugger, the timer's all slow down so that everything can be stepped
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// together, one clock at a time.
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// together, one clock at a time.
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//
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//
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reg [(BW-1):0] r_counter;
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reg [(BW-1):0] r_counter;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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r_counter <= r_counter+1;
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r_counter <= r_counter+1;
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//
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//
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// Writes to the counter set an interrupt--but only if they are in the
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// Writes to the counter set an interrupt--but only if they are in the
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// future as determined by the signed result of an unsigned subtract.
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// future as determined by the signed result of an unsigned subtract.
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//
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//
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reg int_set, new_set;
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reg int_set, new_set;
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reg [(BW-1):0] int_when, new_when;
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reg [(BW-1):0] int_when, new_when;
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wire signed [(BW-1):0] till_when, till_wb;
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wire signed [(BW-1):0] till_when, till_wb;
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assign till_when = int_when-r_counter;
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assign till_when = int_when-r_counter;
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assign till_wb = new_when-r_counter;
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assign till_wb = new_when-r_counter;
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initial new_set = 1'b0;
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always @(posedge i_clk)
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// Delay things by a clock to simplify our logic
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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begin
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new_set <= 1'b1;
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new_when<= i_wb_data;
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end else
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new_set <= 1'b0;
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initial o_int = 1'b0;
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initial o_int = 1'b0;
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initial int_set = 1'b0;
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initial int_set = 1'b0;
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initial new_set = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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o_int <= 1'b0;
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o_int <= 1'b0;
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if ((i_ce)&&(int_set)&&(r_counter == int_when))
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if ((i_ce)&&(int_set)&&(r_counter == int_when))
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begin // Interrupts are self-clearing
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begin // Interrupts are self-clearing
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o_int <= 1'b1; // Set the interrupt flag
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o_int <= 1'b1; // Set the interrupt flag
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int_set <= 1'b0;// Clear the interrupt
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int_set <= 1'b0;// Clear the interrupt
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end
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end
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new_set <= 1'b0;
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if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
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if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
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begin
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begin
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int_when <= new_when;
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int_when <= new_when;
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int_set <= ((int_set)||(till_wb>0));
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int_set <= ((int_set)||(till_wb>0));
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end
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end
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// Delay things by a clock to simplify our logic
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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begin
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new_set <= 1'b1;
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new_when<= i_wb_data;
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end
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end
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end
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//
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//
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// Acknowledge any wishbone accesses -- everything we did took only
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// Acknowledge any wishbone accesses -- everything we did took only
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// one clock anyway.
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// one clock anyway.
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//
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//
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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assign o_wb_data = r_counter;
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assign o_wb_data = r_counter;
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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endmodule
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endmodule
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