///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: ziptimer.v
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// Filename: ziptimer.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: A lighter weight implementation of the Zip Timer.
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// Purpose: A lighter weight implementation of the Zip Timer.
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//
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//
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// Interface:
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// Interface:
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// Two options:
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// Two options:
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// 1. One combined register for both control and value, and ...
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// 1. One combined register for both control and value, and ...
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// The reload value is set any time the timer data value is "set".
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// The reload value is set any time the timer data value is "set".
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// Reading the register returns the timer value. Controls are
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// Reading the register returns the timer value. Controls are
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// set so that writing a value to the timer automatically starts
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// set so that writing a value to the timer automatically starts
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// it counting down.
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// it counting down.
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// 2. Two registers, one for control one for value.
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// 2. Two registers, one for control one for value.
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// The control register would have the reload value in it.
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// The control register would have the reload value in it.
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// On the clock when the interface is set to zero the interrupt is set.
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// On the clock when the interface is set to zero the interrupt is set.
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// Hence setting the timer to zero will disable the timer without
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// Hence setting the timer to zero will disable the timer without
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// setting any interrupts. Thus setting it to five will count
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// setting any interrupts. Thus setting it to five will count
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// 5 clocks: 5, 4, 3, 2, 1, Interrupt.
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// 5 clocks: 5, 4, 3, 2, 1, Interrupt.
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//
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//
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//
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//
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// Control bits:
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// Control bits:
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// (Start_n/Stop. This bit has been dropped. Writing to this
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// (Start_n/Stop. This bit has been dropped. Writing to this
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// timer any value but zero starts it. Writing a zero
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// timer any value but zero starts it. Writing a zero
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// clears and stops it.)
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// clears and stops it.)
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// AutoReload. If set, then on reset the timer automatically
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// AutoReload. If set, then on reset the timer automatically
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// loads the last set value and starts over. This is
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// loads the last set value and starts over. This is
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// useful for distinguishing between a one-time interrupt
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// useful for distinguishing between a one-time interrupt
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// timer, and a repetitive interval timer.
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// timer, and a repetitive interval timer.
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// (INTEN. Interrupt enable--reaching zero always creates an
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// (INTEN. Interrupt enable--reaching zero always creates an
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// interrupt, so this control bit isn't needed. The
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// interrupt, so this control bit isn't needed. The
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// interrupt controller can be used to mask the interrupt.)
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// interrupt controller can be used to mask the interrupt.)
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// (COUNT-DOWN/UP: This timer is *only* a count-down timer.
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// (COUNT-DOWN/UP: This timer is *only* a count-down timer.
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// There is no means of setting it to count up.)
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// There is no means of setting it to count up.)
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// WatchDog
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// WatchDog
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// This timer can be implemented as a watchdog timer simply by
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// This timer can be implemented as a watchdog timer simply by
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// connecting the interrupt line to the reset line of the CPU.
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// connecting the interrupt line to the reset line of the CPU.
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// When the timer then expires, it will trigger a CPU reset.
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// When the timer then expires, it will trigger a CPU reset.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Tecnology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module ziptimer(i_clk, i_rst, i_ce,
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module ziptimer(i_clk, i_rst, i_ce,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_int);
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o_int);
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parameter BW = 32, VW = (BW-1);
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parameter BW = 32, VW = (BW-1);
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input i_clk, i_rst, i_ce;
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input i_clk, i_rst, i_ce;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [(BW-1):0] i_wb_data;
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input [(BW-1):0] i_wb_data;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output wire [(BW-1):0] o_wb_data;
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output wire [(BW-1):0] o_wb_data;
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// Interrupt line
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// Interrupt line
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output reg o_int;
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output reg o_int;
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reg r_auto_reload, r_running;
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reg r_auto_reload, r_running;
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reg [(VW-1):0] r_reload_value;
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reg [(VW-1):0] r_reload_value;
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wire wb_write;
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wire wb_write;
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assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
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assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
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initial r_running = 1'b0;
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initial r_running = 1'b0;
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initial r_auto_reload = 1'b0;
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initial r_auto_reload = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_running <= 1'b0;
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r_running <= 1'b0;
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else if (wb_write)
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else if (wb_write)
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r_running <= (|i_wb_data[(VW-1):0]);
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r_running <= (|i_wb_data[(VW-1):0]);
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else if ((o_int)&&(~r_auto_reload))
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else if ((o_int)&&(~r_auto_reload))
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r_running <= 1'b0;
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r_running <= 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wb_write)
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if (wb_write)
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r_auto_reload <= (i_wb_data[(BW-1)]);
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r_auto_reload <= (i_wb_data[(BW-1)]);
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// If setting auto-reload mode, and the value to other
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// If setting auto-reload mode, and the value to other
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// than zero, set the auto-reload value
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// than zero, set the auto-reload value
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
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if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
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r_reload_value <= i_wb_data[(VW-1):0];
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r_reload_value <= i_wb_data[(VW-1):0];
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reg [(VW-1):0] r_value;
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reg [(VW-1):0] r_value;
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initial r_value = 0;
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initial r_value = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wb_write)
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if (wb_write)
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r_value <= i_wb_data[(VW-1):0];
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r_value <= i_wb_data[(VW-1):0];
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else if ((r_running)&&(i_ce)&&(~o_int))
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else if ((r_running)&&(i_ce)&&(~o_int))
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r_value <= r_value - 1;
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r_value <= r_value + {(VW){1'b1}}; // r_value - 1;
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else if ((r_running)&&(r_auto_reload)&&(o_int))
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else if ((r_running)&&(r_auto_reload)&&(o_int))
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r_value <= r_reload_value;
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r_value <= r_reload_value;
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// Set the interrupt on our last tick.
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// Set the interrupt on our last tick.
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initial o_int = 1'b0;
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initial o_int = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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o_int <= (r_running)&&(r_value == { {(VW-1){1'b0}}, 1'b1 });
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o_int <= (r_running)&&(r_value == { {(VW-1){1'b0}}, 1'b1 });
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else
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else
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o_int <= 1'b0;
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o_int <= 1'b0;
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initial o_wb_ack = 1'b0;
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initial o_wb_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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assign o_wb_data = { r_auto_reload, r_value };
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assign o_wb_data = { r_auto_reload, r_value };
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endmodule
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endmodule
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