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[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Diff between revs 105 and 183

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Rev 105 Rev 183
Line 47... Line 47...
`ifdef  DEBUG_SCOPE
`ifdef  DEBUG_SCOPE
                , o_zip_debug
                , o_zip_debug
`endif
`endif
                );
                );
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
                        LGICACHE=6, START_HALTED=0,
                        LGICACHE=8, START_HALTED=0,
                        AW=ADDRESS_WIDTH;
                        AW=ADDRESS_WIDTH;
        input   i_clk, i_rst;
        input   i_clk, i_rst;
        // Wishbone master
        // Wishbone master
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire    [(AW-1):0]       o_wb_addr;
        output  wire    [(AW-1):0]       o_wb_addr;

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