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[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Diff between revs 183 and 201

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///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    zipbones.v
// Filename:    zipbones.v
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
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//              need to be implemented off-module.
//              need to be implemented off-module.
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, 2017, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
 
// You should have received a copy of the GNU General Public License along
 
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
 
// target there if the PDF file isn't present.)  If not, see
 
// <http://www.gnu.org/licenses/> for a copy.
 
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
 
//
//
//
`include "cpudefs.v"
`include "cpudefs.v"
//
//
module  zipbones(i_clk, i_rst,
module  zipbones(i_clk, i_rst,
                // Wishbone master interface from the CPU
                // Wishbone master interface from the CPU
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
                // Incoming interrupts
                // Incoming interrupts
                i_ext_int,
                i_ext_int,
                // Our one outgoing interrupt
                // Our one outgoing interrupt
                o_ext_int,
                o_ext_int,
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                        o_dbg_ack, o_dbg_stall, o_dbg_data
                        o_dbg_ack, o_dbg_stall, o_dbg_data
`ifdef  DEBUG_SCOPE
`ifdef  DEBUG_SCOPE
                , o_zip_debug
                , o_zip_debug
`endif
`endif
                );
                );
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=30,
                        LGICACHE=8, START_HALTED=0,
                        LGICACHE=8, START_HALTED=0;
                        AW=ADDRESS_WIDTH;
        localparam      AW=ADDRESS_WIDTH;
        input   i_clk, i_rst;
        input   i_clk, i_rst;
        // Wishbone master
        // Wishbone master
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire    [(AW-1):0]       o_wb_addr;
        output  wire    [(AW-1):0]       o_wb_addr;
        output  wire    [31:0]   o_wb_data;
        output  wire    [31:0]   o_wb_data;
 
        output  wire    [3:0]    o_wb_sel;
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
        input                   i_wb_err;
        input                   i_wb_err;
        // Incoming interrupts
        // Incoming interrupts
        input                   i_ext_int;
        input                   i_ext_int;
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                        cpu_op_stall, cpu_pf_stall, cpu_i_count;
                        cpu_op_stall, cpu_pf_stall, cpu_i_count;
        wire    [31:0]   cpu_data;
        wire    [31:0]   cpu_data;
        wire    [31:0]   cpu_dbg_data;
        wire    [31:0]   cpu_dbg_data;
        assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
        assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
                                        &&(i_dbg_we)&&(i_dbg_addr));
                                        &&(i_dbg_we)&&(i_dbg_addr));
        zipcpu  #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
        zipcpu  #(.RESET_ADDRESS(RESET_ADDRESS),
 
                        .ADDRESS_WIDTH(ADDRESS_WIDTH),
 
                        .LGICACHE(LGICACHE),
 
                        .WITH_LOCAL_BUS(0))
                thecpu(i_clk, cpu_reset, i_ext_int,
                thecpu(i_clk, cpu_reset, i_ext_int,
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
                                i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
                                i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
                                cpu_dbg_cc, cpu_break,
                                cpu_dbg_cc, cpu_break,
                        o_wb_cyc, o_wb_stb,
                        o_wb_cyc, o_wb_stb,
                                cpu_lcl_cyc, cpu_lcl_stb,
                                cpu_lcl_cyc, cpu_lcl_stb,
                                o_wb_we, o_wb_addr, o_wb_data,
                                o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
                                i_wb_ack, i_wb_stall, i_wb_data,
                                i_wb_ack, i_wb_stall, i_wb_data,
                                (i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)),
                                (i_wb_err)||(cpu_lcl_cyc),
                        cpu_op_stall, cpu_pf_stall, cpu_i_count
                        cpu_op_stall, cpu_pf_stall, cpu_i_count
`ifdef  DEBUG_SCOPE
`ifdef  DEBUG_SCOPE
                        , o_zip_debug
                        , o_zip_debug
`endif
`endif
                        );
                        );

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