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[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Diff between revs 38 and 48

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Rev 38 Rev 48
Line 40... Line 40...
                // Our one outgoing interrupt
                // Our one outgoing interrupt
                o_ext_int,
                o_ext_int,
                // Wishbone slave interface for debugging purposes
                // Wishbone slave interface for debugging purposes
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
        parameter       RESET_ADDRESS=32'h0100000, START_HALTED=1,
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
                        EXTERNAL_INTERRUPTS=1;
                        LGICACHE=6, START_HALTED=1,
 
                        AW=ADDRESS_WIDTH;
        input   i_clk, i_rst;
        input   i_clk, i_rst;
        // Wishbone master
        // Wishbone master
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire    [31:0]   o_wb_addr;
        output  wire    [(AW-1):0]       o_wb_addr;
        output  wire    [31:0]   o_wb_data;
        output  wire    [31:0]   o_wb_data;
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
        input                   i_wb_err;
        input                   i_wb_err;
        // Incoming interrupts
        // Incoming interrupts
        input           [(EXTERNAL_INTERRUPTS-1):0]      i_ext_int;
        input                   i_ext_int;
        // Outgoing interrupt
        // Outgoing interrupt
        output  wire            o_ext_int;
        output  wire            o_ext_int;
        // Wishbone slave
        // Wishbone slave
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
        input           [31:0]   i_dbg_data;
        input           [31:0]   i_dbg_data;
Line 66... Line 67...
        // 
        // 
        //
        //
        //
        //
        wire    sys_cyc, sys_stb, sys_we;
        wire    sys_cyc, sys_stb, sys_we;
        wire    [4:0]    sys_addr;
        wire    [4:0]    sys_addr;
        wire    [31:0]   cpu_addr;
        wire    [(AW-1):0]       cpu_addr;
        wire    [31:0]   sys_data;
        wire    [31:0]   sys_data;
        wire            sys_ack, sys_stall;
        wire            sys_ack, sys_stall;
 
 
        //
        //
        // The external debug interface
        // The external debug interface
Line 136... Line 137...
        //      0x00400 -> cmd_halt
        //      0x00400 -> cmd_halt
        //      0x00800 -> cmd_clear_pf_cache
        //      0x00800 -> cmd_clear_pf_cache
        //      0x01000 -> cc.sleep
        //      0x01000 -> cc.sleep
        //      0x02000 -> cc.gie
        //      0x02000 -> cc.gie
        //      0x10000 -> External interrupt line is high
        //      0x10000 -> External interrupt line is high
        assign  cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
        assign  cmd_data = { 7'h00, 8'h00, i_ext_int,
                        2'b00, cpu_dbg_cc,
                        2'b00, cpu_dbg_cc,
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                        pic_data[15], cpu_reset, 1'b0, cmd_addr };
                        pic_data[15], cpu_reset, 1'b0, cmd_addr };
        wire    cpu_gie;
        wire    cpu_gie;
        assign  cpu_gie = cpu_dbg_cc[1];
        assign  cpu_gie = cpu_dbg_cc[1];
Line 154... Line 155...
        wire    [31:0]   cpu_data, wb_data;
        wire    [31:0]   cpu_data, wb_data;
        wire            cpu_ack, cpu_stall, cpu_err;
        wire            cpu_ack, cpu_stall, cpu_err;
        wire    [31:0]   cpu_dbg_data;
        wire    [31:0]   cpu_dbg_data;
        assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
        assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
                                        &&(i_dbg_we)&&(i_dbg_addr));
                                        &&(i_dbg_we)&&(i_dbg_addr));
        zipcpu  #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, i_ext_int,
        zipcpu  #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
 
                thecpu(i_clk, cpu_reset, i_ext_int,
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
                                i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
                                i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
                                cpu_dbg_cc, cpu_break,
                                cpu_dbg_cc, cpu_break,
                        o_wb_cyc, o_wb_stb,
                        o_wb_cyc, o_wb_stb,
                                cpu_lcl_cyc, cpu_lcl_stb,
                                cpu_lcl_cyc, cpu_lcl_stb,

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