| Line 40... |
Line 40... |
// Our one outgoing interrupt
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// Our one outgoing interrupt
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o_ext_int,
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o_ext_int,
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// Wishbone slave interface for debugging purposes
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// Wishbone slave interface for debugging purposes
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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o_dbg_ack, o_dbg_stall, o_dbg_data);
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o_dbg_ack, o_dbg_stall, o_dbg_data);
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parameter RESET_ADDRESS=32'h0100000, START_HALTED=1,
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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EXTERNAL_INTERRUPTS=1;
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LGICACHE=6, START_HALTED=1,
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AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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// Wishbone master
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// Wishbone master
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire [31:0] o_wb_addr;
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output wire [(AW-1):0] o_wb_addr;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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input i_wb_err;
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input i_wb_err;
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// Incoming interrupts
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// Incoming interrupts
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input [(EXTERNAL_INTERRUPTS-1):0] i_ext_int;
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input i_ext_int;
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// Outgoing interrupt
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// Outgoing interrupt
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output wire o_ext_int;
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output wire o_ext_int;
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// Wishbone slave
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// Wishbone slave
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input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
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input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
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input [31:0] i_dbg_data;
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input [31:0] i_dbg_data;
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| Line 66... |
Line 67... |
//
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//
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//
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//
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//
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//
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wire sys_cyc, sys_stb, sys_we;
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wire sys_cyc, sys_stb, sys_we;
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wire [4:0] sys_addr;
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wire [4:0] sys_addr;
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wire [31:0] cpu_addr;
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wire [(AW-1):0] cpu_addr;
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wire [31:0] sys_data;
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wire [31:0] sys_data;
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wire sys_ack, sys_stall;
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wire sys_ack, sys_stall;
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|
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//
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//
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// The external debug interface
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// The external debug interface
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| Line 136... |
Line 137... |
// 0x00400 -> cmd_halt
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// 0x00400 -> cmd_halt
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// 0x00800 -> cmd_clear_pf_cache
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// 0x00800 -> cmd_clear_pf_cache
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// 0x01000 -> cc.sleep
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// 0x01000 -> cc.sleep
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// 0x02000 -> cc.gie
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// 0x02000 -> cc.gie
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// 0x10000 -> External interrupt line is high
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// 0x10000 -> External interrupt line is high
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assign cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
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assign cmd_data = { 7'h00, 8'h00, i_ext_int,
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2'b00, cpu_dbg_cc,
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2'b00, cpu_dbg_cc,
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1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
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1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
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pic_data[15], cpu_reset, 1'b0, cmd_addr };
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pic_data[15], cpu_reset, 1'b0, cmd_addr };
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wire cpu_gie;
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wire cpu_gie;
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assign cpu_gie = cpu_dbg_cc[1];
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assign cpu_gie = cpu_dbg_cc[1];
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| Line 154... |
Line 155... |
wire [31:0] cpu_data, wb_data;
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wire [31:0] cpu_data, wb_data;
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wire cpu_ack, cpu_stall, cpu_err;
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wire cpu_ack, cpu_stall, cpu_err;
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wire [31:0] cpu_dbg_data;
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wire [31:0] cpu_dbg_data;
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assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
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assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
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&&(i_dbg_we)&&(i_dbg_addr));
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&&(i_dbg_we)&&(i_dbg_addr));
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zipcpu #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, i_ext_int,
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zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
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thecpu(i_clk, cpu_reset, i_ext_int,
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cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
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cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
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i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
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i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
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cpu_dbg_cc, cpu_break,
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cpu_dbg_cc, cpu_break,
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o_wb_cyc, o_wb_stb,
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o_wb_cyc, o_wb_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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