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[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Diff between revs 48 and 56

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Rev 48 Rev 56
Line 39... Line 39...
                i_ext_int,
                i_ext_int,
                // Our one outgoing interrupt
                // Our one outgoing interrupt
                o_ext_int,
                o_ext_int,
                // Wishbone slave interface for debugging purposes
                // Wishbone slave interface for debugging purposes
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
                        o_dbg_ack, o_dbg_stall, o_dbg_data,
 
                o_zip_debug);
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
                        LGICACHE=6, START_HALTED=1,
                        LGICACHE=6, START_HALTED=1,
                        AW=ADDRESS_WIDTH;
                        AW=ADDRESS_WIDTH;
        input   i_clk, i_rst;
        input   i_clk, i_rst;
        // Wishbone master
        // Wishbone master
Line 61... Line 62...
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
        input           [31:0]   i_dbg_data;
        input           [31:0]   i_dbg_data;
        output  reg             o_dbg_ack;
        output  reg             o_dbg_ack;
        output  wire            o_dbg_stall;
        output  wire            o_dbg_stall;
        output  wire    [31:0]   o_dbg_data;
        output  wire    [31:0]   o_dbg_data;
 
        //
 
        output  wire    [31:0]   o_zip_debug;
 
 
        // 
        // 
        //
        //
        //
        //
        wire    sys_cyc, sys_stb, sys_we;
        wire    sys_cyc, sys_stb, sys_we;
Line 87... Line 90...
        // register.
        // register.
        //
        //
        wire            cpu_break, dbg_cmd_write;
        wire            cpu_break, dbg_cmd_write;
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
        reg     [4:0]    cmd_addr;
        reg     [4:0]    cmd_addr;
        wire    [1:0]    cpu_dbg_cc;
        wire    [3:0]    cpu_dbg_cc;
        assign  dbg_cmd_write = (i_dbg_cyc)&&(i_dbg_stb)&&(i_dbg_we)&&(~i_dbg_addr);
        assign  dbg_cmd_write = (i_dbg_cyc)&&(i_dbg_stb)&&(i_dbg_we)&&(~i_dbg_addr);
        //
        //
        initial cmd_reset = 1'b1;
        initial cmd_reset = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
                cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
Line 124... Line 127...
        wire    cpu_reset;
        wire    cpu_reset;
        assign  cpu_reset = (cmd_reset)||(i_rst);
        assign  cpu_reset = (cmd_reset)||(i_rst);
 
 
        wire    cpu_halt, cpu_dbg_stall;
        wire    cpu_halt, cpu_dbg_stall;
        assign  cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
        assign  cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
        wire    [31:0]   pic_data;
 
        wire    [31:0]   cmd_data;
        wire    [31:0]   cmd_data;
        // Values:
        // Values:
        //      0x0003f -> cmd_addr mask
        //      0x0003f -> cmd_addr mask
        //      0x00040 -> reset
        //      0x00040 -> reset
        //      0x00080 -> PIC interrrupts enabled
        //      0x00080 -> PIC interrrupts enabled
Line 138... Line 140...
        //      0x00800 -> cmd_clear_pf_cache
        //      0x00800 -> cmd_clear_pf_cache
        //      0x01000 -> cc.sleep
        //      0x01000 -> cc.sleep
        //      0x02000 -> cc.gie
        //      0x02000 -> cc.gie
        //      0x10000 -> External interrupt line is high
        //      0x10000 -> External interrupt line is high
        assign  cmd_data = { 7'h00, 8'h00, i_ext_int,
        assign  cmd_data = { 7'h00, 8'h00, i_ext_int,
                        2'b00, cpu_dbg_cc,
                        cpu_dbg_cc,
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                        pic_data[15], cpu_reset, 1'b0, cmd_addr };
                        1'b0, cpu_reset, 1'b0, cmd_addr };
        wire    cpu_gie;
 
        assign  cpu_gie = cpu_dbg_cc[1];
 
 
 
        //
        //
        // The CPU itself
        // The CPU itself
        //
        //
        wire            cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
        wire            cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
                        cpu_we, cpu_dbg_we,
                        cpu_we, cpu_dbg_we,
                        cpu_op_stall, cpu_pf_stall, cpu_i_count;
                        cpu_op_stall, cpu_pf_stall, cpu_i_count;
        wire    [31:0]   cpu_data, wb_data;
        wire    [31:0]   cpu_data;
        wire            cpu_ack, cpu_stall, cpu_err;
 
        wire    [31:0]   cpu_dbg_data;
        wire    [31:0]   cpu_dbg_data;
        assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
        assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
                                        &&(i_dbg_we)&&(i_dbg_addr));
                                        &&(i_dbg_we)&&(i_dbg_addr));
        zipcpu  #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
        zipcpu  #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
                thecpu(i_clk, cpu_reset, i_ext_int,
                thecpu(i_clk, cpu_reset, i_ext_int,
Line 163... Line 162...
                                i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
                                i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
                                cpu_dbg_cc, cpu_break,
                                cpu_dbg_cc, cpu_break,
                        o_wb_cyc, o_wb_stb,
                        o_wb_cyc, o_wb_stb,
                                cpu_lcl_cyc, cpu_lcl_stb,
                                cpu_lcl_cyc, cpu_lcl_stb,
                                o_wb_we, o_wb_addr, o_wb_data,
                                o_wb_we, o_wb_addr, o_wb_data,
                                i_wb_ack, i_wb_stall, wb_data,
                                i_wb_ack, i_wb_stall, i_wb_data,
                                i_wb_err,
                                i_wb_err,
                        cpu_op_stall, cpu_pf_stall, cpu_i_count);
                        cpu_op_stall, cpu_pf_stall, cpu_i_count,
 
                        o_zip_debug);
 
 
        // Return debug response values
        // Return debug response values
        assign  o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;
        assign  o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;
        initial o_dbg_ack = 1'b0;
        initial o_dbg_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall));
                o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall));
        assign  o_dbg_stall=(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr);
        assign  o_dbg_stall=(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr);
 
 
        assign  o_ext_int = (cmd_halt) && (~cpu_stall);
        assign  o_ext_int = (cmd_halt) && (~i_wb_stall);
 
 
endmodule
endmodule
 
 
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