| Line 127... |
Line 127... |
// Wishbone master interface from the CPU
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// Wishbone master interface from the CPU
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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// Incoming interrupts
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// Incoming interrupts
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i_ext_int,
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i_ext_int,
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// Our one outgoing interrupt
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o_ext_int,
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// Wishbone slave interface for debugging purposes
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// Wishbone slave interface for debugging purposes
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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o_dbg_ack, o_dbg_stall, o_dbg_data);
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o_dbg_ack, o_dbg_stall, o_dbg_data);
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parameter RESET_ADDRESS=32'h0100000;
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parameter RESET_ADDRESS=32'h0100000;
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input i_clk, i_rst;
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input i_clk, i_rst;
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| Line 140... |
Line 142... |
output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// Incoming interrupts
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// Incoming interrupts
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input i_ext_int;
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input i_ext_int;
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// Outgoing interrupt
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output wire o_ext_int;
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// Wishbone slave
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// Wishbone slave
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input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
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input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
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input [31:0] i_dbg_data;
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input [31:0] i_dbg_data;
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output wire o_dbg_ack;
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output wire o_dbg_ack;
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output wire o_dbg_stall;
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output wire o_dbg_stall;
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| Line 193... |
Line 197... |
// two accesses: write the address to the control register (and halt
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// two accesses: write the address to the control register (and halt
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// the CPU if not halted), then read/write the data from the data
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// the CPU if not halted), then read/write the data from the data
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// register.
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// register.
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//
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//
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wire cpu_break, dbg_cmd_write;
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wire cpu_break, dbg_cmd_write;
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reg cmd_reset, cmd_halt, cmd_step;
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reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
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reg [5:0] cmd_addr;
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reg [5:0] cmd_addr;
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wire [3:0] cpu_dbg_cc;
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assign dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
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assign dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
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//
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//
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initial cmd_reset = 1'b1;
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initial cmd_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
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cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
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| Line 209... |
Line 214... |
cmd_halt <= 1'b1;
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cmd_halt <= 1'b1;
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else if (dbg_cmd_write)
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else if (dbg_cmd_write)
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cmd_halt <= dbg_idata[10];
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cmd_halt <= dbg_idata[10];
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else if ((cmd_step)||(cpu_break))
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else if ((cmd_step)||(cpu_break))
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cmd_halt <= 1'b1;
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cmd_halt <= 1'b1;
|
|
|
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always @(posedge i_clk)
|
|
if (i_rst)
|
|
cmd_clear_pf_cache <= 1'b0;
|
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else if (dbg_cmd_write)
|
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cmd_clear_pf_cache <= dbg_idata[11];
|
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else
|
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cmd_clear_pf_cache <= 1'b0;
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//
|
//
|
initial cmd_step = 1'b0;
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initial cmd_step = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
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cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
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//
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//
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| Line 225... |
Line 238... |
|
|
wire cpu_halt, cpu_dbg_stall;
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wire cpu_halt, cpu_dbg_stall;
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assign cpu_halt = (cmd_halt)&&(~cmd_step);
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assign cpu_halt = (cmd_halt)&&(~cmd_step);
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wire [31:0] pic_data;
|
wire [31:0] pic_data;
|
wire [31:0] cmd_data;
|
wire [31:0] cmd_data;
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assign cmd_data = { 21'h00, cmd_halt, (~cpu_dbg_stall), 1'b0, pic_data[15],
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// Values:
|
cpu_reset, cmd_addr };
|
// 0x0003f -> cmd_addr mask
|
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// 0x00040 -> reset
|
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// 0x00080 -> interrrupts enabled
|
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// 0x00100 -> cmd_step
|
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// 0x00200 -> cmd_stall
|
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// 0x00400 -> cmd_halt
|
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// 0x00800 -> cmd_clear_pf_cache
|
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// 0x01000 -> cc.sleep
|
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// 0x02000 -> cc.gie
|
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// 0x04000 -> cc.step
|
|
// 0x08000 -> cc.break_en
|
|
// 0x10000 -> External interrupt line is high
|
|
assign cmd_data = { 15'h00, i_ext_int, cpu_dbg_cc,
|
|
1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
|
|
pic_data[15], cpu_reset, cmd_addr };
|
|
|
`ifdef USE_TRAP
|
`ifdef USE_TRAP
|
//
|
//
|
// The TRAP peripheral
|
// The TRAP peripheral
|
//
|
//
|
| Line 449... |
Line 476... |
wire cpu_ack, cpu_stall;
|
wire cpu_ack, cpu_stall;
|
wire [31:0] cpu_dbg_data;
|
wire [31:0] cpu_dbg_data;
|
assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
|
assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
|
&&(dbg_we)&&(dbg_addr));
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&&(dbg_we)&&(dbg_addr));
|
zipcpu #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
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zipcpu #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
|
cpu_halt, cmd_addr[4:0], cpu_dbg_we,
|
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
|
dbg_idata, cpu_dbg_stall, cpu_dbg_data,
|
dbg_idata, cpu_dbg_stall, cpu_dbg_data,
|
cpu_break,
|
cpu_dbg_cc, cpu_break,
|
cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data,
|
cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data,
|
cpu_ack, cpu_stall, wb_data,
|
cpu_ack, cpu_stall, wb_data,
|
cpu_op_stall, cpu_pf_stall, cpu_i_count);
|
cpu_op_stall, cpu_pf_stall, cpu_i_count);
|
|
|
// Now, arbitrate the bus ... first for the local peripherals
|
// Now, arbitrate the bus ... first for the local peripherals
|
| Line 527... |
Line 554... |
|
|
assign cpu_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
|
assign cpu_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
|
| wdt_stall | cache_stall
|
| wdt_stall | cache_stall
|
| cpu_ext_stall);
|
| cpu_ext_stall);
|
assign cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack);
|
assign cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack);
|
|
|
|
assign o_ext_int = (cmd_halt) && (~cpu_stall);
|
|
|
endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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