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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: zipsystem.v
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// Filename: zipsystem.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// watchdog-timers,
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// watchdog-timers,
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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`include "cpudefs.v"
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`include "cpudefs.v"
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//
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//
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// While I hate adding delays to any bus access, this next delay is required
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// While I hate adding delays to any bus access, this next delay is required
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// to make timing close in my Basys-3 design.
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// to make timing close in my Basys-3 design.
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//
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//
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//
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//
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//
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//
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module zipsystem(i_clk, i_rst,
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module zipsystem(i_clk, i_rst,
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// Wishbone master interface from the CPU
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// Wishbone master interface from the CPU
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
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// Incoming interrupts
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// Incoming interrupts
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i_ext_int,
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i_ext_int,
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// Our one outgoing interrupt
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// Our one outgoing interrupt
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o_ext_int,
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o_ext_int,
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o_dbg_ack, o_dbg_stall, o_dbg_data
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o_dbg_ack, o_dbg_stall, o_dbg_data
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`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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, o_cpu_debug
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, o_cpu_debug
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`endif
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`endif
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);
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);
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=30,
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LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
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LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
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`ifdef OPT_MULTIPLY
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`ifdef OPT_MULTIPLY
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IMPLEMENT_MPY = `OPT_MULTIPLY,
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IMPLEMENT_MPY = `OPT_MULTIPLY,
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`else
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`else
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IMPLEMENT_MPY = 0,
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IMPLEMENT_MPY = 0,
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`ifdef OPT_IMPLEMENT_FPU
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`ifdef OPT_IMPLEMENT_FPU
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IMPLEMENT_FPU=1,
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IMPLEMENT_FPU=1,
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`else
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`else
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IMPLEMENT_FPU=0,
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IMPLEMENT_FPU=0,
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`endif
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`endif
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IMPLEMENT_LOCK=1,
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IMPLEMENT_LOCK=1;
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// Derived parameters
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localparam // Derived parameters
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AW=ADDRESS_WIDTH;
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AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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// Wishbone master
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// Wishbone master
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire [(AW-1):0] o_wb_addr;
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output wire [(AW-1):0] o_wb_addr;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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output wire [3:0] o_wb_sel;
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input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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input i_wb_err;
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input i_wb_err;
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// Incoming interrupts
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// Incoming interrupts
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input [(EXTERNAL_INTERRUPTS-1):0] i_ext_int;
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input [(EXTERNAL_INTERRUPTS-1):0] i_ext_int;
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// Handle our interrupt vector generation/coordination
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// Handle our interrupt vector generation/coordination
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wire [14:0] main_int_vector, alt_int_vector;
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wire [14:0] main_int_vector, alt_int_vector;
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wire ctri_int, tma_int, tmb_int, tmc_int, jif_int, dmac_int;
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wire ctri_int, tma_int, tmb_int, tmc_int, jif_int, dmac_int;
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wire mtc_int, moc_int, mpc_int, mic_int,
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wire mtc_int, moc_int, mpc_int, mic_int,
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utc_int, uoc_int, upc_int, uic_int;
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utc_int, uoc_int, upc_int, uic_int;
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assign main_int_vector[5:0] = { ctri_int, tma_int, tmb_int, tmc_int,
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jif_int, dmac_int };
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generate
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generate
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if (EXTERNAL_INTERRUPTS < 9)
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if (EXTERNAL_INTERRUPTS < 9)
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assign main_int_vector = { {(9-EXTERNAL_INTERRUPTS){1'b0}},
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assign main_int_vector[14:6] = { {(9-EXTERNAL_INTERRUPTS){1'b0}},
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i_ext_int, ctri_int,
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i_ext_int };
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tma_int, tmb_int, tmc_int,
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jif_int, dmac_int };
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else
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else
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assign main_int_vector = { i_ext_int[8:0], ctri_int,
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assign main_int_vector[14:6] = i_ext_int[8:0];
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tma_int, tmb_int, tmc_int,
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jif_int, dmac_int };
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endgenerate
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endgenerate
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generate
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generate
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if (EXTERNAL_INTERRUPTS <= 9)
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if (EXTERNAL_INTERRUPTS <= 9)
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`ifdef INCLUDE_ACCOUNTING_COUNTERS
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`ifdef INCLUDE_ACCOUNTING_COUNTERS
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assign alt_int_vector = { 7'h00,
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assign alt_int_vector = { 7'h00,
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wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
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wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
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wire [31:0] dbg_idata, dbg_odata;
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wire [31:0] dbg_idata, dbg_odata;
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reg dbg_ack;
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reg dbg_ack;
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`ifdef DELAY_DBG_BUS
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`ifdef DELAY_DBG_BUS
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wire dbg_err, no_dbg_err;
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wire dbg_err, no_dbg_err;
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wire [3:0] dbg_sel;
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assign dbg_err = 1'b0;
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assign dbg_err = 1'b0;
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busdelay #(1,32) wbdelay(i_clk,
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busdelay #(1,32) wbdelay(i_clk,
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, 4'hf,
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o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
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o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
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dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
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dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata, dbg_sel,
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dbg_ack, dbg_stall, dbg_odata, dbg_err);
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dbg_ack, dbg_stall, dbg_odata, dbg_err);
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`else
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`else
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assign dbg_cyc = i_dbg_cyc;
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assign dbg_cyc = i_dbg_cyc;
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assign dbg_stb = i_dbg_stb;
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assign dbg_stb = i_dbg_stb;
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assign dbg_we = i_dbg_we;
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assign dbg_we = i_dbg_we;
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Line 677... |
// The CPU itself
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// The CPU itself
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//
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//
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wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
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wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
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cpu_we, cpu_dbg_we;
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cpu_we, cpu_dbg_we;
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wire [31:0] cpu_data, wb_data;
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wire [31:0] cpu_data, wb_data;
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wire [3:0] cpu_sel;
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wire cpu_ack, cpu_stall, cpu_err;
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wire cpu_ack, cpu_stall, cpu_err;
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wire [31:0] cpu_dbg_data;
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wire [31:0] cpu_dbg_data;
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assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
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assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
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&&(dbg_we)&&(dbg_addr));
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&&(dbg_we)&&(dbg_addr));
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zipcpu #(
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zipcpu #(
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Line 697... |
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
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cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
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dbg_idata, cpu_dbg_stall, cpu_dbg_data,
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dbg_idata, cpu_dbg_stall, cpu_dbg_data,
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cpu_dbg_cc, cpu_break,
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cpu_dbg_cc, cpu_break,
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cpu_gbl_cyc, cpu_gbl_stb,
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cpu_gbl_cyc, cpu_gbl_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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cpu_we, cpu_addr, cpu_data,
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cpu_we, cpu_addr, cpu_data, cpu_sel,
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cpu_ack, cpu_stall, wb_data,
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cpu_ack, cpu_stall, wb_data,
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cpu_err,
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cpu_err,
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cpu_op_stall, cpu_pf_stall, cpu_i_count
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cpu_op_stall, cpu_pf_stall, cpu_i_count
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`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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, o_cpu_debug
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, o_cpu_debug
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Line 751... |
wire ext_cyc, ext_stb, ext_we, ext_err;
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wire ext_cyc, ext_stb, ext_we, ext_err;
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wire cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
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wire cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
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cpu_ext_err;
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cpu_ext_err;
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wire [(AW-1):0] ext_addr;
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wire [(AW-1):0] ext_addr;
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wire [31:0] ext_odata;
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wire [31:0] ext_odata;
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wire [3:0] ext_sel;
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wbpriarbiter #(32,AW) dmacvcpu(i_clk,
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wbpriarbiter #(32,AW) dmacvcpu(i_clk,
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cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data,
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cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data, cpu_sel,
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cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
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cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
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dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
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dc_cyc, dc_stb, dc_we, dc_addr, dc_data, 4'hf,
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dc_ack, dc_stall, dc_err,
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dc_ack, dc_stall, dc_err,
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ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
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ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, ext_sel,
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ext_ack, ext_stall, ext_err);
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ext_ack, ext_stall, ext_err);
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`ifdef DELAY_EXT_BUS
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`ifdef DELAY_EXT_BUS
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busdelay #(AW,32) extbus(i_clk,
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busdelay #(AW,32) extbus(i_clk,
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ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
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ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
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ext_ack, ext_stall, ext_idata, ext_err,
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ext_ack, ext_stall, ext_idata, ext_err,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int));
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i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int));
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`else
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`else
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assign o_wb_cyc = ext_cyc;
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assign o_wb_cyc = ext_cyc;
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assign o_wb_stb = ext_stb;
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assign o_wb_stb = ext_stb;
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assign o_wb_we = ext_we;
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assign o_wb_we = ext_we;
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assign o_wb_addr = ext_addr;
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assign o_wb_addr = ext_addr;
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assign o_wb_data = ext_odata;
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assign o_wb_data = ext_odata;
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assign o_wb_sel = ext_sel;
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assign ext_ack = i_wb_ack;
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assign ext_ack = i_wb_ack;
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assign ext_stall = i_wb_stall;
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assign ext_stall = i_wb_stall;
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assign ext_idata = i_wb_data;
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assign ext_idata = i_wb_data;
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assign ext_err = (i_wb_err)||(wdbus_int);
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assign ext_err = (i_wb_err)||(wdbus_int);
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`endif
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`endif
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