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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Diff between revs 201 and 209

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//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
// Purpose:     This portion of the ZIP CPU implements a number of soft
// Purpose:     This portion of the ZIP CPU implements a number of soft
//              peripherals to the CPU nearby its CORE.  The functionality
//              peripherals to the CPU nearby its CORE.  The functionality
//              sits on the data bus, and does not include any true
//      sits on the data bus, and does not include any true external hardware
//              external hardware peripherals.  The peripherals included here
//      peripherals.  The peripherals included here include:
//              include:
 
//
 
//
//
//      Local interrupt controller--for any/all of the interrupts generated
//      Local interrupt controller--for any/all of the interrupts generated
//              here.  This would include a pin for interrupts generated
//              here.  This would include a pin for interrupts generated
//              elsewhere, so this interrupt controller could be a master
//              elsewhere, so this interrupt controller could be a master
//              handling all interrupts.  My interrupt controller would work
//              handling all interrupts.  My interrupt controller would work
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//
//
//              The ZIP-CPU supports only one interrupt because, as I understand
//              The ZIP-CPU supports only one interrupt because, as I understand
//              modern systems (Linux), they tend to send all interrupts to the
//              modern systems (Linux), they tend to send all interrupts to the
//              same interrupt vector anyway.  Hence, that's what we do here.
//              same interrupt vector anyway.  Hence, that's what we do here.
//
//
//      Bus Error interrupts -- generates an interrupt any time the wishbone
 
//              bus produces an error on a given access, for whatever purpose
 
//              also records the address on the bus at the time of the error.
 
//
 
//      Trap instructions
 
//              Writing to this "register" will always create an interrupt.
 
//              After the interrupt, this register may be read to see what
 
//              value had been written to it.
 
//
 
//      Bit reverse register ... ?
 
//
 
//      (Potentially an eventual floating point co-processor ...)
 
//
 
//      Real-time clock
 
//
 
//      Interval timer(s) (Count down from fixed value, and either stop on
//      Interval timer(s) (Count down from fixed value, and either stop on
//              zero, or issue an interrupt and restart automatically on zero)
//              zero, or issue an interrupt and restart automatically on zero)
//              These can be implemented as watchdog timers if desired--the
//              These can be implemented as watchdog timers if desired--the
//              only difference is that a watchdog timer's interrupt feeds the
//              only difference is that a watchdog timer's interrupt feeds the
//              reset line instead of the processor interrupt line.
//              reset line instead of the processor interrupt line.
//
//
//      Watch-dog timer: this is the same as an interval timer, only it's
//      Watch-dog timer: this is the same as an interval timer, only it's
//              interrupt/time-out line is wired to the reset line instead of
//              interrupt/time-out line is wired to the reset line instead of
//              the interrupt line of the CPU.
//              the interrupt line of the CPU.
//
//
//      ROM Memory map
//      Direct Memory Access Controller: This controller allows you to command
//              Set a register to control this map, and a DMA will begin to
//              automatic memory moves.  Such memory moves will take place
//              fill this memory from a slower FLASH.  Once filled, accesses
//              without the CPU's involvement until they are done.  See the
//              will be from this memory instead of 
//              DMA specification for more information. (Currently contained
 
//              w/in the ZipCPU spec.)
 
//
 
//      (Potentially an eventual floating point co-processor ...?)
 
//
 
// Busses:      The ZipSystem implements a series of busses to make this take
 
//              place.  These busses are identified by their prefix:
 
//
 
//      cpu     This is the bus as the CPU sees it.  Since the CPU controls
 
//              two busses (a local and a global one), it uses _gbl_ to indicate
 
//              the external bus (going through the MMU if necessary) and
 
//              _lcl_ to indicate a peripheral bus seen here.
 
//
 
//      mmu     Sits between the CPU's wishbone interface and the external
 
//              bus.  Has no access to peripherals.
 
//
 
//      sys     A local bus implemented here within this space.  This is how the
 
//              CPU talks to the ZipSystem peripherals.  However, this bus
 
//              can also be accessed from the external debug bus.
//
//
 
//      io_dbg
 
//      io_wb
//
//
//      Doing some market comparison, let's look at what peripherals a TI
//      dbg     This is identical to the io_dbg bus, but separated by a clock
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
//      dc      The output of the DMA controller
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
 
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
 
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
 
//      watchdog-timers,
 
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
// Copyright (C) 2015-2019, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
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//
//
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
//
//
 
`default_nettype        none
 
//
`include "cpudefs.v"
`include "cpudefs.v"
//
//
 
`define RESET_BIT       6
 
`define STEP_BIT        8
 
`define HALT_BIT        10
 
`define CLEAR_CACHE_BIT 11
 
//
// While I hate adding delays to any bus access, this next delay is required
// While I hate adding delays to any bus access, this next delay is required
// to make timing close in my Basys-3 design.
// to make timing close in my Basys-3 design.
`define DELAY_DBG_BUS
`define DELAY_DBG_BUS
// On my previous version, I needed to add a delay to access the external
 
// bus.  Activate the define below and that delay will be put back into place.
 
// This particular version no longer needs the delay in order to run at 
 
// 100 MHz.  Timing indicates I may even run this at 250 MHz without the
 
// delay too, so we're doing better.  To get rid of this, I placed the logic
 
// determining whether or not I was accessing the local system bus one clock
 
// earlier, or into the memops.v file.  This also required my wishbone bus
 
// arbiter to maintain the bus selection as well, so that got updated ...
 
// you get the picture.  But, the bottom line is that I no longer need this
 
// delay.
 
//
//
// `define      DELAY_EXT_BUS   // Required no longer!
// `define      DELAY_EXT_BUS
//
//
//
//
// If space is tight, you might not wish to have your performance and
// If space is tight, you might not wish to have your performance and
// accounting counters, so let's make those optional here
// accounting counters, so let's make those optional here
//      Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU)
//      Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU)
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//      Without Counters        2796            2046
//      Without Counters        2796            2046
 
 
//
//
// Now, where am I placing all of my peripherals?
// Now, where am I placing all of my peripherals?
`define PERIPHBASE      32'hc0000000
`define PERIPHBASE      32'hc0000000
`define INTCTRL         5'h0    // 
`define INTCTRL         8'h0    // 
`define WATCHDOG        5'h1    // Interrupt generates reset signal
`define WATCHDOG        8'h1    // Interrupt generates reset signal
`define BUSWATCHDOG     5'h2    // Sets IVEC[0]
`define BUSWATCHDOG     8'h2    // Sets IVEC[0]
`define CTRINT          5'h3    // Sets IVEC[5]
`define CTRINT          8'h3    // Sets IVEC[5]
`define TIMER_A         5'h4    // Sets IVEC[4]
`define TIMER_A         8'h4    // Sets IVEC[4]
`define TIMER_B         5'h5    // Sets IVEC[3]
`define TIMER_B         8'h5    // Sets IVEC[3]
`define TIMER_C         5'h6    // Sets IVEC[2]
`define TIMER_C         8'h6    // Sets IVEC[2]
`define JIFFIES         5'h7    // Sets IVEC[1]
`define JIFFIES         8'h7    // Sets IVEC[1]
 
 
 
 
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
`define MSTR_TASK_CTR   5'h08
`define MSTR_TASK_CTR   8'h08
`define MSTR_MSTL_CTR   5'h09
`define MSTR_MSTL_CTR   8'h09
`define MSTR_PSTL_CTR   5'h0a
`define MSTR_PSTL_CTR   8'h0a
`define MSTR_INST_CTR   5'h0b
`define MSTR_INST_CTR   8'h0b
`define USER_TASK_CTR   5'h0c
`define USER_TASK_CTR   8'h0c
`define USER_MSTL_CTR   5'h0d
`define USER_MSTL_CTR   8'h0d
`define USER_PSTL_CTR   5'h0e
`define USER_PSTL_CTR   8'h0e
`define USER_INST_CTR   5'h0f
`define USER_INST_CTR   8'h0f
 
`endif
 
 
 
`ifdef  OPT_MMU
 
`define MMU_ADDR        8'h80
`endif
`endif
 
 
// Although I have a hole at 5'h2, the DMA controller requires four wishbone
// Although I have a hole at 5'h2, the DMA controller requires four wishbone
// addresses, therefore we place it by itself and expand our address bus
// addresses, therefore we place it by itself and expand our address bus
// width here by another bit.
// width here by another bit.
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//      DBGDATA
//      DBGDATA
//              read/writes internal registers
//              read/writes internal registers
//
//
//
//
//
//
module  zipsystem(i_clk, i_rst,
module  zipsystem(i_clk, i_reset,
                // Wishbone master interface from the CPU
                // Wishbone master interface from the CPU
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
                // Incoming interrupts
                // Incoming interrupts
                i_ext_int,
                i_ext_int,
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                        o_dbg_ack, o_dbg_stall, o_dbg_data
                        o_dbg_ack, o_dbg_stall, o_dbg_data
`ifdef  DEBUG_SCOPE
`ifdef  DEBUG_SCOPE
                , o_cpu_debug
                , o_cpu_debug
`endif
`endif
                );
                );
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=30,
        parameter       RESET_ADDRESS=32'h1000_0000, ADDRESS_WIDTH=30,
                        LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
                        LGICACHE=10,
 
                        LGDCACHE=12;    // Set to zero for no data cache
 
        parameter [0:0]   START_HALTED=1;
 
        parameter       EXTERNAL_INTERRUPTS=1,
`ifdef  OPT_MULTIPLY
`ifdef  OPT_MULTIPLY
                        IMPLEMENT_MPY = `OPT_MULTIPLY,
                        IMPLEMENT_MPY = `OPT_MULTIPLY;
`else
`else
                        IMPLEMENT_MPY = 0,
                        IMPLEMENT_MPY = 0;
`endif
`endif
 
        parameter [0:0]
`ifdef  OPT_DIVIDE
`ifdef  OPT_DIVIDE
                        IMPLEMENT_DIVIDE=1,
                        IMPLEMENT_DIVIDE=1,
`else
`else
                        IMPLEMENT_DIVIDE=0,
                        IMPLEMENT_DIVIDE=0,
`endif
`endif
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`else
`else
                        IMPLEMENT_FPU=0,
                        IMPLEMENT_FPU=0,
`endif
`endif
                        IMPLEMENT_LOCK=1;
                        IMPLEMENT_LOCK=1;
        localparam      // Derived parameters
        localparam      // Derived parameters
                        AW=ADDRESS_WIDTH;
                        PHYSICAL_ADDRESS_WIDTH=ADDRESS_WIDTH,
        input   i_clk, i_rst;
                        PAW=ADDRESS_WIDTH,
 
`ifdef  OPT_MMU
 
                        VIRTUAL_ADDRESS_WIDTH=30,
 
`else
 
                        VIRTUAL_ADDRESS_WIDTH=PAW,
 
`endif
 
                        LGTLBSZ = 6,
 
                        VAW=VIRTUAL_ADDRESS_WIDTH;
 
 
 
        localparam      AW=ADDRESS_WIDTH;
 
        input   wire    i_clk, i_reset;
        // Wishbone master
        // Wishbone master
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire    [(AW-1):0]       o_wb_addr;
        output  wire    [(PAW-1):0]      o_wb_addr;
        output  wire    [31:0]   o_wb_data;
        output  wire    [31:0]   o_wb_data;
        output  wire    [3:0]    o_wb_sel;
        output  wire    [3:0]    o_wb_sel;
        input                   i_wb_ack, i_wb_stall;
        input   wire            i_wb_ack, i_wb_stall;
        input           [31:0]   i_wb_data;
        input   wire    [31:0]   i_wb_data;
        input                   i_wb_err;
        input   wire            i_wb_err;
        // Incoming interrupts
        // Incoming interrupts
        input           [(EXTERNAL_INTERRUPTS-1):0]      i_ext_int;
        input   wire    [(EXTERNAL_INTERRUPTS-1):0]      i_ext_int;
        // Outgoing interrupt
        // Outgoing interrupt
        output  wire            o_ext_int;
        output  wire            o_ext_int;
        // Wishbone slave
        // Wishbone slave
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
        input   wire            i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
        input           [31:0]   i_dbg_data;
        input   wire    [31:0]   i_dbg_data;
        output  wire            o_dbg_ack;
        output  wire            o_dbg_ack;
        output  wire            o_dbg_stall;
        output  wire            o_dbg_stall;
        output  wire    [31:0]   o_dbg_data;
        output  wire    [31:0]   o_dbg_data;
        //
        //
`ifdef  DEBUG_SCOPE
`ifdef  DEBUG_SCOPE
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`else
`else
                assign  alt_int_vector = { 15'h00 };
                assign  alt_int_vector = { 15'h00 };
`endif
`endif
        else
        else
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
 
        if (EXTERNAL_INTERRUPTS >= 15)
 
                assign  alt_int_vector = { i_ext_int[14:8],
 
                                        mtc_int, moc_int, mpc_int, mic_int,
 
                                        utc_int, uoc_int, upc_int, uic_int };
 
        else
                assign  alt_int_vector = { {(7-(EXTERNAL_INTERRUPTS-9)){1'b0}},
                assign  alt_int_vector = { {(7-(EXTERNAL_INTERRUPTS-9)){1'b0}},
                                        i_ext_int[(EXTERNAL_INTERRUPTS-1):9],
                                        i_ext_int[(EXTERNAL_INTERRUPTS-1):9],
                                        mtc_int, moc_int, mpc_int, mic_int,
                                        mtc_int, moc_int, mpc_int, mic_int,
                                        utc_int, uoc_int, upc_int, uic_int };
                                        utc_int, uoc_int, upc_int, uic_int };
`else
`else
 
        if (EXTERNAL_INTERRUPTS >= 24)
 
                assign  alt_int_vector = { i_ext_int[(EXTERNAL_INTERRUPTS-1):9] };
 
        else
                assign  alt_int_vector = { {(15-(EXTERNAL_INTERRUPTS-9)){1'b0}},
                assign  alt_int_vector = { {(15-(EXTERNAL_INTERRUPTS-9)){1'b0}},
                                        i_ext_int[(EXTERNAL_INTERRUPTS-1):9] };
                                        i_ext_int[(EXTERNAL_INTERRUPTS-1):9] };
`endif
`endif
        endgenerate
        endgenerate
 
 
 
 
        // Delay the debug port by one clock, to meet timing requirements
        // Delay the debug port by one clock, to meet timing requirements
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
        wire    [31:0]   dbg_idata, dbg_odata;
        wire    [31:0]   dbg_idata, dbg_odata;
        reg             dbg_ack;
        reg             dbg_ack;
`ifdef  DELAY_DBG_BUS
 
        wire            dbg_err, no_dbg_err;
 
        wire    [3:0]    dbg_sel;
        wire    [3:0]    dbg_sel;
 
        wire            no_dbg_err;
 
`ifdef  DELAY_DBG_BUS
 
        // Make verilator happy
 
        // verilator lint_off UNUSED
 
        // verilator lint_on  UNUSED
 
        wire            dbg_err;
        assign          dbg_err = 1'b0;
        assign          dbg_err = 1'b0;
        busdelay #(1,32) wbdelay(i_clk,
        busdelay #(1,32) wbdelay(i_clk, i_reset,
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, 4'hf,
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, 4'hf,
                        o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
                        o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata, dbg_sel,
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata, dbg_sel,
                        dbg_ack, dbg_stall, dbg_odata, dbg_err);
                        dbg_ack, dbg_stall, dbg_odata, dbg_err);
`else
`else
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        assign  dbg_addr    = i_dbg_addr;
        assign  dbg_addr    = i_dbg_addr;
        assign  dbg_idata   = i_dbg_data;
        assign  dbg_idata   = i_dbg_data;
        assign  o_dbg_ack   = dbg_ack;
        assign  o_dbg_ack   = dbg_ack;
        assign  o_dbg_stall = dbg_stall;
        assign  o_dbg_stall = dbg_stall;
        assign  o_dbg_data  = dbg_odata;
        assign  o_dbg_data  = dbg_odata;
 
        assign  dbg_sel     = 4'b1111;
 
        assign  no_dbg_err  = 1'b0;
`endif
`endif
 
 
        // 
        // 
        //
        //
        //
        //
        wire    sys_cyc, sys_stb, sys_we;
        wire    sys_cyc, sys_stb, sys_we;
        wire    [4:0]    sys_addr;
        wire    [7:0]    sys_addr;
        wire    [(AW-1):0]       cpu_addr;
        wire    [(PAW-1):0]      cpu_addr;
        wire    [31:0]   sys_data;
        wire    [31:0]   sys_data;
        wire            sys_ack, sys_stall;
        reg     [31:0]   sys_idata;
 
        reg             sys_ack;
 
        wire            sys_stall;
 
 
 
        wire    sel_counter, sel_timer, sel_pic, sel_apic,
 
                sel_watchdog, sel_bus_watchdog, sel_dmac, sel_mmus;
 
        //
 
        assign  sel_pic         = (sys_stb)&&(sys_addr == `INTCTRL);
 
        assign  sel_watchdog    = (sys_stb)&&(sys_addr == `WATCHDOG);
 
        assign  sel_bus_watchdog= (sys_stb)&&(sys_addr == `BUSWATCHDOG);
 
        assign  sel_apic        = (sys_stb)&&(sys_addr == `CTRINT);
 
        assign  sel_timer       = (sys_stb)&&(sys_addr[7:2] == 6'h1);
 
        assign  sel_counter     = (sys_stb)&&(sys_addr[7:3] == 5'h1);
 
        assign  sel_dmac        = (sys_stb)&&(sys_addr[7:4] == 4'h1);
 
        assign  sel_mmus        = (sys_stb)&&(sys_addr[7]);
 
 
        //
        //
        // The external debug interface
        // The external debug interface
        //
        //
        // We offer only a limited interface here, requiring a pre-register
        // We offer only a limited interface here, requiring a pre-register
Line 308... Line 350...
        //
        //
        wire            cpu_break, dbg_cmd_write;
        wire            cpu_break, dbg_cmd_write;
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
        reg     [5:0]    cmd_addr;
        reg     [5:0]    cmd_addr;
        wire    [3:0]    cpu_dbg_cc;
        wire    [3:0]    cpu_dbg_cc;
        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
        assign  dbg_cmd_write = (dbg_stb)&&(dbg_we)&&(!dbg_addr);
 
        //
 
        // Always start us off with an initial reset
        //
        //
        initial cmd_reset = 1'b1;
        initial cmd_reset = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[`RESET_BIT]))
 
                        ||(wdt_reset);
        //
        //
        initial cmd_halt  = START_HALTED;
        initial cmd_halt  = START_HALTED;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
        if (i_reset)
                        cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
                cmd_halt <= START_HALTED;
 
        else if (cmd_reset)
 
                cmd_halt <= START_HALTED;
                else if (dbg_cmd_write)
                else if (dbg_cmd_write)
                        cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
                cmd_halt <= ((dbg_idata[`HALT_BIT])&&(!dbg_idata[`STEP_BIT]));
                else if ((cmd_step)||(cpu_break))
                else if ((cmd_step)||(cpu_break))
                        cmd_halt  <= 1'b1;
                        cmd_halt  <= 1'b1;
 
 
        initial cmd_clear_pf_cache = 1'b1;
        initial cmd_clear_pf_cache = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
                cmd_clear_pf_cache <= (dbg_cmd_write)&&(dbg_idata[`CLEAR_CACHE_BIT]);
                                        &&((dbg_idata[11])||(dbg_idata[6]));
 
        //
        //
        initial cmd_step  = 1'b0;
        initial cmd_step  = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
                cmd_step <= (dbg_cmd_write)&&(dbg_idata[`STEP_BIT]);
        //
        //
 
        initial cmd_addr = 6'h0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (dbg_cmd_write)
                if (dbg_cmd_write)
                        cmd_addr <= dbg_idata[5:0];
                        cmd_addr <= dbg_idata[5:0];
 
 
        wire    cpu_reset;
        wire    cpu_reset;
        assign  cpu_reset = (cmd_reset)||(wdt_reset)||(i_rst);
        assign  cpu_reset = (cmd_reset);
 
 
        wire    cpu_halt, cpu_dbg_stall;
        wire    cpu_halt, cpu_dbg_stall;
        assign  cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
        assign  cpu_halt = (cmd_halt);
        wire    [31:0]   pic_data;
        wire    [31:0]   pic_data;
        wire    [31:0]   cmd_data;
        wire    [31:0]   cmd_data;
        // Values:
        // Values:
        //      0x0003f -> cmd_addr mask
        //      0x0003f -> cmd_addr mask
        //      0x00040 -> reset
        //      0x00040 -> reset
Line 360... Line 407...
        generate
        generate
        if (EXTERNAL_INTERRUPTS < 16)
        if (EXTERNAL_INTERRUPTS < 16)
                assign  cmd_data = { {(16-EXTERNAL_INTERRUPTS){1'b0}},
                assign  cmd_data = { {(16-EXTERNAL_INTERRUPTS){1'b0}},
                                        i_ext_int,
                                        i_ext_int,
                                cpu_dbg_cc,     // 4 bits
                                cpu_dbg_cc,     // 4 bits
                                1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                                1'b0, cmd_halt, (!cpu_dbg_stall), 1'b0,
                                pic_data[15], cpu_reset, cmd_addr };
                                pic_data[15], cpu_reset, cmd_addr };
        else
        else
                assign  cmd_data = { i_ext_int[15:0], cpu_dbg_cc,
                assign  cmd_data = { i_ext_int[15:0], cpu_dbg_cc,
                                1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                                1'b0, cmd_halt, (!cpu_dbg_stall), 1'b0,
                                pic_data[15], cpu_reset, cmd_addr };
                                pic_data[15], cpu_reset, cmd_addr };
        endgenerate
        endgenerate
 
 
        wire    cpu_gie;
        wire    cpu_gie;
        assign  cpu_gie = cpu_dbg_cc[1];
        assign  cpu_gie = cpu_dbg_cc[1];
Line 377... Line 424...
        // The WATCHDOG Timer
        // The WATCHDOG Timer
        //
        //
        wire            wdt_ack, wdt_stall, wdt_reset;
        wire            wdt_ack, wdt_stall, wdt_reset;
        wire    [31:0]   wdt_data;
        wire    [31:0]   wdt_data;
        ziptimer #(32,31,0)
        ziptimer #(32,31,0)
                watchdog(i_clk, cpu_reset, ~cmd_halt,
                watchdog(i_clk, cpu_reset, !cmd_halt,
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
                        sys_cyc, (sys_stb)&&(sel_watchdog), sys_we,
                                sys_data,
                                sys_data,
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
 
 
        //
        //
        // Position two, a second watchdog timer--this time for the wishbone
        // Position two, a second watchdog timer--this time for the wishbone
        // bus, in order to tell/find wishbone bus lockups.  In its current
        // bus, in order to tell/find wishbone bus lockups.  In its current
        // configuration, it cannot be configured and all bus accesses must
        // configuration, it cannot be configured and all bus accesses must
        // take less than the number written to this register.
        // take less than the number written to this register.
        //
        //
        reg     wdbus_ack;
        reg     wdbus_ack;
        reg     [(AW-1):0]       r_wdbus_data;
        reg     [(PAW-1):0]      r_wdbus_data;
        wire    [31:0]           wdbus_data;
        wire    [31:0]           wdbus_data;
        wire    [14:0]   wdbus_ignored_data;
 
        wire    reset_wdbus_timer, wdbus_int;
        wire    reset_wdbus_timer, wdbus_int;
        assign  reset_wdbus_timer = ((o_wb_cyc)&&((o_wb_stb)||(i_wb_ack)));
        assign  reset_wdbus_timer = (!o_wb_cyc)||(o_wb_stb)||(i_wb_ack);
        wbwatchdog #(14) watchbus(i_clk,(cpu_reset)||(reset_wdbus_timer),
        wbwatchdog #(14) watchbus(i_clk,(cpu_reset)||(reset_wdbus_timer),
                        o_wb_cyc, 14'h2000, wdbus_int);
                        14'h2000, wdbus_int);
        initial r_wdbus_data = 0;
        initial r_wdbus_data = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((wdbus_int)||(cpu_ext_err))
                if ((wdbus_int)||(cpu_err))
                        r_wdbus_data = o_wb_addr;
                        r_wdbus_data <= o_wb_addr;
        assign  wdbus_data = { {(32-AW){1'b0}}, r_wdbus_data };
        assign  wdbus_data = { {(32-PAW){1'b0}}, r_wdbus_data };
        initial wdbus_ack = 1'b0;
        initial wdbus_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                wdbus_ack <= ((sys_cyc)&&(sys_stb)&&(sys_addr == 5'h02));
                wdbus_ack <= ((sys_cyc)&&(sys_stb)&&(sel_bus_watchdog));
 
 
        // Counters -- for performance measurement and accounting
        // Counters -- for performance measurement and accounting
        //
        //
        // Here's the stuff we'll be counting ....
        // Here's the stuff we'll be counting ....
        //
        //
Line 419... Line 465...
        // for an overall counter.
        // for an overall counter.
        //
        //
        // Master task counter
        // Master task counter
        wire            mtc_ack, mtc_stall;
        wire            mtc_ack, mtc_stall;
        wire    [31:0]   mtc_data;
        wire    [31:0]   mtc_data;
        zipcounter      mtask_ctr(i_clk, (~cpu_halt), sys_cyc,
        zipcounter      mtask_ctr(i_clk, 1'b0, (!cpu_halt), sys_cyc,
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b000),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
 
 
        // Master Operand Stall counter
        // Master Operand Stall counter
        wire            moc_ack, moc_stall;
        wire            moc_ack, moc_stall;
        wire    [31:0]   moc_data;
        wire    [31:0]   moc_data;
        zipcounter      mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
        zipcounter      mmstall_ctr(i_clk,1'b0, (cpu_op_stall), sys_cyc,
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b001),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                moc_ack, moc_stall, moc_data, moc_int);
                                moc_ack, moc_stall, moc_data, moc_int);
 
 
        // Master PreFetch-Stall counter
        // Master PreFetch-Stall counter
        wire            mpc_ack, mpc_stall;
        wire            mpc_ack, mpc_stall;
        wire    [31:0]   mpc_data;
        wire    [31:0]   mpc_data;
        zipcounter      mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
        zipcounter      mpstall_ctr(i_clk,1'b0, (cpu_pf_stall), sys_cyc,
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b010),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
 
 
        // Master Instruction counter
        // Master Instruction counter
        wire            mic_ack, mic_stall;
        wire            mic_ack, mic_stall;
        wire    [31:0]   mic_data;
        wire    [31:0]   mic_data;
        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,
        zipcounter      mins_ctr(i_clk,1'b0, (cpu_i_count), sys_cyc,
                                (sys_stb)&&(sys_addr == `MSTR_INST_CTR),
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b011),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                mic_ack, mic_stall, mic_data, mic_int);
                                mic_ack, mic_stall, mic_data, mic_int);
 
 
        //
        //
        // The user counters are different from those of the master.  They will
        // The user counters are different from those of the master.  They will
        // be reset any time a task is given control of the CPU.
        // be reset any time a task is given control of the CPU.
        //
        //
        // User task counter
        // User task counter
        wire            utc_ack, utc_stall;
        wire            utc_ack, utc_stall;
        wire    [31:0]   utc_data;
        wire    [31:0]   utc_data;
        zipcounter      utask_ctr(i_clk,(~cpu_halt)&&(cpu_gie), sys_cyc,
        zipcounter      utask_ctr(i_clk,1'b0, (!cpu_halt)&&(cpu_gie), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b100),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                utc_ack, utc_stall, utc_data, utc_int);
                                utc_ack, utc_stall, utc_data, utc_int);
 
 
        // User Op-Stall counter
        // User Op-Stall counter
        wire            uoc_ack, uoc_stall;
        wire            uoc_ack, uoc_stall;
        wire    [31:0]   uoc_data;
        wire    [31:0]   uoc_data;
        zipcounter      umstall_ctr(i_clk,(cpu_op_stall)&&(cpu_gie), sys_cyc,
        zipcounter      umstall_ctr(i_clk,1'b0, (cpu_op_stall)&&(cpu_gie), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b101),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
 
 
        // User PreFetch-Stall counter
        // User PreFetch-Stall counter
        wire            upc_ack, upc_stall;
        wire            upc_ack, upc_stall;
        wire    [31:0]   upc_data;
        wire    [31:0]   upc_data;
        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall)&&(cpu_gie), sys_cyc,
        zipcounter      upstall_ctr(i_clk,1'b0, (cpu_pf_stall)&&(cpu_gie), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b110),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                upc_ack, upc_stall, upc_data, upc_int);
                                upc_ack, upc_stall, upc_data, upc_int);
 
 
        // User instruction counter
        // User instruction counter
        wire            uic_ack, uic_stall;
        wire            uic_ack, uic_stall;
        wire    [31:0]   uic_data;
        wire    [31:0]   uic_data;
        zipcounter      uins_ctr(i_clk,(cpu_i_count)&&(cpu_gie), sys_cyc,
        zipcounter      uins_ctr(i_clk,1'b0, (cpu_i_count)&&(cpu_gie), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_INST_CTR),
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b111),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                uic_ack, uic_stall, uic_data, uic_int);
                                uic_ack, uic_stall, uic_data, uic_int);
 
 
        // A little bit of pre-cleanup (actr = accounting counters)
        // A little bit of pre-cleanup (actr = accounting counters)
        wire            actr_ack, actr_stall;
        wire            actr_ack, actr_stall;
Line 516... Line 562...
        assign  uoc_int = 1'b0;
        assign  uoc_int = 1'b0;
        assign  upc_int = 1'b0;
        assign  upc_int = 1'b0;
        assign  uic_int = 1'b0;
        assign  uic_int = 1'b0;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                actr_ack <= (sys_stb)&&(sys_addr[4:3] == 2'b01);
                actr_ack <= sel_counter;
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
 
 
        //
        //
        // The DMA Controller
        // The DMA Controller
        //
        //
        wire            dmac_stb, dc_err;
        wire            dmac_stb, dc_err;
        wire    [31:0]   dmac_data;
        wire    [31:0]   dmac_data;
        wire            dmac_ack, dmac_stall;
        wire            dmac_ack, dmac_stall;
        wire            dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
        wire            dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
        wire    [31:0]   dc_data;
        wire    [31:0]   dc_data;
        wire    [(AW-1):0]       dc_addr;
        wire    [(PAW-1):0]      dc_addr;
        wire            cpu_gbl_cyc;
        wire            cpu_gbl_cyc;
        wire    [31:0]   dmac_int_vec;
        wire    [31:0]   dmac_int_vec;
        assign  dmac_int_vec = { 1'b0, alt_int_vector, 1'b0,
        assign  dmac_int_vec = { 1'b0, alt_int_vector, 1'b0,
                                        main_int_vector[14:1], 1'b0 };
                                        main_int_vector[14:1], 1'b0 };
        assign  dmac_stb = (sys_stb)&&(sys_addr[4]);
        assign  dmac_stb = (sys_stb)&&(sel_dmac);
`ifdef  INCLUDE_DMA_CONTROLLER
`ifdef  INCLUDE_DMA_CONTROLLER
        wbdmac  #(AW) dma_controller(i_clk, cpu_reset,
        wbdmac  #(PAW) dma_controller(i_clk, cpu_reset,
                                sys_cyc, dmac_stb, sys_we,
                                sys_cyc, dmac_stb, sys_we,
                                        sys_addr[1:0], sys_data,
                                        sys_addr[1:0], sys_data,
                                        dmac_ack, dmac_stall, dmac_data,
                                        dmac_ack, dmac_stall, dmac_data,
                                // Need the outgoing DMAC wishbone bus
                                // Need the outgoing DMAC wishbone bus
                                dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
                                dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
Line 547... Line 593...
                                dmac_int_vec,
                                dmac_int_vec,
                                // DMAC interrupt, for upon completion
                                // DMAC interrupt, for upon completion
                                dmac_int);
                                dmac_int);
`else
`else
        reg     r_dmac_ack;
        reg     r_dmac_ack;
 
        initial r_dmac_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_dmac_ack <= (sys_cyc)&&(dmac_stb);
                r_dmac_ack <= (sys_cyc)&&(dmac_stb);
        assign  dmac_ack = r_dmac_ack;
        assign  dmac_ack = r_dmac_ack;
        assign  dmac_data = 32'h000;
        assign  dmac_data = 32'h000;
        assign  dmac_stall = 1'b0;
        assign  dmac_stall = 1'b0;
 
 
        assign  dc_cyc  = 1'b0;
        assign  dc_cyc  = 1'b0;
        assign  dc_stb  = 1'b0;
        assign  dc_stb  = 1'b0;
        assign  dc_we   = 1'b0;
        assign  dc_we   = 1'b0;
        assign  dc_addr = { (AW) {1'b0} };
        assign  dc_addr = { (PAW) {1'b0} };
        assign  dc_data = 32'h00;
        assign  dc_data = 32'h00;
 
 
        assign  dmac_int = 1'b0;
        assign  dmac_int = 1'b0;
`endif
`endif
 
 
        wire            ctri_sel, ctri_stall;
        wire            ctri_sel, ctri_stall;
        reg             ctri_ack;
        reg             ctri_ack;
        wire    [31:0]   ctri_data;
        wire    [31:0]   ctri_data;
        assign  ctri_sel = (sys_stb)&&(sys_addr == `CTRINT);
        assign  ctri_sel = (sys_stb)&&(sel_apic);
 
        initial ctri_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                ctri_ack <= ctri_sel;
                ctri_ack <= (ctri_sel)&&(!cpu_reset);
        assign  ctri_stall = 1'b0;
        assign  ctri_stall = 1'b0;
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
        //
        //
        // Counter Interrupt controller
        // Counter Interrupt controller
        //
        //
        generate
        generate if (EXTERNAL_INTERRUPTS <= 9)
        if (EXTERNAL_INTERRUPTS <= 9)
        begin : ALT_PIC
        begin
 
                icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel),
                icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel),
                                        sys_data, ctri_data, alt_int_vector[7:0],
                                        sys_data, ctri_data, alt_int_vector[7:0],
                                        ctri_int);
                                        ctri_int);
        end else begin
        end else begin : ALT_PIC
                icontrol #(8+(EXTERNAL_INTERRUPTS-9))
                icontrol #(8+(EXTERNAL_INTERRUPTS-9))
                                ctri(i_clk, cpu_reset, (ctri_sel),
                                ctri(i_clk, cpu_reset, (ctri_sel),
                                        sys_data, ctri_data,
                                        sys_data, ctri_data,
                                        alt_int_vector[(EXTERNAL_INTERRUPTS-2):0],
                                        alt_int_vector[(EXTERNAL_INTERRUPTS-2):0],
                                        ctri_int);
                                        ctri_int);
        end endgenerate
        end endgenerate
 
 
`else   //      INCLUDE_ACCOUNTING_COUNTERS
`else   //      INCLUDE_ACCOUNTING_COUNTERS
 
 
        generate
        generate if (EXTERNAL_INTERRUPTS <= 9)
        if (EXTERNAL_INTERRUPTS <= 9)
        begin : ALT_PIC
        begin
 
                assign  ctri_stall = 1'b0;
                assign  ctri_stall = 1'b0;
                assign  ctri_data  = 32'h0000;
                assign  ctri_data  = 32'h0000;
                assign  ctri_int   = 1'b0;
                assign  ctri_int   = 1'b0;
        end else begin
        end else begin : ALT_PIC
                icontrol #(EXTERNAL_INTERRUPTS-9)
                icontrol #(EXTERNAL_INTERRUPTS-9)
                                ctri(i_clk, cpu_reset, (ctri_sel),
                                ctri(i_clk, cpu_reset, (ctri_sel),
                                        sys_data, ctri_data,
                                        sys_data, ctri_data,
                                alt_int_vector[(EXTERNAL_INTERRUPTS-10):0],
                                alt_int_vector[(EXTERNAL_INTERRUPTS-10):0],
                                        ctri_int);
                                        ctri_int);
Line 610... Line 656...
        //
        //
        // Timer A
        // Timer A
        //
        //
        wire            tma_ack, tma_stall;
        wire            tma_ack, tma_stall;
        wire    [31:0]   tma_data;
        wire    [31:0]   tma_data;
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
        ziptimer timer_a(i_clk, cpu_reset, !cmd_halt,
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
                sys_cyc, (sys_stb)&&(sel_timer)&&(sys_addr[1:0] == 2'b00),
                                sys_data,
                        sys_we, sys_data,
                        tma_ack, tma_stall, tma_data, tma_int);
                        tma_ack, tma_stall, tma_data, tma_int);
 
 
        //
        //
        // Timer B
        // Timer B
        //
        //
        wire            tmb_ack, tmb_stall;
        wire            tmb_ack, tmb_stall;
        wire    [31:0]   tmb_data;
        wire    [31:0]   tmb_data;
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
        ziptimer timer_b(i_clk, cpu_reset, !cmd_halt,
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
                sys_cyc, (sys_stb)&&(sel_timer)&&(sys_addr[1:0] == 2'b01),
                                sys_data,
                        sys_we, sys_data,
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
 
 
        //
        //
        // Timer C
        // Timer C
        //
        //
        wire            tmc_ack, tmc_stall;
        wire            tmc_ack, tmc_stall;
        wire    [31:0]   tmc_data;
        wire    [31:0]   tmc_data;
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
        ziptimer timer_c(i_clk, cpu_reset, !cmd_halt,
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
                sys_cyc, (sys_stb)&&(sel_timer)&&(sys_addr[1:0]==2'b10),
                                sys_data,
                        sys_we, sys_data,
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
 
 
        //
        //
        // JIFFIES
        // JIFFIES
        //
        //
        wire            jif_ack, jif_stall;
        wire            jif_ack, jif_stall;
        wire    [31:0]   jif_data;
        wire    [31:0]   jif_data;
        zipjiffies jiffies(i_clk, ~cmd_halt,
        zipjiffies jiffies(i_clk, cpu_reset, !cmd_halt,
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
                        sys_cyc, (sys_stb)&&(sel_timer)&&(sys_addr[1:0] == 2'b11), sys_we,
                                sys_data,
                                sys_data,
                        jif_ack, jif_stall, jif_data, jif_int);
                        jif_ack, jif_stall, jif_data, jif_int);
 
 
        //
        //
        // The programmable interrupt controller peripheral
        // The programmable interrupt controller peripheral
        //
        //
        wire            pic_interrupt;
        wire            pic_interrupt;
        generate
        generate if (EXTERNAL_INTERRUPTS < 9)
        if (EXTERNAL_INTERRUPTS < 9)
        begin : MAIN_PIC
        begin
 
                icontrol #(6+EXTERNAL_INTERRUPTS)       pic(i_clk, cpu_reset,
                icontrol #(6+EXTERNAL_INTERRUPTS)       pic(i_clk, cpu_reset,
                                        (sys_cyc)&&(sys_stb)&&(sys_we)
                                        (sys_cyc)&&(sys_stb)&&(sys_we)
                                                &&(sys_addr==`INTCTRL),
                                                &&(sel_pic),
                                        sys_data, pic_data,
                                        sys_data, pic_data,
                                        main_int_vector[(6+EXTERNAL_INTERRUPTS-1):0], pic_interrupt);
                                        main_int_vector[(6+EXTERNAL_INTERRUPTS-1):0], pic_interrupt);
        end else begin
        end else begin : MAIN_PIC
                icontrol #(15)  pic(i_clk, cpu_reset,
                icontrol #(15)  pic(i_clk, cpu_reset,
                                        (sys_cyc)&&(sys_stb)&&(sys_we)
                                        (sys_cyc)&&(sys_stb)&&(sys_we)
                                                &&(sys_addr==`INTCTRL),
                                                &&(sel_pic),
                                        sys_data, pic_data,
                                        sys_data, pic_data,
                                        main_int_vector[14:0], pic_interrupt);
                                        main_int_vector[14:0], pic_interrupt);
        end endgenerate
        end endgenerate
 
 
        wire    pic_stall;
        wire    pic_stall;
        assign  pic_stall = 1'b0;
        assign  pic_stall = 1'b0;
        reg     pic_ack;
        reg     pic_ack;
        always @(posedge i_clk)
        always @(posedge i_clk)
                pic_ack <= (sys_stb)&&(sys_addr == `INTCTRL);
                pic_ack <= (sys_stb)&&(sel_pic);
 
 
        //
        //
        // The CPU itself
        // The CPU itself
        //
        //
        wire            cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
        wire            cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
                        cpu_we, cpu_dbg_we;
                        cpu_we, cpu_dbg_we;
        wire    [31:0]   cpu_data, wb_data;
        wire    [31:0]   cpu_data, cpu_idata;
        wire    [3:0]    cpu_sel;
        wire    [3:0]    cpu_sel, mmu_sel;
        wire            cpu_ack, cpu_stall, cpu_err;
        wire            cpu_ack, cpu_stall, cpu_err;
        wire    [31:0]   cpu_dbg_data;
        wire    [31:0]   cpu_dbg_data;
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(!cmd_addr[5])
                                        &&(dbg_we)&&(dbg_addr));
                                        &&(dbg_we)&&(dbg_addr));
        zipcpu  #(
        zipcpu  #(      .RESET_ADDRESS(RESET_ADDRESS),
                        .RESET_ADDRESS(RESET_ADDRESS),
                        .ADDRESS_WIDTH(VIRTUAL_ADDRESS_WIDTH),
                        .ADDRESS_WIDTH(ADDRESS_WIDTH),
 
                        .LGICACHE(LGICACHE),
                        .LGICACHE(LGICACHE),
 
                        .OPT_LGDCACHE(LGDCACHE),
                        .IMPLEMENT_MPY(IMPLEMENT_MPY),
                        .IMPLEMENT_MPY(IMPLEMENT_MPY),
                        .IMPLEMENT_DIVIDE(IMPLEMENT_DIVIDE),
                        .IMPLEMENT_DIVIDE(IMPLEMENT_DIVIDE),
                        .IMPLEMENT_FPU(IMPLEMENT_FPU),
                        .IMPLEMENT_FPU(IMPLEMENT_FPU),
                        .IMPLEMENT_LOCK(IMPLEMENT_LOCK)
                        .IMPLEMENT_LOCK(IMPLEMENT_LOCK),
 
                        .WITH_LOCAL_BUS(1'b1)
                )
                )
                thecpu(i_clk, cpu_reset, pic_interrupt,
                thecpu(i_clk, cpu_reset, pic_interrupt,
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
                                cpu_dbg_cc, cpu_break,
                                cpu_dbg_cc, cpu_break,
                        cpu_gbl_cyc, cpu_gbl_stb,
                        cpu_gbl_cyc, cpu_gbl_stb,
                                cpu_lcl_cyc, cpu_lcl_stb,
                                cpu_lcl_cyc, cpu_lcl_stb,
                                cpu_we, cpu_addr, cpu_data, cpu_sel,
                                cpu_we, cpu_addr, cpu_data, cpu_sel,
                                cpu_ack, cpu_stall, wb_data,
                                // Return values from the Wishbone bus
                                cpu_err,
                                cpu_ack, cpu_stall, cpu_idata, cpu_err,
                        cpu_op_stall, cpu_pf_stall, cpu_i_count
                        cpu_op_stall, cpu_pf_stall, cpu_i_count
`ifdef  DEBUG_SCOPE
`ifdef  DEBUG_SCOPE
                        , o_cpu_debug
                        , o_cpu_debug
`endif
`endif
                        );
                        );
 
 
 
        wire    ext_ack, ext_stall;
 
        wire    mmu_cyc, mmu_stb, mmu_we, mmu_stall, mmu_ack, mmu_err;
 
        wire    mmus_ack, mmus_stall;
 
        wire [PAW-1:0]   mmu_addr;
 
        wire [31:0]      mmu_data, mmu_idata, mmus_data;
 
 
 
        // Specific responses from the MMU
 
        wire            cpu_miss;
 
 
 
        // The mmu_cpu_ lines are the return bus lines from the MMU.  They
 
        // are separate from the cpu_'s lines simply because either the sys_
 
        // (local) bus or the mmu_cpu_ (global) bus might return a response to
 
        // the CPU, and the responses haven't been merged back together again
 
        // yet.
 
        wire            mmu_cpu_ack, mmu_cpu_stall;
 
        wire    [31:0]   mmu_cpu_idata;
 
 
 
        // The wires associated with cache snooping
 
        wire            pf_return_stb, pf_return_we, pf_return_cachable;
 
        wire    [19:0]   pf_return_v, pf_return_p;
 
 
 
`ifdef  OPT_MMU
 
        // Ok ... here's the MMU
 
        zipmmu  #(      .LGTBL(LGTLBSZ),
 
                        .ADDRESS_WIDTH(PHYSICAL_ADDRESS_WIDTH)
 
                        )
 
                themmu(i_clk, cpu_reset,
 
                        // Slave interface
 
                        (sys_stb)&&(sel_mmus),
 
                                sys_we, sys_addr[7:0], sys_data,
 
                                mmus_ack, mmus_stall, mmus_data,
 
                        // CPU global bus master lines
 
                        cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr,
 
                                cpu_data, cpu_sel,
 
                        // MMU bus master outgoing lines
 
                        mmu_cyc, mmu_stb, mmu_we, mmu_addr, mmu_data, mmu_sel,
 
                                // .... and the return from the slave(s)
 
                                mmu_stall, mmu_ack, mmu_err, mmu_idata,
 
                        // CPU gobal bus master return lines
 
                                mmu_cpu_stall, mmu_cpu_ack, cpu_err, cpu_miss, mmu_cpu_idata,
 
                                pf_return_stb, pf_return_we, pf_return_p, pf_return_v,
 
                                        pf_return_cachable);
 
 
 
`else
 
        assign  mmu_cyc   = cpu_gbl_cyc;
 
        assign  mmu_stb   = cpu_gbl_stb;
 
        assign  mmu_we    = cpu_we;
 
        assign  mmu_addr  = cpu_addr;
 
        assign  mmu_data  = cpu_data;
 
        assign  mmu_sel   = cpu_sel;
 
        assign  cpu_miss  = 1'b0;
 
        assign  cpu_err   = (mmu_err)&&(cpu_gbl_cyc);
 
        assign  mmu_cpu_idata = mmu_idata;
 
        assign  mmu_cpu_stall = mmu_stall;
 
        assign  mmu_cpu_ack   = mmu_ack;
 
        reg     r_mmus_ack;
 
        initial r_mmus_ack = 1'b0;
 
        always @(posedge i_clk)
 
                r_mmus_ack <= (sys_stb)&&(sys_addr[7]);
 
        assign  mmus_ack   = r_mmus_ack;
 
        assign  mmus_stall = 1'b0;
 
        assign  mmus_data  = 32'h0;
 
 
 
        assign  pf_return_stb = 0;
 
        assign  pf_return_v   = 0;
 
        assign  pf_return_p   = 0;
 
        assign  pf_return_we  = 0;
 
        assign  pf_return_cachable = 0;
 
`endif
 
        // Responses from the MMU still need to be merged/muxed back together
 
        // with the responses from the local bus
 
        assign  cpu_ack   = ((cpu_lcl_cyc)&&(sys_ack))
 
                                ||((cpu_gbl_cyc)&&(mmu_cpu_ack));
 
        assign  cpu_stall = ((cpu_lcl_cyc)&&(sys_stall))
 
                                ||((cpu_gbl_cyc)&&(mmu_cpu_stall));
 
        assign  cpu_idata     = (cpu_gbl_cyc)?mmu_cpu_idata : sys_idata;
 
 
 
        // The following lines (will be/) are used to allow the prefetch to
 
        // snoop on any external interaction.  Until this capability is
 
        // integrated into the CPU, they are unused.  Here we tell Verilator
 
        // not to be surprised that these lines are unused:
 
 
 
        // verilator lint_off UNUSED
 
        wire    [(3+1+20+20-1):0]        mmu_unused;
 
        assign  mmu_unused = { pf_return_stb, pf_return_we,
 
                                pf_return_p, pf_return_v, pf_return_cachable,
 
                                cpu_miss };
 
        // verilator lint_on UNUSED
 
 
        // Now, arbitrate the bus ... first for the local peripherals
        // Now, arbitrate the bus ... first for the local peripherals
        // For the debugger to have access to the local system bus, the
        // For the debugger to have access to the local system bus, the
        // following must be true:
        // following must be true:
        //      (dbg_cyc)       The debugger must request the bus
        //      (dbg_cyc)       The debugger must request the bus
        //      (~cpu_lcl_cyc)  The CPU cannot be using it (CPU gets priority)
        //      (!cpu_lcl_cyc)  The CPU cannot be using it (CPU gets priority)
        //      (dbg_addr)      The debugger must be requesting its data
        //      (dbg_addr)      The debugger must be requesting its data
        //                              register, not just the control register
        //                              register, not just the control register
        // and one of two other things.  Either
        // and one of two other things.  Either
        //      ((cpu_halt)&&(~cpu_dbg_stall))  the CPU is completely halted,
        //      ((cpu_halt)&&(!cpu_dbg_stall))  the CPU is completely halted,
        // or
        // or
        //      (~cmd_addr[5])          we are trying to read a CPU register
        //      (!cmd_addr[5])          we are trying to read a CPU register
        //                      while in motion.  Let the user beware that,
        //                      while in motion.  Let the user beware that,
        //                      by not waiting for the CPU to fully halt,
        //                      by not waiting for the CPU to fully halt,
        //                      his results may not be what he expects.
        //                      his results may not be what he expects.
        //
        //
        wire    sys_dbg_cyc = ((dbg_cyc)&&(~cpu_lcl_cyc)&&(dbg_addr))
        wire    sys_dbg_cyc = ((dbg_cyc)&&(!cpu_lcl_cyc)&&(dbg_addr))
                                &&(((cpu_halt)&&(~cpu_dbg_stall))
                                &&(cmd_addr[5]);
                                        ||(~cmd_addr[5]));
 
        assign  sys_cyc = (cpu_lcl_cyc)||(sys_dbg_cyc);
        assign  sys_cyc = (cpu_lcl_cyc)||(sys_dbg_cyc);
        assign  sys_stb = (cpu_lcl_cyc)
        assign  sys_stb = (cpu_lcl_cyc)
                                ? (cpu_lcl_stb)
                                ? (cpu_lcl_stb)
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
 
 
        assign  sys_we  = (cpu_lcl_cyc) ? cpu_we : dbg_we;
        assign  sys_we  = (cpu_lcl_cyc) ? cpu_we : dbg_we;
        assign  sys_addr= (cpu_lcl_cyc) ? cpu_addr[4:0] : cmd_addr[4:0];
        assign  sys_addr= (cpu_lcl_cyc) ? cpu_addr[7:0] : { 3'h0, cmd_addr[4:0]};
        assign  sys_data= (cpu_lcl_cyc) ? cpu_data : dbg_idata;
        assign  sys_data= (cpu_lcl_cyc) ? cpu_data : dbg_idata;
 
 
        // Return debug response values
        // Return debug response values
        assign  dbg_odata = (~dbg_addr)?cmd_data
        // A return from one of three busses:
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
        //      CMD     giving command instructions to the CPU (step, halt, etc)
 
        //      CPU-DBG-DATA    internal register responses from within the CPU
 
        //      sys     Responses from the front-side bus here in the ZipSystem
 
        assign  dbg_odata = (!dbg_addr) ? cmd_data
 
                                :((!cmd_addr[5])?cpu_dbg_data : sys_idata);
        initial dbg_ack = 1'b0;
        initial dbg_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                dbg_ack <= (dbg_cyc)&&(dbg_stb)&&(~dbg_stall);
                dbg_ack <= (dbg_stb)&&(!dbg_stall);
        assign  dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr);
        assign  dbg_stall=(dbg_cyc)&&(
 
                ((!sys_dbg_cyc)&&(cpu_dbg_stall))
 
                        ||(sys_stall)
 
                )&&(dbg_addr);
 
 
        // Now for the external wishbone bus
        // Now for the external wishbone bus
        //      Need to arbitrate between the flash cache and the CPU
        //      Need to arbitrate between the flash cache and the CPU
        // The way this works, though, the CPU will stall once the flash 
        // The way this works, though, the CPU will stall once the flash 
        // cache gets access to the bus--the CPU will be stuck until the 
        // cache gets access to the bus--the CPU will be stuck until the 
        // flash cache is finished with the bus.
        // flash cache is finished with the bus.
        wire            ext_cyc, ext_stb, ext_we, ext_err;
        wire            ext_cyc, ext_stb, ext_we, ext_err;
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
        wire    [(PAW-1):0]      ext_addr;
                                cpu_ext_err;
 
        wire    [(AW-1):0]       ext_addr;
 
        wire    [31:0]           ext_odata;
        wire    [31:0]           ext_odata;
        wire    [3:0]            ext_sel;
        wire    [3:0]            ext_sel;
        wbpriarbiter #(32,AW) dmacvcpu(i_clk,
        wbpriarbiter #(32,PAW) dmacvcpu(i_clk,
                        cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data, cpu_sel,
                        mmu_cyc, mmu_stb, mmu_we, mmu_addr, mmu_data, mmu_sel,
                                cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
                                mmu_ack, mmu_stall, mmu_err,
                        dc_cyc, dc_stb, dc_we, dc_addr, dc_data, 4'hf,
                        dc_cyc, dc_stb, dc_we, dc_addr, dc_data, 4'hf,
                                        dc_ack, dc_stall, dc_err,
                                        dc_ack, dc_stall, dc_err,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, ext_sel,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, ext_sel,
                                ext_ack, ext_stall, ext_err);
                                ext_ack, ext_stall, ext_err);
 
        assign  mmu_idata = ext_idata;
 
/*
 
        assign  ext_cyc  = mmu_cyc;
 
        assign  ext_stb  = mmu_stb;
 
        assign  ext_we   = mmu_we;
 
        assign  ext_odata= mmu_data;
 
        assign  ext_addr = mmu_addr;
 
        assign  ext_sel  = mmu_sel;
 
        assign  mmu_ack  = ext_ack;
 
        assign  mmu_stall= ext_stall;
 
        assign  mmu_err  = ext_err;
 
*/
 
 
`ifdef  DELAY_EXT_BUS
`ifdef  DELAY_EXT_BUS
        busdelay #(AW,32) extbus(i_clk,
        busdelay #(.AW(PAW),.DW(32),.DELAY_STALL(0)) extbus(i_clk, i_reset,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, ext_sel,
                                ext_ack, ext_stall, ext_idata, ext_err,
                                ext_ack, ext_stall, ext_idata, ext_err,
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
                                i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int));
                                i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int));
`else
`else
        assign  o_wb_cyc  = ext_cyc;
        assign  o_wb_cyc  = ext_cyc;
Line 786... Line 937...
        wire    [31:0]   tmr_data;
        wire    [31:0]   tmr_data;
        assign  tmr_data = (tma_ack)?tma_data
        assign  tmr_data = (tma_ack)?tma_data
                                :(tmb_ack ? tmb_data
                                :(tmb_ack ? tmb_data
                                :(tmc_ack ? tmc_data
                                :(tmc_ack ? tmc_data
                                :jif_data));
                                :jif_data));
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
        always @(posedge i_clk)
                        :((actr_ack|dmac_ack)?((actr_ack)?actr_data:dmac_data)
                casez({ mmus_ack,  tmr_ack, wdt_ack,  actr_ack,
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
                        dmac_ack, pic_ack, ctri_ack, wdbus_ack })
                        :((wdbus_ack)?wdbus_data:(ext_idata))));
                8'b1???????: sys_idata <=  mmus_data;
 
                8'b01??????: sys_idata <=  tmr_data;
 
                8'b001?????: sys_idata <=  wdt_data;
 
                8'b0001????: sys_idata <=  actr_data;
 
                8'b00001???: sys_idata <=  dmac_data;
 
                8'b000001??: sys_idata <=  pic_data;
 
                8'b0000001?: sys_idata <=  ctri_data;
 
                8'b00000001: sys_idata <=  wdbus_data;
 
                default:     sys_idata <=  mmus_data;
 
                endcase
 
 
 
        always @(posedge i_clk)
 
        if ((i_reset)||(!sys_cyc))
 
                sys_ack <= 1'b0;
 
        else
 
                sys_ack <= (|{  mmu_ack, tmr_ack, wdt_ack, actr_ack,
 
                                dmac_ack, pic_ack, ctri_ack, wdbus_ack,
 
                                mmus_ack });
 
 
        assign  sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
        assign  sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
                                | wdt_stall | ctri_stall | actr_stall
                                | wdt_stall | ctri_stall | actr_stall
                                | pic_stall | dmac_stall); // Always 1'b0!
                                | pic_stall | dmac_stall | mmus_stall); // Always 1'b0!
        assign  cpu_stall = (sys_stall)|(cpu_ext_stall);
 
        assign  sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack);
 
        assign  cpu_ack = (sys_ack)||(cpu_ext_ack);
 
        assign  cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
 
 
 
        assign  o_ext_int = (cmd_halt) && (~cpu_stall);
        assign  o_ext_int = (cmd_halt) && (!cpu_stall);
 
 
 
        // Make verilator happy
 
        // verilator lint_off UNUSED
 
        wire    [5:0]    unused;
 
        assign unused = { no_dbg_err, dbg_sel, sel_mmus };
 
`ifndef INCLUDE_ACCOUNTING_COUNTERS
 
        wire    [11:0]   unused_ctrs;
 
        assign  unused_ctrs = {
 
                moc_int, mpc_int, mic_int, mtc_int,
 
                uoc_int, upc_int, uic_int, utc_int,
 
                cpu_gie, cpu_op_stall, cpu_pf_stall, cpu_i_count };
 
`endif
 
`ifndef INCLUDE_DMA_CONTROLLER
 
        wire    [34:0]   unused_dmac;
 
        assign  unused_dmac = { dc_err, dc_ack, dc_stall, dmac_int_vec };
 
`endif
 
        // verilator lint_on UNUSED
endmodule
endmodule
 
 
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