| Line 80... |
Line 80... |
// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// While I hate adding delays to any bus access, these two are required
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// While I hate adding delays to any bus access, this next delay is required
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// to make timing close in my Basys-3 design.
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// to make timing close in my Basys-3 design.
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`define DELAY_EXT_BUS
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`define DELAY_DBG_BUS
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`define DELAY_DBG_BUS
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//
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// On my previous version, I needed to add a delay to access the external
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// bus. Activate the define below and that delay will be put back into place.
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// This particular version no longer needs the delay in order to run at
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// 100 MHz. Timing indicates I may even run this at 250 MHz without the
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// delay too, so we're doing better. To get rid of this, I placed the logic
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// determining whether or not I was accessing the local system bus one clock
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// earlier, or into the memops.v file. This also required my wishbone bus
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// arbiter to maintain the bus selection as well, so that got updated ...
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// you get the picture. But, the bottom line is that I no longer need this
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// delay.
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//
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// `define DELAY_EXT_BUS // Required no longer!k
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//
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//
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// If space is tight, you might not wish to have your performance and
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// accounting counters, so let's make those optional here
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// Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU)
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// When including counters,
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// Slice LUTs ZipSystem ZipCPU
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// With Counters 3315 2432
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// Without Counters 2796 2046
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`define INCLUDE_ACCOUNTING_COUNTERS
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|
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//
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//
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// Now, where am I placing all of my peripherals?
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// Now, where am I placing all of my peripherals?
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`define PERIPHBASE 32'hc0000000
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`define PERIPHBASE 32'hc0000000
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`define INTCTRL 4'h0 //
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`define INTCTRL 5'h0 //
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`define WATCHDOG 4'h1 // Interrupt generates reset signal
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`define WATCHDOG 5'h1 // Interrupt generates reset signal
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`define CACHECTRL 4'h2 // Sets IVEC[0]
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// `define CACHECTRL 5'h2 // Sets IVEC[0]
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`define CTRINT 4'h3 // Sets IVEC[5]
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`define CTRINT 5'h3 // Sets IVEC[5]
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`define TIMER_A 4'h4 // Sets IVEC[4]
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`define TIMER_A 5'h4 // Sets IVEC[4]
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`define TIMER_B 4'h5 // Sets IVEC[3]
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`define TIMER_B 5'h5 // Sets IVEC[3]
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`define TIMER_C 4'h6 // Sets IVEC[2]
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`define TIMER_C 5'h6 // Sets IVEC[2]
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`define JIFFIES 4'h7 // Sets IVEC[1]
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`define JIFFIES 5'h7 // Sets IVEC[1]
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|
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`define MSTR_TASK_CTR 4'h8
|
|
`define MSTR_MSTL_CTR 4'h9
|
`ifdef INCLUDE_ACCOUNTING_COUNTERS
|
`define MSTR_PSTL_CTR 4'ha
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`define MSTR_TASK_CTR 5'h08
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`define MSTR_INST_CTR 4'hb
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`define MSTR_MSTL_CTR 5'h09
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`define USER_TASK_CTR 4'hc
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`define MSTR_PSTL_CTR 5'h0a
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`define USER_MSTL_CTR 4'hd
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`define MSTR_INST_CTR 5'h0b
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`define USER_PSTL_CTR 4'he
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`define USER_TASK_CTR 5'h0c
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`define USER_INST_CTR 4'hf
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`define USER_MSTL_CTR 5'h0d
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`define USER_PSTL_CTR 5'h0e
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`define USER_INST_CTR 5'h0f
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`endif
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|
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// Although I have a hole at 5'h2, the DMA controller requires four wishbone
|
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// addresses, therefore we place it by itself and expand our address bus
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// width here by another bit.
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`define DMAC 5'h10
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|
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`define CACHEBASE 16'hc010 //
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// `define RTC_CLOCK 32'hc0000008 // A global something
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// `define RTC_CLOCK 32'hc0000008 // A global something
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// `define BITREV 32'hc0000003
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// `define BITREV 32'hc0000003
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//
|
//
|
// DBGCTRL
|
// DBGCTRL
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// 10 HALT
|
// 10 HALT
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| Line 124... |
Line 152... |
// DBGDATA
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// DBGDATA
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// read/writes internal registers
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// read/writes internal registers
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module zipsystem(i_clk, i_rst,
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module zipsystem(i_clk, i_rst,
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// Wishbone master interface from the CPU
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// Wishbone master interface from the CPU
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
|
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
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// Incoming interrupts
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// Incoming interrupts
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i_ext_int,
|
i_ext_int,
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// Our one outgoing interrupt
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// Our one outgoing interrupt
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o_ext_int,
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o_ext_int,
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// Wishbone slave interface for debugging purposes
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// Wishbone slave interface for debugging purposes
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| Line 141... |
Line 169... |
output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire [31:0] o_wb_addr;
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output wire [31:0] o_wb_addr;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
|
|
input i_wb_err;
|
// Incoming interrupts
|
// Incoming interrupts
|
input [(EXTERNAL_INTERRUPTS-1):0] i_ext_int;
|
input [(EXTERNAL_INTERRUPTS-1):0] i_ext_int;
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// Outgoing interrupt
|
// Outgoing interrupt
|
output wire o_ext_int;
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output wire o_ext_int;
|
// Wishbone slave
|
// Wishbone slave
|
| Line 159... |
Line 188... |
// Delay the debug port by one clock, to meet timing requirements
|
// Delay the debug port by one clock, to meet timing requirements
|
wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
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wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
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wire [31:0] dbg_idata, dbg_odata;
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wire [31:0] dbg_idata, dbg_odata;
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reg dbg_ack;
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reg dbg_ack;
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`ifdef DELAY_DBG_BUS
|
`ifdef DELAY_DBG_BUS
|
|
wire dbg_err, no_dbg_err;
|
|
assign dbg_err = 1'b0;
|
busdelay #(1,32) wbdelay(i_clk,
|
busdelay #(1,32) wbdelay(i_clk,
|
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
|
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
|
o_dbg_ack, o_dbg_stall, o_dbg_data,
|
o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
|
dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
|
dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
|
dbg_ack, dbg_stall, dbg_odata);
|
dbg_ack, dbg_stall, dbg_odata, dbg_err);
|
`else
|
`else
|
assign dbg_cyc = i_dbg_cyc;
|
assign dbg_cyc = i_dbg_cyc;
|
assign dbg_stb = i_dbg_stb;
|
assign dbg_stb = i_dbg_stb;
|
assign dbg_we = i_dbg_we;
|
assign dbg_we = i_dbg_we;
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assign dbg_addr = i_dbg_addr;
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assign dbg_addr = i_dbg_addr;
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| Line 179... |
Line 210... |
|
|
//
|
//
|
//
|
//
|
//
|
//
|
wire sys_cyc, sys_stb, sys_we;
|
wire sys_cyc, sys_stb, sys_we;
|
wire [3:0] sys_addr;
|
wire [4:0] sys_addr;
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wire [31:0] cpu_addr;
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wire [31:0] cpu_addr;
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wire [31:0] sys_data;
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wire [31:0] sys_data;
|
// wire sys_ack, sys_stall;
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wire sys_ack, sys_stall;
|
|
|
//
|
//
|
// The external debug interface
|
// The external debug interface
|
//
|
//
|
// We offer only a limited interface here, requiring a pre-register
|
// We offer only a limited interface here, requiring a pre-register
|
| Line 212... |
Line 243... |
initial cmd_halt = 1'b1;
|
initial cmd_halt = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
|
cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
|
else if (dbg_cmd_write)
|
else if (dbg_cmd_write)
|
cmd_halt <= dbg_idata[10];
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cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
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else if ((cmd_step)||(cpu_break))
|
else if ((cmd_step)||(cpu_break))
|
cmd_halt <= 1'b1;
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cmd_halt <= 1'b1;
|
|
|
always @(posedge i_clk)
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always @(posedge i_clk)
|
if (i_rst)
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if (i_rst)
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| Line 233... |
Line 264... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if (dbg_cmd_write)
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if (dbg_cmd_write)
|
cmd_addr <= dbg_idata[5:0];
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cmd_addr <= dbg_idata[5:0];
|
|
|
wire cpu_reset;
|
wire cpu_reset;
|
assign cpu_reset = (cmd_reset)||(wdt_reset);
|
assign cpu_reset = (cmd_reset)||(wdt_reset)||(i_rst);
|
|
|
wire cpu_halt, cpu_dbg_stall;
|
wire cpu_halt, cpu_dbg_stall;
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assign cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
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assign cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
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wire [31:0] pic_data;
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wire [31:0] pic_data;
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wire [31:0] cmd_data;
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wire [31:0] cmd_data;
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| Line 278... |
Line 309... |
sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
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sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
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sys_data,
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sys_data,
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wdt_ack, wdt_stall, wdt_data, wdt_reset);
|
wdt_ack, wdt_stall, wdt_data, wdt_reset);
|
|
|
//
|
//
|
// The Flash Cache, a pre-read cache to memory that can be used to
|
// Position two ... unclaimed / unused
|
// create a fast memory access area
|
|
//
|
//
|
wire cache_int;
|
wire cache_stall;
|
wire [31:0] cache_data;
|
assign cache_stall = 1'b0;
|
wire cache_stb, cache_ack, cache_stall;
|
reg cache_ack;
|
wire fc_cyc, fc_stb, fc_we, fc_ack, fc_stall;
|
always @(posedge i_clk)
|
wire [31:0] fc_data, fc_addr;
|
cache_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == 5'h02);
|
flashcache #(10) manualcache(i_clk,
|
|
sys_cyc, cache_stb,
|
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((sys_stb)&&(sys_addr == `CACHECTRL)),
|
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sys_we, cpu_addr[9:0], sys_data,
|
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cache_ack, cache_stall, cache_data,
|
|
// Need the outgoing CACHE wishbone bus
|
|
fc_cyc, fc_stb, fc_we, fc_addr, fc_data,
|
|
fc_ack, fc_stall, ext_idata,
|
|
// Cache interrupt, for upon completion
|
|
cache_int);
|
|
|
|
|
|
// Counters -- for performance measurement and accounting
|
// Counters -- for performance measurement and accounting
|
//
|
//
|
// Here's the stuff we'll be counting ....
|
// Here's the stuff we'll be counting ....
|
//
|
//
|
wire cpu_op_stall, cpu_pf_stall, cpu_i_count;
|
wire cpu_op_stall, cpu_pf_stall, cpu_i_count;
|
|
|
|
`ifdef INCLUDE_ACCOUNTING_COUNTERS
|
//
|
//
|
// The master counters will, in general, not be reset. They'll be used
|
// The master counters will, in general, not be reset. They'll be used
|
// for an overall counter.
|
// for an overall counter.
|
//
|
//
|
// Master task counter
|
// Master task counter
|
wire mtc_ack, mtc_stall, mtc_int;
|
wire mtc_ack, mtc_stall, mtc_int;
|
wire [31:0] mtc_data;
|
wire [31:0] mtc_data;
|
zipcounter mtask_ctr(i_clk, (~cmd_halt), sys_cyc,
|
zipcounter mtask_ctr(i_clk, (~cpu_halt), sys_cyc,
|
(sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
|
(sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
|
sys_we, sys_data,
|
sys_we, sys_data,
|
mtc_ack, mtc_stall, mtc_data, mtc_int);
|
mtc_ack, mtc_stall, mtc_data, mtc_int);
|
|
|
// Master Operand Stall counter
|
// Master Operand Stall counter
|
| Line 347... |
Line 366... |
// be reset any time a task is given control of the CPU.
|
// be reset any time a task is given control of the CPU.
|
//
|
//
|
// User task counter
|
// User task counter
|
wire utc_ack, utc_stall, utc_int;
|
wire utc_ack, utc_stall, utc_int;
|
wire [31:0] utc_data;
|
wire [31:0] utc_data;
|
zipcounter utask_ctr(i_clk,(~cmd_halt), sys_cyc,
|
zipcounter utask_ctr(i_clk,(~cpu_halt), sys_cyc,
|
(sys_stb)&&(sys_addr == `USER_TASK_CTR),
|
(sys_stb)&&(sys_addr == `USER_TASK_CTR),
|
sys_we, sys_data,
|
sys_we, sys_data,
|
utc_ack, utc_stall, utc_data, utc_int);
|
utc_ack, utc_stall, utc_data, utc_int);
|
|
|
// User Op-Stall counter
|
// User Op-Stall counter
|
| Line 391... |
Line 410... |
: ((mic_ack) ? mic_data
|
: ((mic_ack) ? mic_data
|
: ((utc_ack) ? utc_data
|
: ((utc_ack) ? utc_data
|
: ((uoc_ack) ? uoc_data
|
: ((uoc_ack) ? uoc_data
|
: ((upc_ack) ? upc_data
|
: ((upc_ack) ? upc_data
|
: uic_data)))))));
|
: uic_data)))))));
|
|
`else // INCLUDE_ACCOUNTING_COUNTERS
|
|
reg actr_ack;
|
|
wire actr_stall;
|
|
wire [31:0] actr_data;
|
|
assign actr_stall = 1'b0;
|
|
assign actr_data = 32'h0000;
|
|
|
|
wire utc_int, uoc_int, upc_int, uic_int;
|
|
wire mtc_int, moc_int, mpc_int, mic_int;
|
|
assign mtc_int = 1'b0;
|
|
assign moc_int = 1'b0;
|
|
assign mpc_int = 1'b0;
|
|
assign mic_int = 1'b0;
|
|
assign utc_int = 1'b0;
|
|
assign uoc_int = 1'b0;
|
|
assign upc_int = 1'b0;
|
|
assign uic_int = 1'b0;
|
|
|
|
always @(posedge i_clk)
|
|
actr_ack <= (sys_stb)&&(sys_addr[4:3] == 2'b01);
|
|
`endif // INCLUDE_ACCOUNTING_COUNTERS
|
|
|
|
//
|
|
// The DMA Controller
|
|
//
|
|
wire dmac_int, dmac_stb, dc_err;
|
|
wire [31:0] dmac_data;
|
|
wire dmac_ack, dmac_stall;
|
|
wire dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
|
|
wire [31:0] dc_data, dc_addr;
|
|
wire cpu_gbl_cyc;
|
|
assign dmac_stb = (sys_stb)&&(sys_addr[4]);
|
|
wbdmac dma_controller(i_clk,
|
|
sys_cyc, dmac_stb, sys_we,
|
|
sys_addr[1:0], sys_data,
|
|
dmac_ack, dmac_stall, dmac_data,
|
|
// Need the outgoing DMAC wishbone bus
|
|
dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
|
|
dc_ack, dc_stall, ext_idata, dc_err,
|
|
// External device interrupts
|
|
{ {(32-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int },
|
|
// DMAC interrupt, for upon completion
|
|
dmac_int,
|
|
// Whether or not the CPU wants the bus
|
|
cpu_gbl_cyc);
|
|
|
|
|
|
`ifdef INCLUDE_ACCOUNTING_COUNTERS
|
//
|
//
|
// Counter Interrupt controller
|
// Counter Interrupt controller
|
//
|
//
|
reg ctri_ack;
|
reg ctri_ack;
|
wire ctri_stall, ctri_int, ctri_sel;
|
wire ctri_stall, ctri_int, ctri_sel;
|
| Line 408... |
Line 472... |
utc_int, uoc_int, upc_int, uic_int };
|
utc_int, uoc_int, upc_int, uic_int };
|
icontrol #(8) ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
|
icontrol #(8) ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
|
sys_data, ctri_data, ctri_vector, ctri_int);
|
sys_data, ctri_data, ctri_vector, ctri_int);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
ctri_ack <= ctri_sel;
|
ctri_ack <= ctri_sel;
|
|
assign ctri_stall = 1'b0;
|
|
`else // INCLUDE_ACCOUNTING_COUNTERS
|
|
reg ctri_ack;
|
|
wire ctri_stall, ctri_int;
|
|
wire [31:0] ctri_data;
|
|
assign ctri_stall = 1'b0;
|
|
assign ctri_data = 32'h0000;
|
|
assign ctri_int = 1'b0;
|
|
|
|
always @(posedge i_clk)
|
|
ctri_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
|
|
`endif // INCLUDE_ACCOUNTING_COUNTERS
|
|
|
|
|
//
|
//
|
// Timer A
|
// Timer A
|
//
|
//
|
| Line 456... |
Line 532... |
// The programmable interrupt controller peripheral
|
// The programmable interrupt controller peripheral
|
//
|
//
|
wire pic_interrupt;
|
wire pic_interrupt;
|
wire [(5+EXTERNAL_INTERRUPTS):0] int_vector;
|
wire [(5+EXTERNAL_INTERRUPTS):0] int_vector;
|
assign int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
|
assign int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
|
jif_int, cache_int };
|
jif_int, dmac_int };
|
icontrol #(6+EXTERNAL_INTERRUPTS) pic(i_clk, cpu_reset,
|
icontrol #(6+EXTERNAL_INTERRUPTS) pic(i_clk, cpu_reset,
|
(sys_cyc)&&(sys_stb)&&(sys_we)
|
(sys_cyc)&&(sys_stb)&&(sys_we)
|
&&(sys_addr==`INTCTRL),
|
&&(sys_addr==`INTCTRL),
|
sys_data, pic_data,
|
sys_data, pic_data,
|
int_vector, pic_interrupt);
|
int_vector, pic_interrupt);
|
|
wire pic_stall;
|
|
assign pic_stall = 1'b0;
|
reg pic_ack;
|
reg pic_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
|
pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
|
|
|
//
|
//
|
// The CPU itself
|
// The CPU itself
|
//
|
//
|
wire cpu_cyc, cpu_stb, cpu_we, cpu_dbg_we;
|
wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
|
|
cpu_we, cpu_dbg_we;
|
wire [31:0] cpu_data, wb_data;
|
wire [31:0] cpu_data, wb_data;
|
wire cpu_ack, cpu_stall;
|
wire cpu_ack, cpu_stall, cpu_err;
|
wire [31:0] cpu_dbg_data;
|
wire [31:0] cpu_dbg_data;
|
assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
|
assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
|
&&(dbg_we)&&(dbg_addr));
|
&&(dbg_we)&&(dbg_addr));
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zipcpu #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
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zipcpu #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
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cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
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cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
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dbg_idata, cpu_dbg_stall, cpu_dbg_data,
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dbg_idata, cpu_dbg_stall, cpu_dbg_data,
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cpu_dbg_cc, cpu_break,
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cpu_dbg_cc, cpu_break,
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cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data,
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cpu_gbl_cyc, cpu_gbl_stb,
|
|
cpu_lcl_cyc, cpu_lcl_stb,
|
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cpu_we, cpu_addr, cpu_data,
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cpu_ack, cpu_stall, wb_data,
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cpu_ack, cpu_stall, wb_data,
|
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cpu_err,
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cpu_op_stall, cpu_pf_stall, cpu_i_count);
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cpu_op_stall, cpu_pf_stall, cpu_i_count);
|
|
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// Now, arbitrate the bus ... first for the local peripherals
|
// Now, arbitrate the bus ... first for the local peripherals
|
assign sys_cyc = (cpu_cyc)||((cpu_halt)&&(~cpu_dbg_stall)&&(dbg_cyc));
|
// For the debugger to have access to the local system bus, the
|
assign sys_stb = (cpu_cyc)
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// following must be true:
|
? ((cpu_stb)&&(cpu_addr[31:4] == 28'hc000000))
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// (dbg_cyc) The debugger must request the bus
|
|
// (~cpu_lcl_cyc) The CPU cannot be using it (CPU gets priority)
|
|
// (dbg_addr) The debugger must be requesting its data
|
|
// register, not just the control register
|
|
// and one of two other things. Either
|
|
// ((cpu_halt)&&(~cpu_dbg_stall)) the CPU is completely halted,
|
|
// or
|
|
// (~cmd_addr[5]) we are trying to read a CPU register
|
|
// while in motion. Let the user beware that,
|
|
// by not waiting for the CPU to fully halt,
|
|
// his results may not be what he expects.
|
|
//
|
|
wire sys_dbg_cyc = ((dbg_cyc)&&(~cpu_lcl_cyc)&&(dbg_addr))
|
|
&&(((cpu_halt)&&(~cpu_dbg_stall))
|
|
||(~cmd_addr[5]));
|
|
assign sys_cyc = (cpu_lcl_cyc)||(sys_dbg_cyc);
|
|
assign sys_stb = (cpu_lcl_cyc)
|
|
? (cpu_lcl_stb)
|
: ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
|
: ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
|
|
|
assign sys_we = (cpu_cyc) ? cpu_we : dbg_we;
|
assign sys_we = (cpu_lcl_cyc) ? cpu_we : dbg_we;
|
assign sys_addr= (cpu_cyc) ? cpu_addr[3:0] : cmd_addr[3:0];
|
assign sys_addr= (cpu_lcl_cyc) ? cpu_addr[4:0] : cmd_addr[4:0];
|
assign sys_data= (cpu_cyc) ? cpu_data : dbg_idata;
|
assign sys_data= (cpu_lcl_cyc) ? cpu_data : dbg_idata;
|
assign cache_stb=((cpu_cyc)&&(cpu_stb)&&(cpu_addr[31:16]==`CACHEBASE));
|
|
|
|
// Return debug response values
|
// Return debug response values
|
assign dbg_odata = (~dbg_addr)?cmd_data
|
assign dbg_odata = (~dbg_addr)?cmd_data
|
:((~cmd_addr[5])?cpu_dbg_data : wb_data);
|
:((~cmd_addr[5])?cpu_dbg_data : wb_data);
|
initial dbg_ack = 1'b0;
|
initial dbg_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
dbg_ack <= (dbg_cyc)&&(dbg_stb)&&
|
dbg_ack <= (dbg_cyc)&&(~dbg_stall);
|
((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));
|
assign dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr);
|
assign dbg_stall=(dbg_addr)&&(dbg_cyc)
|
|
&&((cpu_cyc)||((cmd_halt)&&(~cpu_halt))
|
|
||(cpu_dbg_stall));
|
|
|
|
// Now for the external wishbone bus
|
// Now for the external wishbone bus
|
// Need to arbitrate between the flash cache and the CPU
|
// Need to arbitrate between the flash cache and the CPU
|
// The way this works, though, the CPU will stall once the flash
|
// The way this works, though, the CPU will stall once the flash
|
// cache gets access to the bus--the CPU will be stuck until the
|
// cache gets access to the bus--the CPU will be stuck until the
|
// flash cache is finished with the bus.
|
// flash cache is finished with the bus.
|
wire ext_cyc, ext_stb, ext_we;
|
wire ext_cyc, ext_stb, ext_we, ext_err;
|
wire cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall;
|
wire cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
|
|
cpu_ext_err;
|
wire [31:0] ext_addr, ext_odata;
|
wire [31:0] ext_addr, ext_odata;
|
wbarbiter #(32,32) flashvcpu(i_clk, i_rst,
|
wbpriarbiter #(32,32) dmacvcpu(i_clk, i_rst,
|
fc_addr, fc_data, fc_we, fc_stb, fc_cyc,
|
cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data,
|
fc_ack, fc_stall,
|
cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
|
cpu_addr, cpu_data, cpu_we,
|
dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
|
((cpu_stb)&&(~sys_stb)&&(~cache_stb)),
|
dc_ack, dc_stall, dc_err,
|
cpu_cyc, cpu_ext_ack, cpu_ext_stall,
|
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
|
ext_addr, ext_odata, ext_we, ext_stb,
|
ext_ack, ext_stall, ext_err);
|
ext_cyc, ext_ack, ext_stall);
|
|
|
|
`ifdef DELAY_EXT_BUS
|
`ifdef DELAY_EXT_BUS
|
busdelay #(32,32) extbus(i_clk,
|
busdelay #(32,32) extbus(i_clk,
|
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
|
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
|
ext_ack, ext_stall, ext_idata,
|
ext_ack, ext_stall, ext_idata, ext_err,
|
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
|
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
|
i_wb_ack, i_wb_stall, i_wb_data);
|
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err);
|
`else
|
`else
|
assign o_wb_cyc = ext_cyc;
|
assign o_wb_cyc = ext_cyc;
|
assign o_wb_stb = ext_stb;
|
assign o_wb_stb = ext_stb;
|
assign o_wb_we = ext_we;
|
assign o_wb_we = ext_we;
|
assign o_wb_addr = ext_addr;
|
assign o_wb_addr = ext_addr;
|
assign o_wb_data = ext_odata;
|
assign o_wb_data = ext_odata;
|
assign ext_ack = i_wb_ack;
|
assign ext_ack = i_wb_ack;
|
assign ext_stall = i_wb_stall;
|
assign ext_stall = i_wb_stall;
|
assign ext_idata = i_wb_data;
|
assign ext_idata = i_wb_data;
|
|
assign ext_err = i_wb_err;
|
`endif
|
`endif
|
|
|
wire tmr_ack;
|
wire tmr_ack;
|
assign tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
|
assign tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
|
wire [31:0] tmr_data;
|
wire [31:0] tmr_data;
|
assign tmr_data = (tma_ack)?tma_data
|
assign tmr_data = (tma_ack)?tma_data
|
:(tmb_ack ? tmb_data
|
:(tmb_ack ? tmb_data
|
:(tmc_ack ? tmc_data
|
:(tmc_ack ? tmc_data
|
:jif_data));
|
:jif_data));
|
assign wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
|
assign wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
|
:((actr_ack|cache_ack)?((actr_ack)?actr_data:cache_data)
|
:((actr_ack|dmac_ack)?((actr_ack)?actr_data:dmac_data)
|
:((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
|
:((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
|
:(ext_idata)));
|
:(ext_idata)));
|
|
|
assign cpu_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
|
assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
|
| wdt_stall | cache_stall
|
| wdt_stall | ctri_stall | actr_stall
|
| cpu_ext_stall);
|
| pic_stall | dmac_stall | cache_stall);
|
assign cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack);
|
assign cpu_stall = (sys_stall)|(cpu_ext_stall);
|
|
assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|cache_ack);
|
|
assign cpu_ack = (sys_ack)||(cpu_ext_ack);
|
|
assign cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
|
|
|
assign o_ext_int = (cmd_halt) && (~cpu_stall);
|
assign o_ext_int = (cmd_halt) && (~cpu_stall);
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
