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[/] [zipcpu/] [trunk/] [sim/] [verilator/] [memsim.h] - Diff between revs 204 and 209

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//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU core
// Project:     Zip CPU -- a small, lightweight, RISC CPU core
//
//
// Purpose:     This creates a memory like device to act on a WISHBONE bus.
// Purpose:     This creates a memory like device to act on a WISHBONE bus.
//              It doesn't exercise the bus thoroughly, but does give some
//              It doesn't exercise the bus thoroughly, but does give some
//              exercise to the bus to see whether or not the bus master
//      exercise to the bus to see whether or not the bus master can control it.
//              can control it.
 
//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
// You should have received a copy of the GNU General Public License along
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
// <http://www.gnu.org/licenses/> for a copy.
//
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html

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