///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: pfcache_tb.cpp
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// Filename: pfcache_tb.cpp
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: Bench testing for the prefetch cache used within the ZipCPU
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// Purpose: Bench testing for the prefetch cache used within the ZipCPU
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// when it is in pipelind mode. Whether or not this module is
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// when it is in pipelind mode. Whether or not this module is
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// used depends upon how the CPU is set up in cpudefs.v.
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// used depends upon how the CPU is set up in cpudefs.v.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#include <signal.h>
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#include <signal.h>
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#include <time.h>
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#include <time.h>
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#include <unistd.h>
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#include <unistd.h>
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#include <assert.h>
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#include <assert.h>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <ctype.h>
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#include <ctype.h>
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#include "verilated.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include "verilated_vcd_c.h"
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#include "Vpfcache.h"
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#include "Vpfcache.h"
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#include "testb.h"
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#include "testb.h"
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#include "cpudefs.h"
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#include "cpudefs.h"
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#include "memsim.h"
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#include "memsim.h"
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#define RAMBASE (1<<20)
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#define RAMBASE (1<<20)
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#define RAMWORDS RAMBASE
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#define RAMWORDS RAMBASE
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#define MAXTIMEOUT 128
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#define MAXTIMEOUT 128
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FILE *gbl_dbgfp = NULL; // Can also be set to stdout
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FILE *gbl_dbgfp = NULL; // Can also be set to stdout
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class PFCACHE_TB : public TESTB<Vpfcache> {
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class PFCACHE_TB : public TESTB<Vpfcache> {
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public:
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public:
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MEMSIM m_mem;
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MEMSIM m_mem;
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bool m_bomb;
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bool m_bomb;
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// Nothing special to do in a startup.
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// Nothing special to do in a startup.
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PFCACHE_TB(void) : m_mem(RAMWORDS), m_bomb(false) {}
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PFCACHE_TB(void) : m_mem(RAMWORDS), m_bomb(false) {}
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void randomize_memory(void) {
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void randomize_memory(void) {
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m_mem.load("/dev/urandom");
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m_mem.load("/dev/urandom");
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}
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}
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// ~CPUOPS_TB(void) {}
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// ~CPUOPS_TB(void) {}
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//
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//
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// Calls TESTB<>::reset to reset the core. Makes sure the i_ce line
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// Calls TESTB<>::reset to reset the core. Makes sure the i_ce line
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// is low during this reset.
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// is low during this reset.
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//
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//
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void reset(void) {
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void reset(void) {
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m_core->i_rst = 0;
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m_core->i_reset = 0;
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m_core->i_pc = RAMBASE;
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m_core->i_pc = RAMBASE<<2;
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m_core->i_new_pc = 0;
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m_core->i_new_pc = 0;
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m_core->i_clear_cache = 1;
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m_core->i_clear_cache = 1;
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m_core->i_stall_n = 1;
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m_core->i_stall_n = 1;
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m_core->i_stall_n = 1;
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m_core->i_stall_n = 1;
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TESTB<Vpfcache>::reset();
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TESTB<Vpfcache>::reset();
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}
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}
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//
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//
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// dbgdump();
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// dbgdump();
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//
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//
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void dbgdump(void) {
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void dbgdump(void) {
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/*
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/*
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char outstr[2048], *s;
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char outstr[2048], *s;
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sprintf(outstr, "Tick %4ld %s%s ",
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sprintf(outstr, "Tick %4ld %s%s ",
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m_tickcount,
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m_tickcount,
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(m_core->i_rst)?"R":" ",
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(m_core->i_rst)?"R":" ",
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(m_core->i_ce)?"CE":" ");
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(m_core->i_ce)?"CE":" ");
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s = &outstr[strlen(outstr)];
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s = &outstr[strlen(outstr)];
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puts(outstr);
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puts(outstr);
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*/
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*/
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}
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}
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bool valid_mem(uint32_t addr) {
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bool valid_mem(uint32_t addr) {
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if (addr < RAMBASE)
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if (addr < RAMBASE)
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return false;
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return false;
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if (addr >= RAMBASE + RAMWORDS)
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if (addr >= RAMBASE + RAMWORDS)
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return false;
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return false;
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return true;
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return true;
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}
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}
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//
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//
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// tick()
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// tick()
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//
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//
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// Call this to step the module under test.
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// Call this to step the module under test.
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//
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//
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void tick(void) {
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void tick(void) {
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bool debug = false;
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bool debug = false;
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if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)) {
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if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)) {
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if (!valid_mem(m_core->o_wb_addr))
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if (!valid_mem(m_core->o_wb_addr))
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m_core->i_wb_err = 1;
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m_core->i_wb_err = 1;
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} else if (m_core->o_wb_stb) {
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} else if (m_core->o_wb_stb) {
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m_bomb = true;
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m_bomb = true;
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}
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}
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if (m_core->o_wb_we)
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if (m_core->o_wb_we)
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m_bomb = true;
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m_bomb = true;
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if (m_core->o_wb_data != 0)
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if (m_core->o_wb_data != 0)
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m_bomb = true;
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m_bomb = true;
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if (debug)
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if (debug)
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dbgdump();
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dbgdump();
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unsigned mask = (RAMBASE-1);
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unsigned mask = (RAMBASE-1);
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m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
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m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
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m_core->o_wb_addr & mask, m_core->o_wb_data, 0,
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m_core->o_wb_addr & mask, m_core->o_wb_data, 0,
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m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
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m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
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TESTB<Vpfcache>::tick();
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TESTB<Vpfcache>::tick();
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if (m_core->o_v) {
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if (m_core->o_valid) {
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uint32_t pc, insn;
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uint32_t pc, insn;
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pc = m_core->o_pc;
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pc = m_core->o_pc;
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insn = m_core->o_i;
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insn = m_core->o_insn;
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if (insn != m_mem[pc & (RAMWORDS-1)]) {
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if (insn != m_mem[(pc>>2) & (RAMWORDS-1)]) {
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fprintf(stderr, "ERR: PF[%08x] = %08x != %08x\n", pc,
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fprintf(stderr, "ERR: PF[%08x] = %08x != %08x\n", pc,
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insn, m_mem[pc & (RAMWORDS-1)]);
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insn, m_mem[(pc>>2) & (RAMWORDS-1)]);
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closetrace();
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closetrace();
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assert(insn == m_mem[pc & (RAMWORDS-1)]);
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assert(insn == m_mem[(pc>>2) & (RAMWORDS-1)]);
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}
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}
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}
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}
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}
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}
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//
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//
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// fetch_insn()
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// fetch_insn()
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//
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//
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void fetch_insn(void) {
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void fetch_insn(void) {
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uint32_t timeout = 0;
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uint32_t timeout = 0;
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if ((m_core->o_v)&&(m_core->i_stall_n))
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if ((m_core->o_valid)&&(m_core->i_stall_n))
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m_core->i_pc++;
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m_core->i_pc++;
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m_core->i_rst = 0;
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m_core->i_reset = 0;
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m_core->i_new_pc = 0;
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m_core->i_new_pc = 0;
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m_core->i_clear_cache = 0;
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m_core->i_clear_cache = 0;
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m_core->i_stall_n = 1;
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m_core->i_stall_n = 1;
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do {
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do {
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tick();
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tick();
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} while((!m_core->o_v)&&(!m_core->o_illegal)&&(timeout++ < MAXTIMEOUT));
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} while((!m_core->o_valid)&&(!m_core->o_illegal)&&(timeout++ < MAXTIMEOUT));
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if (timeout >= MAXTIMEOUT)
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if (timeout >= MAXTIMEOUT)
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m_bomb = true;
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m_bomb = true;
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}
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}
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//
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//
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// skip_fetch()
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// skip_fetch()
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//
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//
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void skip_fetch(void) {
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void skip_fetch(void) {
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uint32_t prevalid, insn;
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uint32_t prevalid, insn;
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if ((m_core->o_v)&&(m_core->i_stall_n))
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if ((m_core->o_valid)&&(m_core->i_stall_n))
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m_core->i_pc++;
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m_core->i_pc++;
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m_core->i_rst = 0;
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m_core->i_reset = 0;
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m_core->i_new_pc = 0;
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m_core->i_new_pc = 0;
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m_core->i_clear_cache = 0;
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m_core->i_clear_cache = 0;
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m_core->i_stall_n = 0;
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m_core->i_stall_n = 0;
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insn = m_core->o_i;
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insn = m_core->o_insn;
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prevalid= m_core->o_v;
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prevalid= m_core->o_valid;
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tick();
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tick();
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if (prevalid) {
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if (prevalid) {
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// if (!m_core->o_v) {
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// if (!m_core->o_valid) {
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// fprintf(stderr, "ERR: VALID dropped on stall!\n");
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// fprintf(stderr, "ERR: VALID dropped on stall!\n");
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// closetrace();
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// closetrace();
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// assert(m_core->o_v);
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// assert(m_core->o_valid);
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// }
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// }
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if (insn != m_core->o_i) {
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if (insn != m_core->o_insn) {
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fprintf(stderr, "ERR: VALID INSN CHANGED on stall!\n");
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fprintf(stderr, "ERR: VALID INSN CHANGED on stall!\n");
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closetrace();
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closetrace();
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assert(insn == m_core->o_i);
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assert(insn == m_core->o_insn);
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}
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}
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}
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}
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}
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}
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//
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//
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// jump
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// jump
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//
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//
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void jump(unsigned target) {
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void jump(unsigned target) {
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uint32_t timeout = 0;
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uint32_t timeout = 0;
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m_core->i_rst = 0;
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m_core->i_reset = 0;
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m_core->i_new_pc = 1;
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m_core->i_new_pc = 1;
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m_core->i_clear_cache = 0;
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m_core->i_clear_cache = 0;
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m_core->i_stall_n = 1;
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m_core->i_stall_n = 1;
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m_core->i_pc = target;
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m_core->i_pc = target;
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tick();
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tick();
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m_core->i_pc++;
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m_core->i_pc++;
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m_core->i_new_pc = 0;
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m_core->i_new_pc = 0;
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m_core->i_stall_n = 0;
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m_core->i_stall_n = 0;
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|
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while((!m_core->o_v)&&(timeout++ < MAXTIMEOUT))
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while((!m_core->o_valid)&&(timeout++ < MAXTIMEOUT))
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tick();
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tick();
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|
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if (timeout >= MAXTIMEOUT)
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if (timeout >= MAXTIMEOUT)
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m_bomb = true;
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m_bomb = true;
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if (m_core->o_v)
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if (m_core->o_valid)
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assert(m_core->o_pc == target);
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assert(m_core->o_pc == target);
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}
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}
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};
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};
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|
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void usage(void) {
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void usage(void) {
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printf("USAGE: pfcache_tb\n");
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printf("USAGE: pfcache_tb\n");
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printf("\n");
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printf("\n");
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}
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}
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|
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int main(int argc, char **argv) {
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int main(int argc, char **argv) {
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// Setup verilator
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// Setup verilator
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Verilated::commandArgs(argc, argv);
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Verilated::commandArgs(argc, argv);
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// Now, create a test bench.
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// Now, create a test bench.
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PFCACHE_TB *tb = new PFCACHE_TB();
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PFCACHE_TB *tb = new PFCACHE_TB();
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int rcode = EXIT_SUCCESS;
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int rcode = EXIT_SUCCESS;
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|
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tb->opentrace("pfcache.vcd");
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tb->opentrace("pfcache.vcd");
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tb->randomize_memory();
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tb->randomize_memory();
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|
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tb->jump(RAMBASE);
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tb->jump(RAMBASE<<2);
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|
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// Simulate running straight through code
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// Simulate running straight through code
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for(int i=0; i<130; i++) {
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for(int i=0; i<130; i++) {
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// printf("FETCH\n");
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// printf("FETCH\n");
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tb->fetch_insn();
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tb->fetch_insn();
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}
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}
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|
|
// Now, let's bounce around through the cache
|
// Now, let's bounce around through the cache
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for(int j=0; j<20; j++) {
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for(int j=0; j<20; j++) {
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tb->jump(RAMBASE+j);
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tb->jump((RAMBASE+j)<<2);
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for(int i=0; i<130; i++) {
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for(int i=0; i<130; i++) {
|
// printf("FETCH\n");
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// printf("FETCH\n");
|
tb->fetch_insn();
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tb->fetch_insn();
|
}
|
}
|
|
|
if (tb->m_bomb) {
|
if (tb->m_bomb) {
|
printf("TEST FAILURE!\n");
|
printf("TEST FAILURE!\n");
|
delete tb;
|
delete tb;
|
exit(EXIT_FAILURE);
|
exit(EXIT_FAILURE);
|
}
|
}
|
}
|
}
|
|
|
// Now, add in some CIS-type instructions
|
// Now, add in some CIS-type instructions
|
for(int i=0; i<130; i++) {
|
for(int i=0; i<130; i++) {
|
unsigned v = rand() & 0x0f;
|
unsigned v = rand() & 0x0f;
|
|
|
if ((v&3)==2) {
|
if ((v&3)==2) {
|
// printf("SKIP\n");
|
// printf("SKIP\n");
|
tb->skip_fetch();
|
tb->skip_fetch();
|
} else {
|
} else {
|
// printf("FETCH\n");
|
// printf("FETCH\n");
|
tb->fetch_insn();
|
tb->fetch_insn();
|
}
|
}
|
|
|
if (tb->m_bomb) {
|
if (tb->m_bomb) {
|
printf("TEST FAILURE!\n");
|
printf("TEST FAILURE!\n");
|
delete tb;
|
delete tb;
|
exit(EXIT_FAILURE);
|
exit(EXIT_FAILURE);
|
}
|
}
|
}
|
}
|
|
|
// Finally, try it all: stalls, CIS, and jumps
|
// Finally, try it all: stalls, CIS, and jumps
|
for(int i=0; i<10000; i++) {
|
for(int i=0; i<10000; i++) {
|
unsigned v = rand() & 0x0f;
|
unsigned v = rand() & 0x0f;
|
if (v == 0) {
|
if (v == 0) {
|
uint32_t target = rand() & (RAMWORDS-1);
|
uint32_t target = rand() & (RAMWORDS-1);
|
target += RAMBASE;
|
target += RAMBASE;
|
// printf("JUMP TO %08x\n", target);
|
// printf("JUMP TO %08x\n", target);
|
tb->jump(target);
|
tb->jump(target<<2);
|
} else if ((v & 3)==2) {
|
} else if ((v & 3)==2) {
|
// printf("SKIP\n");
|
// printf("SKIP\n");
|
tb->skip_fetch();
|
tb->skip_fetch();
|
} else {
|
} else {
|
// printf("FETCH\n");
|
// printf("FETCH\n");
|
tb->fetch_insn();
|
tb->fetch_insn();
|
}
|
}
|
|
|
if (tb->m_bomb) {
|
if (tb->m_bomb) {
|
printf("TEST FAILURE!\n");
|
printf("TEST FAILURE!\n");
|
delete tb;
|
delete tb;
|
exit(EXIT_FAILURE);
|
exit(EXIT_FAILURE);
|
}
|
}
|
}
|
}
|
|
|
printf("SUCCESS!\n");
|
printf("SUCCESS!\n");
|
exit(rcode);
|
exit(rcode);
|
}
|
}
|
|
|
|
|
