OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [gcc-zippatch.patch] - Diff between revs 103 and 111

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Rev 103 Rev 111
Line 44... Line 44...
+    unsupported_languages="$unsupported_languages fortran java"
+    unsupported_languages="$unsupported_languages fortran java"
+    ;;
+    ;;
 esac
 esac
 
 
 # If we aren't building newlib, then don't build libgloss, since libgloss
 # If we aren't building newlib, then don't build libgloss, since libgloss
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cgraphbuild.c gcc-5.3.0-zip/gcc/cgraphbuild.c
 
--- gcc-5.3.0-original/gcc/cgraphbuild.c        2015-01-09 15:18:42.000000000 -0500
 
+++ gcc-5.3.0-zip/gcc/cgraphbuild.c     2016-03-24 22:13:24.815287808 -0400
 
@@ -62,6 +62,13 @@
 
 #include "ipa-prop.h"
 
 #include "ipa-inline.h"
 
 
 
+#ifdef DO_ZIP_DEBUGS
 
+extern void zip_debug_rtx(const_rtx);
 
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
 
+#else
 
+#define        ZIP_DEBUG_LINE(STR,RTX)
 
+#endif
 
+
 
 /* Context of record_reference.  */
 
 struct record_reference_ctx
 
 {
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/common/config/zip/zip-common.c gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/common/config/zip/zip-common.c gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c
--- gcc-5.3.0-original/gcc/common/config/zip/zip-common.c       1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/common/config/zip/zip-common.c       1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c    2016-02-14 00:54:31.821055716 -0500
+++ gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c    2016-02-14 00:54:31.821055716 -0500
@@ -0,0 +1,52 @@
@@ -0,0 +1,52 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
Line 101... Line 118...
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table
+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table
+
+
+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;
+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h       2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h       2016-03-25 10:21:47.127775498 -0400
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h    2015-07-24 12:00:26.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h    2015-07-24 12:00:26.000000000 -0400
@@ -21,7 +21,7 @@
@@ -21,7 +21,7 @@
 #ifndef GCC_AARCH64_LINUX_H
 #ifndef GCC_AARCH64_LINUX_H
 #define GCC_AARCH64_LINUX_H
 #define GCC_AARCH64_LINUX_H
 
 
Line 113... Line 130...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
 
 
 #undef  ASAN_CC1_SPEC
 #undef  ASAN_CC1_SPEC
 #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
 #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h     2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h     2016-03-25 10:21:47.127775498 -0400
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h  2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h  2015-01-05 07:33:28.000000000 -0500
@@ -23,8 +23,8 @@
@@ -23,8 +23,8 @@
 #define EXTRA_SPECS \
 #define EXTRA_SPECS \
 { "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
 { "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
 
 
Line 127... Line 144...
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #elif DEFAULT_LIBC == LIBC_GLIBC
 #elif DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h      2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h      2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h   2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h   2015-01-05 07:33:28.000000000 -0500
@@ -68,8 +68,8 @@
@@ -68,8 +68,8 @@
    GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI.  */
    GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI.  */
 
 
 #undef  GLIBC_DYNAMIC_LINKER
 #undef  GLIBC_DYNAMIC_LINKER
Line 141... Line 158...
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
 #define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
 #define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
 
 
 #define GLIBC_DYNAMIC_LINKER \
 #define GLIBC_DYNAMIC_LINKER \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h       2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h       2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h    2015-06-23 05:26:54.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h    2015-06-23 05:26:54.000000000 -0400
@@ -62,7 +62,7 @@
@@ -62,7 +62,7 @@
 
 
 #define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
 #define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
 
 
Line 153... Line 170...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 #define LINUX_TARGET_LINK_SPEC  "%{h*} \
 #define LINUX_TARGET_LINK_SPEC  "%{h*} \
    %{static:-Bstatic} \
    %{static:-Bstatic} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
--- gcc-5.3.0-original/gcc/config/bfin/linux.h  2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/bfin/linux.h  2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -45,7 +45,7 @@
@@ -45,7 +45,7 @@
   %{shared:-G -Bdynamic} \
   %{shared:-G -Bdynamic} \
   %{!shared: %{!static: \
   %{!shared: %{!static: \
    %{rdynamic:-export-dynamic} \
    %{rdynamic:-export-dynamic} \
Line 165... Line 182...
+   -dynamic-linker /lib/ld-uClibc.so.0} \
+   -dynamic-linker /lib/ld-uClibc.so.0} \
    %{static}} -init __init -fini __fini"
    %{static}} -init __init -fini __fini"
 
 
 #undef TARGET_SUPPORTS_SYNC_CALLS
 #undef TARGET_SUPPORTS_SYNC_CALLS
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
--- gcc-5.3.0-original/gcc/config/cris/linux.h  2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/cris/linux.h  2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -102,7 +102,7 @@
@@ -102,7 +102,7 @@
 #undef CRIS_DEFAULT_CPU_VERSION
 #undef CRIS_DEFAULT_CPU_VERSION
 #define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
 #define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
 
 
Line 177... Line 194...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef CRIS_LINK_SUBTARGET_SPEC
 #undef CRIS_LINK_SUBTARGET_SPEC
 #define CRIS_LINK_SUBTARGET_SPEC \
 #define CRIS_LINK_SUBTARGET_SPEC \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h        2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h        2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h     2015-06-25 13:53:14.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h     2015-06-25 13:53:14.000000000 -0400
@@ -129,9 +129,9 @@
@@ -129,9 +129,9 @@
 #endif
 #endif
 
 
 #if FBSD_MAJOR < 6
 #if FBSD_MAJOR < 6
Line 192... Line 209...
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
 #endif
 #endif
 
 
 /* NOTE: The freebsd-spec.h header is included also for various
 /* NOTE: The freebsd-spec.h header is included also for various
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
--- gcc-5.3.0-original/gcc/config/frv/linux.h   2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/frv/linux.h   2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h        2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h        2015-01-05 07:33:28.000000000 -0500
@@ -34,7 +34,7 @@
@@ -34,7 +34,7 @@
 #define ENDFILE_SPEC \
 #define ENDFILE_SPEC \
   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
 
 
Line 204... Line 221...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "\
 #define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
--- gcc-5.3.0-original/gcc/config/i386/gnu.h    2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/i386/gnu.h    2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
@@ -22,7 +22,7 @@
@@ -22,7 +22,7 @@
 #define GNU_USER_LINK_EMULATION "elf_i386"
 #define GNU_USER_LINK_EMULATION "elf_i386"
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 #undef GNU_USER_DYNAMIC_LINKER
Line 216... Line 233...
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
 
 
 #undef STARTFILE_SPEC
 #undef STARTFILE_SPEC
 #if defined HAVE_LD_PIE
 #if defined HAVE_LD_PIE
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h      2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h      2015-01-05 07:33:28.000000000 -0500
@@ -22,6 +22,6 @@
@@ -22,6 +22,6 @@
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
 
 
Line 229... Line 246...
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h   2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h   2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h        2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h        2015-01-05 07:33:28.000000000 -0500
@@ -19,4 +19,4 @@
@@ -19,4 +19,4 @@
 <http://www.gnu.org/licenses/>.  */
 <http://www.gnu.org/licenses/>.  */
 
 
 #define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
 #define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
--- gcc-5.3.0-original/gcc/config/i386/linux64.h        2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/i386/linux64.h        2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h     2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h     2015-01-05 07:33:28.000000000 -0500
@@ -27,6 +27,6 @@
@@ -27,6 +27,6 @@
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64"
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
 
 
Line 251... Line 268...
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
--- gcc-5.3.0-original/gcc/config/i386/linux.h  2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/i386/linux.h  2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -20,4 +20,4 @@
@@ -20,4 +20,4 @@
 <http://www.gnu.org/licenses/>.  */
 <http://www.gnu.org/licenses/>.  */
 
 
 #define GNU_USER_LINK_EMULATION "elf_i386"
 #define GNU_USER_LINK_EMULATION "elf_i386"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
--- gcc-5.3.0-original/gcc/config/ia64/linux.h  2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/ia64/linux.h  2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -55,7 +55,7 @@
@@ -55,7 +55,7 @@
 /* Define this for shared library support because it isn't in the main
 /* Define this for shared library support because it isn't in the main
    linux.h file.  */
    linux.h file.  */
 
 
Line 272... Line 289...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "\
 #define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h      2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h      2015-01-05 07:33:28.000000000 -0500
@@ -32,4 +32,4 @@
@@ -32,4 +32,4 @@
 
 
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 #undef GNU_USER_DYNAMIC_LINKER
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h    2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h    2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
@@ -31,5 +31,4 @@
@@ -31,5 +31,4 @@
   while (0)
   while (0)
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 #undef GNU_USER_DYNAMIC_LINKER
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-
-
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
--- gcc-5.3.0-original/gcc/config/linux.h       2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/linux.h       2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/linux.h    2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/linux.h    2015-01-05 07:33:28.000000000 -0500
@@ -73,10 +73,10 @@
@@ -73,10 +73,10 @@
    GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
    GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
    GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
    GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
    supporting both 32-bit and 64-bit compilation.  */
    supporting both 32-bit and 64-bit compilation.  */
Line 309... Line 326...
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
 #define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
 #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h    2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h    2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
@@ -67,7 +67,7 @@
@@ -67,7 +67,7 @@
    %{shared:-shared} \
    %{shared:-shared} \
    %{symbolic:-Bsymbolic} \
    %{symbolic:-Bsymbolic} \
    %{rdynamic:-export-dynamic} \
    %{rdynamic:-export-dynamic} \
Line 321... Line 338...
+   -dynamic-linker /lib/ld-linux.so.2"
+   -dynamic-linker /lib/ld-linux.so.2"
 
 
 #define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
 #define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
 
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
--- gcc-5.3.0-original/gcc/config/m68k/linux.h  2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/m68k/linux.h  2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -71,7 +71,7 @@
@@ -71,7 +71,7 @@
    When the -shared link option is used a final link is not being
    When the -shared link option is used a final link is not being
    done.  */
    done.  */
 
 
Line 333... Line 350...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "-m m68kelf %{shared} \
 #define LINK_SPEC "-m m68kelf %{shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h    2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h    2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
@@ -28,7 +28,7 @@
@@ -28,7 +28,7 @@
 #undef TLS_NEEDS_GOT
 #undef TLS_NEEDS_GOT
 #define TLS_NEEDS_GOT 1
 #define TLS_NEEDS_GOT 1
 
 
Line 345... Line 362...
+#define DYNAMIC_LINKER "/lib/ld.so.1"
+#define DYNAMIC_LINKER "/lib/ld.so.1"
 #undef  SUBTARGET_EXTRA_SPECS
 #undef  SUBTARGET_EXTRA_SPECS
 #define SUBTARGET_EXTRA_SPECS \
 #define SUBTARGET_EXTRA_SPECS \
   { "dynamic_linker", DYNAMIC_LINKER }
   { "dynamic_linker", DYNAMIC_LINKER }
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
--- gcc-5.3.0-original/gcc/config/mips/linux.h  2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/mips/linux.h  2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -22,20 +22,20 @@
@@ -22,20 +22,20 @@
 #define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
 #define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
 
 
 #define GLIBC_DYNAMIC_LINKER32 \
 #define GLIBC_DYNAMIC_LINKER32 \
Line 375... Line 392...
+  "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
+  "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
 
 
 #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
 #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
 #define GNU_USER_DYNAMIC_LINKERN32 \
 #define GNU_USER_DYNAMIC_LINKERN32 \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h       2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h       2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h    2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h    2015-01-05 07:33:28.000000000 -0500
@@ -32,7 +32,7 @@
@@ -32,7 +32,7 @@
 #undef  ASM_SPEC
 #undef  ASM_SPEC
 #define ASM_SPEC ""
 #define ASM_SPEC ""
 
 
Line 387... Line 404...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef  LINK_SPEC
 #undef  LINK_SPEC
 #define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
 #define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h      2015-09-24 20:04:26.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h      2015-09-24 20:04:26.000000000 -0400
@@ -37,7 +37,7 @@
@@ -37,7 +37,7 @@
 /* Define this for shared library support because it isn't in the main
 /* Define this for shared library support because it isn't in the main
    linux.h file.  */
    linux.h file.  */
 
 
Line 399... Line 416...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "\
 #define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h      2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h      2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h   2015-03-09 19:18:57.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h   2015-03-09 19:18:57.000000000 -0400
@@ -357,14 +357,14 @@
@@ -357,14 +357,14 @@
 #undef LINK_OS_DEFAULT_SPEC
 #undef LINK_OS_DEFAULT_SPEC
 #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
 #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
 
 
Line 422... Line 439...
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #elif DEFAULT_LIBC == LIBC_GLIBC
 #elif DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h        2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h        2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h     2015-09-24 09:46:45.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h     2015-09-24 09:46:45.000000000 -0400
@@ -757,8 +757,8 @@
@@ -757,8 +757,8 @@
 
 
 #define LINK_START_LINUX_SPEC ""
 #define LINK_START_LINUX_SPEC ""
 
 
Line 436... Line 453...
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
 #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
--- gcc-5.3.0-original/gcc/config/s390/linux.h  2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/s390/linux.h  2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h       2015-05-11 03:14:10.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h       2015-05-11 03:14:10.000000000 -0400
@@ -60,8 +60,8 @@
@@ -60,8 +60,8 @@
 #define MULTILIB_DEFAULTS { "m31" }
 #define MULTILIB_DEFAULTS { "m31" }
 #endif
 #endif
 
 
Line 450... Line 467...
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
 
 
 #undef  LINK_SPEC
 #undef  LINK_SPEC
 #define LINK_SPEC \
 #define LINK_SPEC \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
--- gcc-5.3.0-original/gcc/config/sh/linux.h    2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/sh/linux.h    2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -43,7 +43,7 @@
@@ -43,7 +43,7 @@
 
 
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
 
 
Line 462... Line 479...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 #undef SUBTARGET_LINK_EMUL_SUFFIX
 #undef SUBTARGET_LINK_EMUL_SUFFIX
 #define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
 #define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h       2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h       2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h    2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h    2015-01-05 07:33:28.000000000 -0500
@@ -84,8 +84,8 @@
@@ -84,8 +84,8 @@
    When the -shared link option is used a final link is not being
    When the -shared link option is used a final link is not being
    done.  */
    done.  */
 
 
Line 485... Line 502...
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
   %{!shared: \
   %{!shared: \
     %{!static: \
     %{!static: \
       %{rdynamic:-export-dynamic} \
       %{rdynamic:-export-dynamic} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h      2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h      2015-01-05 07:33:28.000000000 -0500
@@ -83,7 +83,7 @@
@@ -83,7 +83,7 @@
    When the -shared link option is used a final link is not being
    When the -shared link option is used a final link is not being
    done.  */
    done.  */
 
 
Line 497... Line 514...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 #undef  LINK_SPEC
 #undef  LINK_SPEC
 #define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
 #define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
--- gcc-5.3.0-original/gcc/config/vax/linux.h   2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/vax/linux.h   2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h        2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h        2015-01-05 07:33:28.000000000 -0500
@@ -41,7 +41,7 @@
@@ -41,7 +41,7 @@
   %{!shared: \
   %{!shared: \
     %{!static: \
     %{!static: \
       %{rdynamic:-export-dynamic} \
       %{rdynamic:-export-dynamic} \
Line 509... Line 526...
+      -dynamic-linker /lib/ld.so.1} \
+      -dynamic-linker /lib/ld.so.1} \
     %{static:-static}}"
     %{static:-static}}"
 
 
 #undef  WCHAR_TYPE
 #undef  WCHAR_TYPE
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h        2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h        2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h     2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h     2015-01-05 07:33:28.000000000 -0500
@@ -44,7 +44,7 @@
@@ -44,7 +44,7 @@
   %{mlongcalls:--longcalls} \
   %{mlongcalls:--longcalls} \
   %{mno-longcalls:--no-longcalls}"
   %{mno-longcalls:--no-longcalls}"
 
 
Line 659... Line 676...
+       # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+       # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+
+
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
--- gcc-5.3.0-original/gcc/config/zip/zip.c     1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip.c     1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c  2016-03-08 04:27:14.906499512 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c  2016-03-24 21:28:04.199373113 -0400
@@ -0,0 +1,2175 @@
@@ -0,0 +1,2324 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   zip.c
+// Filename:   zip.c
+//
+//
+// Project:    Zip CPU backend for the GNU Compiler Collection
+// Project:    Zip CPU backend for the GNU Compiler Collection
Line 771... Line 788...
+static bool    zip_scalar_mode_supported_p(enum machine_mode mode);
+static bool    zip_scalar_mode_supported_p(enum machine_mode mode);
+static bool    zip_libgcc_floating_mode_supported_p(enum machine_mode mode);
+static bool    zip_libgcc_floating_mode_supported_p(enum machine_mode mode);
+static int     zip_address_cost(rtx addr, enum machine_mode mode, addr_space_t as, bool spd);
+static int     zip_address_cost(rtx addr, enum machine_mode mode, addr_space_t as, bool spd);
+static bool    zip_mode_dependent_address_p(const_rtx addr, addr_space_t);
+static bool    zip_mode_dependent_address_p(const_rtx addr, addr_space_t);
+static unsigned HOST_WIDE_INT  zip_const_anchor = 0x20000;
+static unsigned HOST_WIDE_INT  zip_const_anchor = 0x20000;
 
+static          HOST_WIDE_INT  zip_min_opb_imm = -0x200000;
 
+static          HOST_WIDE_INT  zip_max_opb_imm =  0x1fffff;
+static          HOST_WIDE_INT  zip_min_anchor_offset = -0x20000;
+static          HOST_WIDE_INT  zip_min_anchor_offset = -0x20000;
+static          HOST_WIDE_INT  zip_max_anchor_offset =  0x1ffff;
+static          HOST_WIDE_INT  zip_max_anchor_offset =  0x1ffff;
+static          HOST_WIDE_INT  zip_min_mov_offset = -0x1000;
+static          HOST_WIDE_INT  zip_min_mov_offset = -0x1000;
+static          HOST_WIDE_INT  zip_max_mov_offset =  0x0fff;
+static          HOST_WIDE_INT  zip_max_mov_offset =  0x0fff;
+static int     zip_sched_issue_rate(void) { return 1; }
+static int     zip_sched_issue_rate(void) { return 1; }
Line 782... Line 801...
+static bool    zip_legitimate_move_operand_p(machine_mode, rtx, bool);
+static bool    zip_legitimate_move_operand_p(machine_mode, rtx, bool);
+       void    zip_debug_rtx_pfx(const char *, const_rtx x);
+       void    zip_debug_rtx_pfx(const char *, const_rtx x);
+       void    zip_debug_rtx(const_rtx x);
+       void    zip_debug_rtx(const_rtx x);
+static void    zip_override_options(void);
+static void    zip_override_options(void);
+static bool    zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
+static bool    zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
+// static      void    zip_canonicalize_comparison(int *, rtx *, rtx *, bool);
 
+static int     zip_memory_move_cost(machine_mode, reg_class_t, bool);
+static int     zip_memory_move_cost(machine_mode, reg_class_t, bool);
 
+static rtx     zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
+
+
+
+
+#define        ALL_DEBUG_OFF   false
+#define        ALL_DEBUG_OFF   false
+#define        ALL_DEBUG_ON    false
+#define        ALL_DEBUG_ON    false
+
+
Line 906... Line 925...
+                       assemble_name(file, buf);
+                       assemble_name(file, buf);
+#endif
+#endif
+                       }
+                       }
+                       break;
+                       break;
+               case PLUS:
+               case PLUS:
+                       if (!REG_P(XEXP(x, 0)))
+                       if (!REG_P(XEXP(x, 0))) {
 
+                               fprintf(stderr, "Unsupported address construct\n");
 
+                               zip_debug_rtx(x);
+                               abort();
+                               abort();
+                       if (CONST_INT_P(XEXP(x, 1))) {
+                       } if (CONST_INT_P(XEXP(x, 1))) {
+                               if (INTVAL(XEXP(x,1))!=0) {
+                               if (INTVAL(XEXP(x,1))!=0) {
+                                       fprintf(file, "%ld(%s)",
+                                       fprintf(file, "%ld(%s)",
+                                       INTVAL(XEXP(x, 1)),
+                                       INTVAL(XEXP(x, 1)),
+                                       reg_names[REGNO(XEXP(x, 0))]);
+                                       reg_names[REGNO(XEXP(x, 0))]);
+                               } else {
+                               } else {
Line 953... Line 974...
+               // of memory space.
+               // of memory space.
+               case MEM:
+               case MEM:
+                       if (dbg) zip_debug_rtx(x);
+                       if (dbg) zip_debug_rtx(x);
+                       zip_print_operand_address(file, XEXP(x, 0));
+                       zip_print_operand_address(file, XEXP(x, 0));
+                       break;
+                       break;
 
+               case CONST_INT:
 
+                       fprintf(file, "%ld",INTVAL(x));
 
+                       break;
+               default:
+               default:
 
+                       fprintf(stderr, "Unknown address format\n");
 
+                       zip_debug_rtx(x);
+                       abort(); break;
+                       abort(); break;
+                       // output_addr_const(file, x);
+                       // output_addr_const(file, x);
+               break;
+               break;
+       }
+       }
+}
+}
Line 1521... Line 1547...
+       ccr = get_attr_ccresult(insn);
+       ccr = get_attr_ccresult(insn);
+       if (ccr == CCRESULT_UNKNOWN) {
+       if (ccr == CCRESULT_UNKNOWN) {
+               CC_STATUS_INIT;
+               CC_STATUS_INIT;
+               if (dbg) fprintf(stderr, "\tINIT-CC\n");
+               if (dbg) fprintf(stderr, "\tINIT-CC\n");
+               return;
+               return;
+       } else if (ccr == CCRESULT_UNCHANGED) {
 
+               if (dbg) fprintf(stderr, "\tUnchanged CC\n");
 
+               return;
 
+       }
+       }
+
+
+       if ((GET_CODE(exp) == PARALLEL)&&(GET_CODE(XVECEXP(exp, 0, 0))==SET)) {
+       if ((GET_CODE(exp) == PARALLEL)&&(GET_CODE(XVECEXP(exp, 0, 0))==SET)) {
+               // This works up and until we add cc0 parallel instructions
+               // This works up and until we add cc0 parallel instructions
+               // to our instruction set.
+               // to our instruction set.
Line 1542... Line 1565...
+               // expression ...?
+               // expression ...?
+               if (dbg) fprintf(stderr, "Non-set expression, doesn\'t touch condition codes\n");
+               if (dbg) fprintf(stderr, "Non-set expression, doesn\'t touch condition codes\n");
+               return;
+               return;
+       }
+       }
+
+
 
+
 
+       if (ccr == CCRESULT_UNCHANGED) {
 
+               if (dbg) fprintf(stderr, "\tUnchanged CC\n");
 
+
 
+               // We can't just run away here ... even though the CC result
 
+               // hasn't changed, GCC's ability to recognize it as a valid
 
+               // result has changed.  In other words, if we just 'set' a
 
+               // value contained within either value1 or value2, then we'll
 
+               // need to update those values so that they are no longer looked
 
+               // upon as potentially containing the current CC values.
 
+
 
+               if (dest) {
 
+                       if (dest == cc0_rtx)
 
+                               CC_STATUS_INIT;
 
+                       else if ((REG_P(dest))&&(dest != pc_rtx)) {
 
+                               // An example here might be a load instruction
 
+                               if (reg_mentioned_p(dest, cc_status.value1))
 
+                                       cc_status.value1 = NULL_RTX;
 
+                               if (reg_mentioned_p(dest, cc_status.value2))
 
+                                       cc_status.value2 = NULL_RTX;
 
+                       }
 
+               }
 
+               return;
 
+       }
 
+
+       // Gotta wait on this test, until we know whether or not the
+       // Gotta wait on this test, until we know whether or not the
+       // conditionally executed instruction was designed to set the
+       // conditionally executed instruction was designed to set the
+       // CC0 register.
+       // CC0 register.
+       conditionally_executed = get_attr_conditional(insn);
+       conditionally_executed = get_attr_conditional(insn);
+       if ((conditionally_executed == CONDITIONAL_YES)&&(dest != cc0_rtx)) {
+       if ((conditionally_executed == CONDITIONAL_YES)&&(dest != cc0_rtx)) {
+               // cc_status is unchanged
+               // cc_status is unchanged
 
+               // However, GCC's vision of it may have changed
 
+               //
 
+               // Initialize CC_STATUS
+               if (dbg) fprintf(stderr, "\tCC -- unchanged (conditional exec)\n");
+               if (dbg) fprintf(stderr, "\tCC -- unchanged (conditional exec)\n");
 
+               CC_STATUS_INIT;
 
+               return;
 
+       } else if (GET_CODE(src)==IF_THEN_ELSE) {
 
+               // Same thing as above
 
+               CC_STATUS_INIT;
+               return;
+               return;
+       }
+       }
+
+
+       if (ccr == CCRESULT_VALIDZN)
+       if (ccr == CCRESULT_VALIDZN)
+               cc_status.flags = CC_NO_OVERFLOW;
+               cc_status.flags = CC_NO_OVERFLOW;
Line 1863... Line 1919...
+               for(tmp_rtx = as_a <const rtx_insn *>(x); tmp_rtx != 0; tmp_rtx = NEXT_INSN(tmp_rtx)) {
+               for(tmp_rtx = as_a <const rtx_insn *>(x); tmp_rtx != 0; tmp_rtx = NEXT_INSN(tmp_rtx)) {
+                       zip_debug_rtx_1(tmp_rtx, lvl+1);
+                       zip_debug_rtx_1(tmp_rtx, lvl+1);
+               }}
+               }}
+               */
+               */
+               zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
+               zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
+               debug_rtx(x);
 
+               zip_debug_print(pfx, lvl, ")");
+               zip_debug_print(pfx, lvl, ")");
+               break;
+               break;
+       case JUMP_INSN: zip_debug_print(pfx, lvl, "(JUMP-INSN");
+       case JUMP_INSN: zip_debug_print(pfx, lvl, "(JUMP-INSN");
 
+               zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
 
+               zip_debug_print(pfx, lvl, ")");
 
+               /*
+               if (JUMP_LABEL(x)) {
+               if (JUMP_LABEL(x)) {
+                       zip_debug_print(pfx, lvl+1, "(w/Label)");
+                       if (GET_CODE(JUMP_LABEL(x)) == LABEL_REF) {
 
+                               char    buf[64];
 
+                               sprintf(buf, "(LABEL *.L%d))", CODE_LABEL_NUMBER(LABEL_REF_LABEL(JUMP_LABEL(x))));
 
+                               zip_debug_print(pfx, lvl+1, buf);
 
+                       } else if (GET_CODE(JUMP_LABEL(x))==CODE_LABEL) {
 
+                               char    buf[64];
 
+                               sprintf(buf, "(CODE_LABEL *.L%d))", CODE_LABEL_NUMBER(JUMP_LABEL(x)));
 
+                               zip_debug_print(pfx, lvl+1, buf);
 
+                       } else
 
+                       zip_debug_print(pfx, lvl+1, "(w/Label))");
+               } else
+               } else
+                       zip_debug_print(pfx, lvl+1, "(NO label)");
+                       zip_debug_print(pfx, lvl+1, "(NO label))");
 
+               debug_rtx(x);
 
+               */
+               break;
+               break;
+       case CALL:
+       case CALL:
+               zip_debug_print(pfx, lvl, "(CALL (Adr) (Args)");
+               zip_debug_print(pfx, lvl, "(CALL (Adr) (Args)");
+               zip_debug_rtx_1(pfx, XEXP(x,0), lvl+1);
+               zip_debug_rtx_1(pfx, XEXP(x,0), lvl+1);
+               zip_debug_rtx_1(pfx, XEXP(x,1), lvl+1);
+               zip_debug_rtx_1(pfx, XEXP(x,1), lvl+1);
Line 1898... Line 1967...
+       case UNSPEC: zip_debug_print(pfx, lvl, "(UNSPEC)"); break;
+       case UNSPEC: zip_debug_print(pfx, lvl, "(UNSPEC)"); break;
+       case UNSPEC_VOLATILE: zip_debug_print(pfx, lvl, "(UNSPEC_VOLATILE)"); break;
+       case UNSPEC_VOLATILE: zip_debug_print(pfx, lvl, "(UNSPEC_VOLATILE)"); break;
+       case CODE_LABEL:
+       case CODE_LABEL:
+               {
+               {
+                       char    buf[64];
+                       char    buf[64];
+                       sprintf(buf, "(CODE_LABEL %d)", CODE_LABEL_NUMBER(x));
+                       sprintf(buf, "(CODE_LABEL *.L%d)", CODE_LABEL_NUMBER(x));
+                       zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
+                       zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
+               } break;
+               } break;
+       case SET:
+       case SET:
+               zip_debug_print_m(pfx, lvl, "(SET", GET_MODE(x));
+               zip_debug_print_m(pfx, lvl, "(SET", GET_MODE(x));
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
Line 1945... Line 2014...
+               zip_debug_print(pfx, lvl, "(COMPARE");
+               zip_debug_print(pfx, lvl, "(COMPARE");
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
+               zip_debug_print(pfx, lvl, ")");
+               zip_debug_print(pfx, lvl, ")");
+               break;
+               break;
 
+       case CONST:
 
+               zip_debug_print_m(pfx, lvl, "(CONST", GET_MODE(x));
 
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
 
+               zip_debug_print(pfx, lvl, ")");
 
+               break;
+       case CONST_INT:
+       case CONST_INT:
+               { char buf[25];
+               { char buf[25];
+               if (GET_MODE(x)==SImode)
+               if (GET_MODE(x)==SImode)
+                       sprintf(buf, "(CONST:SI %ld)", INTVAL(x));
+                       sprintf(buf, "(CONST_INT:SI %ld)", INTVAL(x));
+               else if (GET_MODE(x)==VOIDmode)
+               else if (GET_MODE(x)==VOIDmode)
+                       sprintf(buf, "(CONST:V %ld)", INTVAL(x));
+                       sprintf(buf, "(CONST_INT:V %ld)", INTVAL(x));
+               else
+               else
+                       sprintf(buf, "(CONST:? %ld)", INTVAL(x));
+                       sprintf(buf, "(CONST_INT:? %ld)", INTVAL(x));
+               zip_debug_print(pfx, lvl, buf);
+               zip_debug_print(pfx, lvl, buf);
+               } break;
+               } break;
+       case LABEL_REF:
+       case LABEL_REF:
+               zip_debug_print(pfx, lvl, "(LABEL)");
+               { char buf[256], *bp;
 
+               sprintf(buf, "(LABEL *.L%d)", CODE_LABEL_NUMBER(LABEL_REF_LABEL(x)));
 
+               zip_debug_print(pfx, lvl, buf);
 
+               }
+               break;
+               break;
+       case SYMBOL_REF:
+       case SYMBOL_REF:
+               {
+               {
+                       char buf[64];
+                       char buf[64];
+                       sprintf(buf, "(SYMBOL: %s)", XSTR(x,0));
+                       sprintf(buf, "(SYMBOL: %s)", XSTR(x,0));
Line 2081... Line 2158...
+       case SCRATCH:   //
+       case SCRATCH:   //
+               zip_debug_print_m(pfx, lvl, "(SCRATCH)", GET_MODE(x));
+               zip_debug_print_m(pfx, lvl, "(SCRATCH)", GET_MODE(x));
+               break;
+               break;
+       case SUBREG:
+       case SUBREG:
+               { char buf[25];
+               { char buf[25];
 
+               if (REG_P(XEXP(x,0))) {
+               sprintf(buf, "(SUBREG %d/%d)", REGNO(XEXP(x,0)),
+               sprintf(buf, "(SUBREG %d/%d)", REGNO(XEXP(x,0)),
+                       SUBREG_BYTE(x));
+                       SUBREG_BYTE(x));
+               zip_debug_print(pfx, lvl, buf);
+               zip_debug_print(pfx, lvl, buf);
+               } break;
+               } else if (MEM_P(XEXP(x,0))) {
 
+                       sprintf(buf, "(SUBREG /%d", SUBREG_BYTE(x));
 
+                       zip_debug_print(pfx, lvl, buf);
 
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
 
+                       zip_debug_print(pfx, lvl, ")");
 
+               } else {
 
+                       sprintf(buf, "(SUBREG UNK /%d", SUBREG_BYTE(x));
 
+                       zip_debug_print(pfx, lvl, buf);
 
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
 
+                       zip_debug_print(pfx, lvl, ")");
 
+               }}
 
+               break;
+       default:
+       default:
+               { char buf[25];
+               { char buf[128];
+               sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
+               sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
+               zip_debug_print(pfx, lvl, buf);
+               zip_debug_print(pfx, lvl, buf);
+               debug_rtx(x);
+               debug_rtx(x);
+               } break;
+               } break;
+       }
+       }
Line 2121... Line 2210...
+       }
+       }
+}
+}
+
+
+
+
+static bool
+static bool
+zip_legitimate_operand_address(const_rtx x, bool strict)
+zip_legitimate_opb(const_rtx x, bool strict)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS\n");
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
+       if (dbg) zip_debug_rtx_pfx("Test: ", x);
+       if (dbg) zip_debug_rtx_pfx("Test: ", x);
+
+
+       /*
 
+        * While this might seem to make sense, it sends GCC into an infinite
 
+        * loop.
 
+        *
 
+       if (GET_CODE(x) == MEM) {
 
+               return (zip_legitimate_operand_address(XEXP(x,0),strict));
 
+       }
 
+       */
 
+
 
+       /*
 
+       if (MEM_P(x)) {
 
+               if((REG_P(XEXP(x,0)))||(GET_CODE(XEXP(x,0))==PLUS))
 
+                       return (zip_legitimate_operand_address(XEXP(x,0),strict));
 
+       } else
 
+       */
 
+
 
+       if (NULL_RTX == x)
+       if (NULL_RTX == x)
+               return false;
+               return false;
+       else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode))
+       else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode))
+               return false;
+               return false;
+       else if (REG_P(x)) {
+       else if (REG_P(x)) {
 
+               bool    res;
 
+               // Only insist the register b a valid register if strict is true
 
+               res = (!strict)||((is_ZIP_REG(REGNO(x)))&&(REGNO(x) != zip_CC));
 
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> %s (Reg)\n",
 
+                       (res)?"YES!":"No");
 
+               return res;
 
+       } else if ((!strict)&&(SUBREG_P(x))) {
+               // Only insist the register b a valid register if strict is true
+               // Only insist the register b a valid register if strict is true
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> YES! (Reg)\n");
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Subreg(Reg),recurse)\n");
+               return (!strict)||(REGNO(x) != zip_CC);
+               return zip_legitimate_opb(XEXP(x,0), strict);
 
+       } else if ((CONST_INT_P(x))
 
+               &&(INTVAL(x) >= zip_min_opb_imm)
 
+               &&(INTVAL(x) <= zip_max_opb_imm)) {
 
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (Const)\n");
 
+               return true;
+       } else if (GET_CODE(x) == PLUS) {
+       } else if (GET_CODE(x) == PLUS) {
+               // Is it a valid register?
+               // Is it a valid register?
+               /*
 
+               if (GET_CODE(XEXP(x,0))==PLUS) {
 
+                       return (zip_legitimate_operand_address(XEXP(XEXP(x,0),0), strict))
 
+                               &&(zip_const_address_operand(XEXP(XEXP(x,0),1)));
 
+               } */
 
+               if(!REG_P(XEXP(x,0))) {
+               if(!REG_P(XEXP(x,0))) {
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> No (No reg in +%s)\n",
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
+                       return false;
+                       return false;
+               } if ((strict)&&(REGNO(XEXP(x,0)) == zip_CC)) {
+               } if ((strict)&&((!is_ZIP_REG(REGNO(XEXP(x,0))))||(REGNO(XEXP(x,0)) == zip_CC))) {
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> No (Wrong reg in +, %d)\n", REGNO(XEXP(x,0)));
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (Wrong reg in +, %d)\n", REGNO(XEXP(x,0)));
+                       return false;
+                       return false;
+               } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
+               } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
+                       &&(INTVAL(XEXP(x, 1)) <= zip_max_anchor_offset)
+                       &&(INTVAL(XEXP(x, 1)) <= zip_max_anchor_offset)
+                       &&(INTVAL(XEXP(x, 1)) >= zip_min_anchor_offset)) {
+                       &&(INTVAL(XEXP(x, 1)) >= zip_min_anchor_offset)) {
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> YES! (reg+int)\n");
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (reg+int)\n");
+                       // if((INTVAL(XEXP(x,1))<0)&&(REGNO(XEXP(x,0))==zip_SP))
+                       // if((INTVAL(XEXP(x,1))<0)&&(REGNO(XEXP(x,0))==zip_SP))
+                               // gcc_unreachable();
+                               // gcc_unreachable();
+                       return true;
+                       return true;
+               } if ((GET_CODE(XEXP(x, 1)) == LABEL_REF)
+               } if ((GET_CODE(XEXP(x, 1)) == LABEL_REF)
+                       ||(GET_CODE(XEXP(x, 1)) == SYMBOL_REF)) {
+                       ||(GET_CODE(XEXP(x, 1)) == SYMBOL_REF)) {
+                       // While we can technically support this, the problem
+                       // While we can technically support this, the problem
+                       // is that the symbol address could be anywhere, and we
+                       // is that the symbol address could be anywhere, and we
+                       // have no way of recovering if it's outside of our
+                       // have no way of recovering if it's outside of our
+                       // 14 allowable bits.
+                       // 14 allowable bits.
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> No. (reg+lbl)\n");
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No. (reg+lbl)\n");
+                       return false;
+                       return false;
+               } if ((GET_CODE(XEXP(x, 1)) == MINUS)
 
+                       &&((GET_CODE(XEXP(XEXP(x,1),0)) == LABEL_REF)
 
+                               ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT)
 
+                               ||(GET_CODE(XEXP(XEXP(x,1),0)) == SYMBOL_REF))
 
+                       &&((GET_CODE(XEXP(XEXP(x,1),1)) == LABEL_REF)
 
+                               ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT)
 
+                               ||(GET_CODE(XEXP(XEXP(x,1),1)) == SYMBOL_REF))
 
+                       &&((GET_CODE(XEXP(XEXP(x,1),0)))
 
+                               == (GET_CODE(XEXP(XEXP(x,1),1))))) {
 
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> YES! (lbl-lbl+reg)\n");
 
+                       return true;
 
+               }
+               }
 
+               // if ((GET_CODE(XEXP(x, 1)) == MINUS)
 
+               //      &&((GET_CODE(XEXP(XEXP(x,1),0)) == LABEL_REF)
 
+               //              ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT)
 
+               //              ||(GET_CODE(XEXP(XEXP(x,1),0)) == SYMBOL_REF))
 
+               //      &&((GET_CODE(XEXP(XEXP(x,1),1)) == LABEL_REF)
 
+               //              ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT)
 
+               //              ||(GET_CODE(XEXP(XEXP(x,1),1)) == SYMBOL_REF))
 
+               //      &&((GET_CODE(XEXP(XEXP(x,1),0)))
 
+               //              == (GET_CODE(XEXP(XEXP(x,1),1))))) {
 
+               //      if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> YES! (lbl-lbl+reg)\n");
 
+               //      return true;
 
+               //}
+       }
+       }
+
+
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> No\n");
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No\n");
+       if (dbg) zip_debug_rtx(x);
+       if (dbg) zip_debug_rtx(x);
+       return false;
+       return false;
+}
+}
+
+
+static bool
+static bool
Line 2212... Line 2293...
+       if (NULL_RTX == x)
+       if (NULL_RTX == x)
+               return false;
+               return false;
+       else if (REG_P(x)) {
+       else if (REG_P(x)) {
+               // Only insist the register b a valid register if strict is true
+               // Only insist the register b a valid register if strict is true
+               if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> YES! (Reg)\n");
+               if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> YES! (Reg)\n");
+               return (!strict)||(REGNO(x) != zip_CC);
+               return (!strict)||((is_ZIP_REG(REGNO(x)))&&(REGNO(x) !=zip_CC));
+       } else if (GET_CODE(x) == PLUS) {
+       } else if (GET_CODE(x) == PLUS) {
 
+               // if (GET_CODE(XEXP(x,0))==PLUS) {
 
+               // return (zip_legitimate_opb(XEXP(x,0), strict))
 
+               // &&(zip_const_address_operand(XEXP(x,0)));
 
+               // }
+               // Is it a valid register?
+               // Is it a valid register?
+               if (GET_CODE(XEXP(x,0))==PLUS) {
+               if(GET_CODE(XEXP(x,0)) != REG) {
+                       return (zip_legitimate_operand_address(XEXP(x,0), strict))
 
+                               &&(zip_const_address_operand(XEXP(x,0)));
 
+               } if(GET_CODE(XEXP(x,0)) != REG) {
 
+                       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No (No reg in +%s)\n",
+                       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No (No reg in +%s)\n",
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
+                       return false;
+                       return false;
+               } if ((strict)&&(REGNO(XEXP(x,0)) == zip_CC)) {
+               } if ((strict)&&
 
+                       ((!is_ZIP_REG(REGNO(XEXP(x,0))))
 
+                       ||(REGNO(XEXP(x,0)) == zip_CC))) {
+                       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No (Wrong reg in +, %d)\n", REGNO(XEXP(x,0)));
+                       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No (Wrong reg in +, %d)\n", REGNO(XEXP(x,0)));
+                       return false;
+                       return false;
+               } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
+               } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
+                       &&(INTVAL(XEXP(x, 1)) <= zip_max_mov_offset)
+                       &&(INTVAL(XEXP(x, 1)) <= zip_max_mov_offset)
+                       &&(INTVAL(XEXP(x, 1)) >= zip_min_mov_offset)) {
+                       &&(INTVAL(XEXP(x, 1)) >= zip_min_mov_offset)) {
Line 2248... Line 2332...
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOV(predicate) for OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOV(predicate) for OPERAND\n");
+       return zip_legitimate_move_operand_p(VOIDmode, op, !can_create_pseudo_p());
+       return zip_legitimate_move_operand_p(VOIDmode, op, !can_create_pseudo_p());
+}
+}
+
+
+int
+int
 
+zip_pd_mvimm_operand(rtx op)
 
+{
 
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
 
+
 
+       if (dbg) fprintf(stderr, "ZIP-VALID-MVIMM(predicate) for OPERAND\n");
 
+       if (!CONST_INT_P(op))
 
+               return false;
 
+       if (INTVAL(op) > zip_max_mov_offset)
 
+               return false;
 
+       if (INTVAL(op) < zip_min_mov_offset)
 
+               return false;
 
+       return true;
 
+}
 
+
 
+int
 
+zip_pd_imm_operand(rtx op)
 
+{
 
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
 
+
 
+       if (dbg) fprintf(stderr, "ZIP-VALID-IMM(predicate) for OPERAND\n");
 
+       if (!CONST_INT_P(op))
 
+               return false;
 
+       if (INTVAL(op) > zip_max_anchor_offset)
 
+               return false;
 
+       if (INTVAL(op) < zip_min_anchor_offset)
 
+               return false;
 
+       return true;
 
+}
 
+
 
+int
+zip_address_operand(rtx op)
+zip_address_operand(rtx op)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
+       return zip_legitimate_operand_address(op, !can_create_pseudo_p());
+       if ((REG_P(op))&&(REGNO(op)==zip_CC))
 
+               return false;
 
+       else if ((GET_CODE(op) == PLUS)&&(REG_P(XEXP(op,0)))
 
+                       &&(REGNO(XEXP(op,0))==zip_CC))
 
+               return false;
 
+       else
 
+               return zip_legitimate_opb(op, !can_create_pseudo_p());
+}
+}
+
+
+int
+int
+zip_pd_address_operand(rtx op)
+zip_pd_opb_operand(rtx op)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS(predicate) for OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
+       return zip_legitimate_operand_address(op, !can_create_pseudo_p());
+       return zip_legitimate_opb(op, !can_create_pseudo_p());
+}
+}
+
+
+int
+int
+zip_ct_address_operand(rtx op)
+zip_ct_address_operand(rtx op)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
+       return zip_legitimate_operand_address(op, !can_create_pseudo_p());
+       return zip_legitimate_opb(op, !can_create_pseudo_p());
+}
+}
+
+
+int
+int
+zip_const_address_operand(rtx x) {
+zip_const_address_operand(rtx x) {
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
Line 2331... Line 2451...
+
+
+       if (dbg) fprintf(stderr, "Zip-LEGITIMATE-ADDRESS-P\n");
+       if (dbg) fprintf(stderr, "Zip-LEGITIMATE-ADDRESS-P\n");
+       if (dbg) zip_debug_rtx(x);
+       if (dbg) zip_debug_rtx(x);
+
+
+       // Only insist the register be a valid register if strict is true
+       // Only insist the register be a valid register if strict is true
+       if (zip_legitimate_operand_address(x, strict))
+       if (zip_legitimate_opb(x, strict))
+               return true;
 
+       else if (zip_const_address_operand(x))
 
+               return true;
+               return true;
 
+       // else if (zip_const_address_operand(x))
 
+               // return true;
+
+
+       return false;
+       return false;
+}
+}
+
+
 
+static rtx
 
+zip_legitimize_address(rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) {
 
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
 
+
 
+       if (dbg) zip_debug_rtx_pfx("LEGITIMIZE: ", x);
 
+       if (zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
 
+               return x;
 
+
 
+       if (GET_CODE(x)==PLUS) {
 
+               if (!REG_P(XEXP(x,0)))
 
+                       XEXP(x,0) = force_reg(GET_MODE(x),XEXP(x,0));
 
+               if ((!zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
 
+                       &&(!CONST_INT_P(XEXP(x,1))))
 
+                       x = force_reg(GET_MODE(x),x);
 
+       } else if (MEM_P(x))
 
+               x = force_reg(GET_MODE(x),x);
 
+
 
+       if (dbg) zip_debug_rtx_pfx("LEGITIMATE: ", x);
 
+       return x;
 
+}
 
+
+void
+void
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
+{
+{
+       assemble_name(stream, name);
+       assemble_name(stream, name);
+       fprintf(stream, "\t.equ ");
+       fprintf(stream, "\t.equ ");
Line 2390... Line 2531...
+               } else return false;
+               } else return false;
+       } return false;
+       } return false;
+}
+}
+*/
+*/
+
+
+#define        SREG_P(RTX) ((REG_P(RTX))||(SUBREG_P(RTX)))
+#define        USE_SUBREG
 
+#ifdef USE_SUBREG
 
+#define        SREG_P(RTX) ((SUBREG_P(RTX))&&(REG_P(XEXP(RTX,0))))
 
+#define        SMEM_P(RTX) ((SUBREG_P(RTX))&&(MEM_P(XEXP(RTX,0))))
 
+#else
 
+#define        SREG_P(RTX)     false
 
+#define        SMEM_P(RTX)     false
 
+#endif
+
+
+bool   zip_gen_move_rtl(rtx dst, rtx src) {
+bool   zip_gen_move_rtl(rtx dst, rtx src) {
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE\n");
+       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE\n");
+       if (dbg) zip_debug_rtx_pfx("FROM: ", src);
+       if (dbg) zip_debug_rtx_pfx("FROM: ", src);
+       if (dbg) zip_debug_rtx_pfx("TO  : ", dst);
+       if (dbg) zip_debug_rtx_pfx("TO  : ", dst);
+       if (dbg) fprintf(stderr, "PSEUDOs: %s\n", can_create_pseudo_p()?"true":"false");
+       if (dbg) fprintf(stderr, "PSEUDOs: %s\n", can_create_pseudo_p()?"true":"false");
+       if ((SREG_P(dst))&&(SREG_P(src))) {
+       if (((REG_P(dst))||(SREG_P(dst)))
 
+                       &&((REG_P(src))||(SREG_P(src)))) {
+               // First type of move... register to register
+               // First type of move... register to register
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/REG -- EMIT\n");
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/REG -- EMIT\n");
 
+               // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
 
+               // if (SREG_P(src)) src = gen_raw_REG(SImode,REGNO(XEXP(src,0))+SUBREG_BYTE(src));
+               emit_insn(gen_movsi_reg(dst, src));
+               emit_insn(gen_movsi_reg(dst, src));
+       } else if ((MEM_P(dst))&&(MEM_P(XEXP(dst,0)))) {
+       } else if ((MEM_P(dst))&&(MEM_P(XEXP(dst,0)))) {
 
+               // An indirect store, (mem (mem (addr .))) = whatever ...
+               if (can_create_pseudo_p()) {
+               if (can_create_pseudo_p()) {
+                       rtx     tmp = gen_reg_rtx(Pmode);
+                       rtx     tmp = gen_reg_rtx(Pmode);
+                       zip_gen_move_rtl(tmp, XEXP(dst,0));
+                       zip_gen_move_rtl(tmp, XEXP(dst,0));
+                       // mark_reg_pointer(tmp,0);
+                       // mark_reg_pointer(tmp,0);
+                       zip_gen_move_rtl(gen_rtx_MEM(GET_MODE(src), tmp), src);
+                       zip_gen_move_rtl(gen_rtx_MEM(GET_MODE(src), tmp), src);
+               } else {
+               } else {
+                       fprintf(stderr, "ZIP:Cannot move into mem w/o pseudo\n");
+                       fprintf(stderr, "ZIP:Cannot move into mem w/o pseudo\n");
+                       return false;
+                       return false;
+               }
+               }
+       } else if ((MEM_P(src))&&(MEM_P(XEXP(src,0)))) {
+       } else if ((MEM_P(src))&&(MEM_P(XEXP(src,0)))) {
 
+               // If this is an indirect load, Rx = (mem (mem (addr)))
+               if (can_create_pseudo_p()) {
+               if (can_create_pseudo_p()) {
+                       rtx     tmp = gen_reg_rtx(Pmode);
+                       rtx     tmp = gen_reg_rtx(Pmode);
+                       zip_gen_move_rtl(tmp, XEXP(src,0));
+                       zip_gen_move_rtl(tmp, XEXP(src,0));
+                       // mark_reg_pointer(tmp,0);
+                       // mark_reg_pointer(tmp,0);
+                       zip_gen_move_rtl(dst, gen_rtx_MEM(GET_MODE(src), tmp));
+                       zip_gen_move_rtl(dst, gen_rtx_MEM(GET_MODE(src), tmp));
+               } else {
+               } else {
+                       fprintf(stderr, "ZIP: Cannot move from mem(mem(ptr)) w/o pseudo\n");
+                       fprintf(stderr, "ZIP: Cannot move from mem(mem(ptr)) w/o pseudo\n");
+                       return false;
+                       return false;
+               }
+               }
+       } else if ((SREG_P(dst))&&(GET_CODE(src)==PLUS)
+       } else if (((REG_P(dst))||(SREG_P(dst)))&&(GET_CODE(src)==PLUS)
+                       &&(REG_P(XEXP(src,0)))
+                       &&(REG_P(XEXP(src,0)))
+                       &&(CONST_INT_P(XEXP(src,1)))) {
+                       &&(CONST_INT_P(XEXP(src,1)))) {
 
+               // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
+               // Second type of move... register plus offset to register
+               // Second type of move... register plus offset to register
+               if ((INTVAL(XEXP(src, 1)) <= zip_max_mov_offset)
+               if ((INTVAL(XEXP(src, 1)) <= zip_max_mov_offset)
+                       &&(INTVAL(XEXP(src, 1)) >= zip_min_mov_offset)) {
+                       &&(INTVAL(XEXP(src, 1)) >= zip_min_mov_offset)) {
+                       // The offset is within bounds
+                       // The offset is within bounds
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/REG+OFF -- EMIT\n");
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/REG+OFF -- EMIT\n");
Line 2458... Line 2612...
+                       emit_insn(gen_movsi(dst, tmp));
+                       emit_insn(gen_movsi(dst, tmp));
+               } else {
+               } else {
+                       fprintf(stderr, "ZIP: Cannot move mem(A) to mem(B) w/o pseudo\n");
+                       fprintf(stderr, "ZIP: Cannot move mem(A) to mem(B) w/o pseudo\n");
+                       return false;
+                       return false;
+               }
+               }
+       } else if ((SREG_P(dst))&&(MEM_P(src))) {
+       } else if (((REG_P(dst))||(SREG_P(dst)))&&(MEM_P(src))) {
+               // Memory load
+               // Memory load
 
+               // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD\n");
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD\n");
+               if (zip_legitimate_operand_address(XEXP(src, 0), false)) {
+               if (zip_legitimate_opb(XEXP(src, 0), false)) {
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/SIMPLE-LOD(ADDR)\n");
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/SIMPLE-LOD(ADDR)\n");
+                       if (dbg) zip_debug_rtx_pfx("Smple-Addr: ", src);
+                       if (dbg) zip_debug_rtx_pfx("Smple-Addr: ", src);
+                       // if (REG_P(XEXP(src,0)))
 
+                               // mark_reg_pointer(XEXP(src,0),0);
 
+                       // else if ((GET_CODE(XEXP(src,0))==PLUS)
 
+                                       // &&(REG_P(XEXP(XEXP(src,0),0))))
 
+                               // mark_reg_pointer(XEXP(XEXP(src,0),0),0);
 
+                       emit_insn(gen_movsi_lod(dst, src));
+                       emit_insn(gen_movsi_lod(dst, src));
+               } else if (zip_const_address_operand(XEXP(src,0))) {
+               } else if (zip_const_address_operand(XEXP(src,0))) {
+                       if (can_create_pseudo_p()) {
+                       if (can_create_pseudo_p()) {
+                               rtx     tmp;
+                               rtx     tmp;
+                               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD(CONST-ADDR)\n");
+                               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD(CONST-ADDR)\n");
+                               tmp = gen_reg_rtx(Pmode);
+                               tmp = gen_reg_rtx(Pmode);
+                               emit_insn(gen_movsi_ldi(tmp, XEXP(src,0)));
+                               emit_insn(gen_movsi_ldi(tmp, XEXP(src,0)));
+                               // mark_reg_pointer(tmp,0);
 
+                               emit_insn(gen_movsi_lod(dst, gen_rtx_MEM(GET_MODE(src),tmp)));
+                               emit_insn(gen_movsi_lod(dst, gen_rtx_MEM(GET_MODE(src),tmp)));
+                       } else {
+                       } else {
+                               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD(CONST-ADDR,SELF)\n");
+                               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD(CONST-ADDR,SELF)\n");
+                               emit_insn(gen_movsi_ldi(dst, XEXP(src,0)));
+                               emit_insn(gen_movsi_ldi(dst, XEXP(src,0)));
+                               emit_insn(gen_movsi_lod(dst, gen_rtx_MEM(GET_MODE(src),dst)));
+                               emit_insn(gen_movsi_lod(dst, gen_rtx_MEM(GET_MODE(src),dst)));
+                       }
+                       }
+               } else {
+               } else {
+                       internal_error("%s", "ZIP/No usable load\n");
+                       internal_error("%s", "ZIP/No usable load\n");
+               }
+               }
+       } else if ((MEM_P(dst))&&(SREG_P(src))) {
+       } else if ((MEM_P(dst))&&((REG_P(src))||(SREG_P(src)))) {
+               // Memory store
+               // Memory store
 
+               // if (SREG_P(src)) src = gen_raw_REG(SImode,REGNO(XEXP(src,0))+SUBREG_BYTE(src));
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO\n");
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO\n");
+               if (zip_legitimate_operand_address(XEXP(dst, 0), false)) {
+               if (zip_legitimate_opb(XEXP(dst, 0), false)) {
+                       // If it's a legitimate address already, do nothing mor
+                       // If it's a legitimate address already, do nothing mor
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO(Legit Addr)--EMIT\n");
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO(Legit Addr)--EMIT\n");
+                       // if (REG_P(XEXP(dst,0)))
+                       // if (REG_P(XEXP(dst,0)))
+                               // mark_reg_pointer(XEXP(dst,0),0);
+                               // mark_reg_pointer(XEXP(dst,0),0);
+                       // else if ((GET_CODE(XEXP(dst,0))==PLUS)
+                       // else if ((GET_CODE(XEXP(dst,0))==PLUS)
Line 2542... Line 2692...
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->MEM -- DONE\n");
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->MEM -- DONE\n");
+               } else {
+               } else {
+                       fprintf(stderr, "ZIP/Cannot store constant into mem w/o pseudo\n");
+                       fprintf(stderr, "ZIP/Cannot store constant into mem w/o pseudo\n");
+                       return false;
+                       return false;
+               }
+               }
+       } else if ((SREG_P(dst))&&(CONST_INT_P(src))) {
+       } else if (((REG_P(dst))||(SREG_P(dst)))&&(CONST_INT_P(src))) {
 
+               // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
+               // Load a constant into a register
+               // Load a constant into a register
+               // The assembler really takes care of all of this, since
+               // The assembler really takes care of all of this, since
+               // the assembler will split the constant if it doesn't fit
+               // the assembler will split the constant if it doesn't fit
+               // into a single instruction.
+               // into a single instruction.
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->REG\n");
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->REG\n");
Line 2561... Line 2712...
+               // The assembler really takes care of all of this, since
+               // The assembler really takes care of all of this, since
+               // the assembler will split the constant if it doesn't fit
+               // the assembler will split the constant if it doesn't fit
+               // into a single instruction.
+               // into a single instruction.
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LABEL->REG\n");
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LABEL->REG\n");
+               emit_insn(gen_movsi_ldi(dst, src));
+               emit_insn(gen_movsi_ldi(dst, src));
 
+       } else if ((REG_P(dst))&&
 
+                       ((GET_CODE(src)==PLUS)
 
+                       &&((GET_CODE(XEXP(src,0))==SYMBOL_REF)
 
+                               ||(GET_CODE(XEXP(src,0))==LABEL_REF))
 
+                       &&(CONST_INT_P(XEXP(src,1))))) {
 
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LABEL+OFFSET->REG\n");
 
+               if ((INTVAL(XEXP(src,1))>=zip_min_mov_offset)
 
+                       &&(INTVAL(XEXP(src,1))<=zip_max_mov_offset)) {
 
+                       emit_insn(gen_movsi_ldi(dst, XEXP(src,1)));
 
+                       emit_insn(gen_movsi_reg_off(dst, dst, XEXP(src,1)));
 
+               } else if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(Pmode);
 
+                       emit_insn(gen_movsi_ldi(tmp, XEXP(src,1)));
 
+                       emit_insn(gen_movsi_ldi(dst, src));
 
+                       emit_insn(gen_addsi3(dst,dst,tmp));
 
+                       return true;
 
+               } else {
 
+                       fprintf(stderr, "Cannot move LABEL+OFFSET -> dst w/o pseudo\n");
 
+                       return false;
 
+               }
 
+       } else if (((REG_P(dst))||(SREG_P(dst)))&&(GET_CODE(src) == CONST)) {
 
+               // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
 
+               zip_gen_move_rtl(dst, XEXP(src,0));
 
+       } else if (SMEM_P(dst)) {
 
+               rtx     addr = XEXP(XEXP(dst,0),0);
 
+               if (REG_P(addr)) {
 
+                       zip_gen_move_rtl(
 
+                               gen_rtx_MEM(SImode, plus_constant(Pmode,addr,
 
+                                       SUBREG_BYTE(dst),false)),src);
 
+               } else if ((GET_CODE(addr)==PLUS)
 
+                               &&(REG_P(XEXP(addr,0)))
 
+                               &&(CONST_INT_P(XEXP(addr,1)))) {
 
+                       rtx addreg = XEXP(addr,0);
 
+                       zip_gen_move_rtl(
 
+                               gen_rtx_MEM(SImode, plus_constant(Pmode,addreg,
 
+                                       INTVAL(XEXP(addr,1))+SUBREG_BYTE(dst),
 
+                                       false)),src);
 
+               } else fprintf(stderr, "ZIP/Cannot understand SUBREG\n");
 
+       } else if (SMEM_P(src)) {
 
+               rtx     addr = XEXP(XEXP(src,0),0);
 
+               if (REG_P(addr)) {
 
+                       zip_gen_move_rtl(dst,
 
+                               gen_rtx_MEM(SImode, plus_constant(Pmode,addr,
 
+                                       SUBREG_BYTE(src),false)));
 
+               } else if ((GET_CODE(addr)==PLUS)
 
+                               &&(REG_P(XEXP(addr,0)))
 
+                               &&(CONST_INT_P(XEXP(addr,1)))) {
 
+                       rtx addreg = XEXP(addr,0);
 
+                       zip_gen_move_rtl(dst,
 
+                               gen_rtx_MEM(SImode, plus_constant(Pmode,addreg,
 
+                                       INTVAL(XEXP(addr,1))+SUBREG_BYTE(src),
 
+                                       false)));
 
+               } else fprintf(stderr, "ZIP/Cannot understand SUBREG\n");
+       } else {
+       } else {
+               fprintf(stderr, "ZIP/No usable move\n");
+               fprintf(stderr, "ZIP/No usable move\n");
+               zip_debug_rtx_pfx("TO  : ", dst);
+               zip_debug_rtx_pfx("TO  : ", dst);
+               zip_debug_rtx_pfx("FROM: ", src);
+               zip_debug_rtx_pfx("FROM: ", src);
+               debug_rtx(dst);
+               debug_rtx(dst);
Line 2681... Line 2885...
+                       return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "MOV", 3);
+                       return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "MOV", 3);
+               else if (zip_const_address_operand(iffalse))
+               else if (zip_const_address_operand(iffalse))
+                       return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LDI", 3);
+                       return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LDI", 3);
+               else if (zip_const_address_operand(iffalse))
+               else if (zip_const_address_operand(iffalse))
+                       return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LDI", 3);
+                       return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LDI", 3);
+               else if ((MEM_P(iffalse))&&(zip_legitimate_operand_address(XEXP(iffalse,0), true)))
+               else if ((MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true)))
+                       return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LOD", 3);
+                       return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LOD", 3);
+               else {
+               else {
+                       internal_error("MOVSICC Unsupported mode");
+                       internal_error("MOVSICC Unsupported mode");
+                       return NULL;
+                       return NULL;
+               }
+               }
Line 2695... Line 2899...
+                       return zip_binary_movsicc(GET_CODE(condition), "MOV",2);
+                       return zip_binary_movsicc(GET_CODE(condition), "MOV",2);
+               else if (zip_const_address_operand(iffalse))
+               else if (zip_const_address_operand(iffalse))
+                       return zip_binary_movsicc(GET_CODE(condition), "LDI",2);
+                       return zip_binary_movsicc(GET_CODE(condition), "LDI",2);
+               else if (zip_const_address_operand(iffalse))
+               else if (zip_const_address_operand(iffalse))
+                       return zip_binary_movsicc(GET_CODE(condition), "LDI",2);
+                       return zip_binary_movsicc(GET_CODE(condition), "LDI",2);
+               else if ((MEM_P(iffalse))&&(zip_legitimate_operand_address(XEXP(iffalse,0), true)))
+               else if ((MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true)))
+                       return zip_binary_movsicc(GET_CODE(condition), "LOD",2);
+                       return zip_binary_movsicc(GET_CODE(condition), "LOD",2);
+               else {
+               else {
+                       internal_error("MOVSICC Unsupported mode");
+                       internal_error("MOVSICC Unsupported mode");
+                       return NULL;
+                       return NULL;
+               }
+               }
Line 2716... Line 2920...
+                       &&(zip_legitimate_move_operand_p(SImode, iffalse, true))) {
+                       &&(zip_legitimate_move_operand_p(SImode, iffalse, true))) {
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A+B ELSE C+D\n");
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A+B ELSE C+D\n");
+               return zip_tertiary_movsicc(condition, "MOV", "MOV");
+               return zip_tertiary_movsicc(condition, "MOV", "MOV");
+       }
+       }
+       if ((MEM_P(iftrue))
+       if ((MEM_P(iftrue))
+               &&(zip_legitimate_operand_address(XEXP(iftrue,0), true))
+               &&(zip_legitimate_opb(XEXP(iftrue,0), true))
+               &&(zip_legitimate_move_operand_p(SImode, iffalse, true))) {
+               &&(zip_legitimate_move_operand_p(SImode, iffalse, true))) {
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE C+D\n");
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE C+D\n");
+               return zip_tertiary_movsicc(condition, "LOD", "MOV");
+               return zip_tertiary_movsicc(condition, "LOD", "MOV");
+       } if ((zip_legitimate_move_operand_p(SImode, iftrue, true))
+       } if ((zip_legitimate_move_operand_p(SImode, iftrue, true))
+               &&(MEM_P(iffalse))&&(zip_legitimate_operand_address(XEXP(iffalse,0), true))) {
+               &&(MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true))) {
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A+B ELSE C[D]\n");
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A+B ELSE C[D]\n");
+               return zip_tertiary_movsicc(condition, "MOV", "LOD");
+               return zip_tertiary_movsicc(condition, "MOV", "LOD");
+       } if ((MEM_P(iftrue))&&(zip_legitimate_operand_address(XEXP(iftrue,0), true))
+       } if ((MEM_P(iftrue))&&(zip_legitimate_opb(XEXP(iftrue,0), true))
+               &&(MEM_P(iffalse))&&(zip_legitimate_operand_address(XEXP(iffalse,0), true))) {
+               &&(MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true))) {
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE C[D]\n");
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE C[D]\n");
+               return zip_tertiary_movsicc(condition, "LOD", "LOD");
+               return zip_tertiary_movsicc(condition, "LOD", "LOD");
 
+       } if ((MEM_P(iftrue))
 
+               &&(zip_legitimate_opb(XEXP(iftrue,0),true))
 
+               &&(zip_const_address_operand(iffalse))) {
 
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE #x\n");
 
+               return zip_tertiary_movsicc(condition, "LOD", "LDI");
 
+       } if ((MEM_P(iffalse))
 
+               &&(zip_legitimate_opb(XEXP(iffalse,0),true))
 
+               &&(zip_const_address_operand(iftrue))) {
 
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) #x ELSE A[B]\n");
 
+               return zip_tertiary_movsicc(condition, "LDI", "LOD");
+       }
+       }
+
+
+       internal_error("MOVSICC Operands not supported");
+       internal_error("MOVSICC Operands not supported");
+}
+}
+
+
Line 2779... Line 2993...
+       }
+       }
+
+
+       return "BREAK";
+       return "BREAK";
+}
+}
+
+
+static void
 
+zip_canonicalize_comparison(int *code ATTRIBUTE_UNUSED, rtx *op0 ATTRIBUTE_UNUSED, rtx *op1 ATTRIBUTE_UNUSED, bool preserve_op0 ATTRIBUTE_UNUSED)
 
+{
 
+/*
 
+ * While I'd like to keep and have this code, it does absolutely nothing.  The
 
+ * code apparently only gets called on non-CC0 targets.
 
+ *
 
+ *
 
+       const bool      dbg = true;
 
+
 
+       if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
 
+       if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, cc0_rtx, const0_rtx));
 
+       if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
 
+       if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
 
+
 
+       if ((!preserve_op0)&&((*code == LE)||(*code == GTU)||(*code == GEU))) {
 
+               rtx tem = *op0;
 
+               *op0 = *op1;
 
+               *op1 = tem;
 
+               *code = (int)swap_condition((enum rtx_code)*code);
 
+       }
 
+
 
+       if ((*code == LE)||(*code == LEU)||(*code==GTU)) {
 
+               int     offset = (*code == GTU) ? 1 : -1;
 
+               bool    swap = false;
 
+               // A < B => A <= B-1
 
+               if (CONST_INT_P(*op1)) {
 
+                       *op1 = GEN_INT(INTVAL(*op1)+offset);
 
+                       swap = true;
 
+               } else if (REG_P(*op1)) {
 
+                       *op1 = plus_constant(SImode, *op1, offset, true);
 
+                       swap = true;
 
+               } else if ((GET_CODE(*op1)==PLUS)&&(CONST_INT_P(XEXP(*op1,1)))){
 
+                       *op1 = plus_constant(GET_MODE(*op1),XEXP(*op1,0),
 
+                                       INTVAL(XEXP(*op1,1))+offset);
 
+                       swap = true;
 
+               } if (swap) {
 
+                       if (*code == LE)
 
+                               (*code) = LT;
 
+                       else if (*code == LEU)
 
+                               (*code) = LTU;
 
+                       else // (*code) == GTU
 
+                               (*code) = GEU;
 
+               }
 
+       }
 
+*/
 
+}
 
+
 
+static int     zip_memory_move_cost(machine_mode mode, reg_class_t ATTRIBUTE_UNUSED, bool in ATTRIBUTE_UNUSED) {
+static int     zip_memory_move_cost(machine_mode mode, reg_class_t ATTRIBUTE_UNUSED, bool in ATTRIBUTE_UNUSED) {
+       int     rv = 14;
+       int     rv = 14;
+       if ((mode == DImode)||(mode == DFmode))
+       if ((mode == DImode)||(mode == DFmode))
+               rv += 2;
+               rv += 2;
+       return rv;
+       return rv;
Line 2838... Line 3004...
+
+
+// #warning "How do we tell the compiler LDI label is expensive as 2 ops"?
+// #warning "How do we tell the compiler LDI label is expensive as 2 ops"?
+
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
--- gcc-5.3.0-original/gcc/config/zip/zip.h     1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip.h     1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h  2016-03-07 20:19:32.623843475 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h  2016-03-19 12:03:33.888255495 -0400
@@ -0,0 +1,3707 @@
@@ -0,0 +1,3889 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   gcc/config/zip/zip.h
+// Filename:   gcc/config/zip/zip.h
+//
+//
+// Project:    Zip CPU backend for the GNU Compiler Collection
+// Project:    Zip CPU backend for the GNU Compiler Collection
Line 2904... Line 3070...
+//     Register  0 (may be) the return address pointer
+//     Register  0 (may be) the return address pointer
+// Registers 16-31 may only be used in supervisor mode.
+// Registers 16-31 may only be used in supervisor mode.
+#define        is_ZIP_GENERAL_REG(REGNO)       ((REGNO)<13)
+#define        is_ZIP_GENERAL_REG(REGNO)       ((REGNO)<13)
+#define        is_ZIP_REG(REGNO)               ((REGNO)<16)
+#define        is_ZIP_REG(REGNO)               ((REGNO)<16)
+
+
+#undef STARTFILE_SPEC
 
+#define        STARTFILE_SPEC  "_start"
 
+
 
+#undef ENDFILE_SPEC
 
+#define        ENDFILE_SPEC    ""
 
+
 
+#undef LIB_SPEC
 
+#define        LIB_SPEC        "%{!g:-lc} %{g:-lg} -lzip"
 
+
 
+// #define     zip_FP_PSEUDO   16
+// #define     zip_FP_PSEUDO   16
+#define        zip_PC          15
+#define        zip_PC          15
+#define        zip_CC          14
+#define        zip_CC          14
+#define        zip_SP          13
+#define        zip_SP          13
+#define        zip_FP          12
+#define        zip_FP          12
Line 2925... Line 3082...
+#define        zip_R1          1
+#define        zip_R1          1
+#define        zip_R0          0
+#define        zip_R0          0
+
+
+#define        ZIP_FIRST_ARG_REGNO     1
+#define        ZIP_FIRST_ARG_REGNO     1
+#define        ZIP_LAST_ARG_REGNO      5
+#define        ZIP_LAST_ARG_REGNO      5
+#define        NUM_ARG_REGS            5
+#define        NUM_ARG_REGS            (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
+#define        MAX_PARM_REGS           5
+#define        MAX_PARM_REGS           (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
+
+
+/* The overall framework of an assembler file */
+/* The overall framework of an assembler file */
+
+
+#undef ASM_SPEC
 
+#define        ASM_COMMENT_START       ";"
+#define        ASM_COMMENT_START       ";"
+#define        ASM_APP_ON              ""
+#define        ASM_APP_ON              ""
+#define        ASM_APP_OFF             ""
+#define        ASM_APP_OFF             ""
+
+
+#define        FILE_ASM_OP             "\t.file\n"
+#define        FILE_ASM_OP             "\t.file\n"
Line 3054... Line 3210...
+
+
+/* A C compound statement with a conditional 'goto LABEL;' executed if X
+/* A C compound statement with a conditional 'goto LABEL;' executed if X
+ * (an RTX) is a legitimate memory address on the target machine for a memory
+ * (an RTX) is a legitimate memory address on the target machine for a memory
+ * operand of mode MODE.
+ * operand of mode MODE.
+ */
+ */
 
+/* 17.03 Controlling the Compilation Driver, 'gcc' */
 
+// DRIVER_SELF_SPECS
 
+// OPTION_DEFAULT_SPECS
 
+// CPP_SPEC
 
+// CPLUSPLUS_CPP_SPEC
 
+// CC1_SPEC
 
+// CC1PLUS_SPEC
 
+/* ASM_SPEC ... A C string constant that tells the GCC driver program options
 
+ * to pass to the assembler.  It can also specify how to translate options you
 
+ * give to GCC into options for GCC to pass to the assembler.  See the file
 
+ * 'sun3.h' for an example of this.
 
+ *
 
+ * Do not define thismacro if it does not need to do anything.
 
+ */
 
+// #undef      ASM_SPEC
 
+// ASM_FINAL_SPEC
 
+// ASM_NEEDS_DASH_FOR_PIPED_INPUT
 
+
 
+/* LINK_SPEC ... A C string constant that tells the GCC driver program options
 
+ * to pass to the linker.  It can also specify how to translate options you give
 
+ * to GCC into options for GCC to pass to the linker.
 
+ *
 
+ * Do not define this macro if it does not need to do anything.
 
+ */
 
+
 
+/* LIB_SPEC ... Another C string constant very much like LINK_SPEC.  The
 
+ * difference between the two is that LIB_SPEC is used at the end of the
 
+ * command given to the linker.
 
+ *
 
+ * If this macro is not defined, a default is provided that loads the standard
 
+ * C library from the usual place.  See 'gcc.c'.
 
+ */
 
+#undef LIB_SPEC
 
+// #define     LIB_SPEC        "%{!g:-lc} %{g:-lg} -lzip"
 
+#define        LIB_SPEC        ""
 
+
 
+/* LIBGCC_SPEC ... Another C string constant that tells the GCC driver program
 
+ * hoow and when to place a reference to 'libgcc.a' into the linker command
 
+ * line.  This constant is placed both before and after the value of LIB_SPEC.
 
+ *
 
+ * If this macro is not defined, the GCC driver provides a default that passes
 
+ * the string '-lgcc' to the linker.
 
+ */
 
+#undef LIBGCC_SPEC
 
+#define        LIBGCC_SPEC     ""
 
+
 
+/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the
 
+ * LIBGCC_SPEC is not directly used by the driver program but is instead
 
+ * modified to refer to different versions of 'libgcc.a' depending on the
 
+ * values of the command line flags '-static', '-shared', '-static-libgcc',
 
+ * and '-shared-libgcc'.  On targets where these modifications are
 
+ * inappropriate, define REAL_LIBGCC_SPEC instead.  REAL_LIBGCC_SPEC tells the
 
+ * driver how to place a reference to 'libgcc' on the link command line, but
 
+ * unlike LIBGCC_SPEC, it is used unmodified.
 
+ */
 
+#define        REAL_LIBGCC_SPEC        ""
 
+
 
+// USE_LD_AS_NEEDED
 
+// LINK_EH_SPEC
 
+
 
+/* STARTFILE_SPEC ... Another C string constant used much like LINK_SPEC.  The
 
+ * difference between the two is that STARTFILE_SPEC is used at the very
 
+ * beginning of the command given to the linker.
 
+ *
 
+ * If this macro is not defined, a default is provided that loads the standard
 
+ * C startup file from the usual place.  See 'gcc.c'
 
+ */
 
+#undef STARTFILE_SPEC
 
+#define        STARTFILE_SPEC  ""
 
+
 
+/* ENDFILE_SPEC ... Another C string constant used much like LINK_SPEC.  The
 
+ * difference between the two is that ENDFILE_SPEC is used at the very end
 
+ * of the command given to the linker.
 
+ *
 
+ * Do not define this macro if it does not do anything.
 
+ */
 
+// #undef      ENDFILE_SPEC
 
+// #define     ENDFILE_SPEC    ""
 
+
 
+// THREAD_MODEL_SPEC
 
+// SYSROOT_SUFFIX_SPEC
 
+// SYSROOT_HEADERS_SUFFIX_SPEC
 
+// EXTRA_SPECS
 
+// LINK_LIBGCC_SPECIAL_1
 
+// LINK_GCC_C_SEQUENCE_SPEC
 
+// LINK_COMMAND_SPEC
 
+// TARGET_ALWAYS_STRIP_DOTDOT
 
+// MULTILIB_DEFAULTS
 
+// RELATIVE_PREFIX_NOT_LINKDIR
 
+// MD_EXEC_PREFIX
 
+// STANDARD_STARTFILE_PREFIX
 
+// STANDARD_STARTFILE_PREFIX_1
 
+// STANDARD_STARTFILE_PREFIX_2
 
+// MD_STARTFILE_PREFIX
 
+// MD_STARTFILE_PREFIX_1
 
+// INIT_ENVIRONMENT
 
+// LOCAL_INCLUDE_DIR
 
+#undef LOCAL_INCLUDE_DIR
 
+
 
+// NATIVE_SYSTEM_HEADER_COMPONENT
 
+// INCLUDE_DEFAULTS
 
+
+/* 17.03 Run-time Target Specification */
+/* 17.03 Run-time Target Specification */
+
+
+/* TARGET_CPU_CPP_BUILTINS() ... This function-like macro expands to a block of
+/* TARGET_CPU_CPP_BUILTINS() ... This function-like macro expands to a block of
+ * code that defines built-in preprocessor macros and assertions for the target
+ * code that defines built-in preprocessor macros and assertions for the target
+ * CPU, using the functions builtin_define, builtin_define_std, and
+ * CPU, using the functions builtin_define, builtin_define_std, and
Line 3799... Line 4057...
+ * base plus index register address.  You should define this macro if base plus
+ * base plus index register address.  You should define this macro if base plus
+ * index addresses have different requirements than other base register uses.
+ * index addresses have different requirements than other base register uses.
+ *
+ *
+ * Zip CPU does not support the base plus index addressing mode, thus ...
+ * Zip CPU does not support the base plus index addressing mode, thus ...
+ */
+ */
+#undef MODE_BASE_REG_REG_CLASS
+// #undef      MODE_BASE_REG_REG_CLASS
+#define        MODE_BASE_REG_REG_CLASS(MODE)   NO_REGS
+// #define     MODE_BASE_REG_REG_CLASS(MODE)   NO_REGS
+
+
+/* INDEX_REG_CLASS ... A macro whose definition is the name of the class to
+/* INDEX_REG_CLASS ... A macro whose definition is the name of the class to
+ * which a valid index register must belong.  An index register is one used in
+ * which a valid index register must belong.  An index register is one used in
+ * an address where its value is either multiplied by a scale factor or added
+ * an address where its value is either multiplied by a scale factor or added
+ * to another register (as well as added to a displacement).
+ * to another register (as well as added to a displacement).
Line 3824... Line 4082...
+# define REGNO_OK_FOR_BASE_P(NUM)      (NUM != zip_CC)
+# define REGNO_OK_FOR_BASE_P(NUM)      (NUM != zip_CC)
+#endif
+#endif
+
+
+/* REGNO_MODE_OK_FOR_BASE_P ... A C expressison that is just like
+/* REGNO_MODE_OK_FOR_BASE_P ... A C expressison that is just like
+ * REGNO_OK_FOR_BASE_P, except that that expression may examine the mode of the
+ * REGNO_OK_FOR_BASE_P, except that that expression may examine the mode of the
+ * memory refgerence in MODE.  You should define this macro if the mode of the
+ * memory reference in MODE.  You should define this macro if the mode of the
+ * memory reference affects whether a register may be used as a base register.
+ * memory reference affects whether a register may be used as a base register.
+ *
+ *
+ * ZipCPU --- the mode doesn't affect anything, so we don't define this.
+ * ZipCPU --- the mode doesn't affect anything, so we don't define this.
+ */
+ */
+
+
Line 3836... Line 4094...
+ * addresses, accessing memory in mode mode.
+ * addresses, accessing memory in mode mode.
+ *
+ *
+ * Use of this macro is deprecated.
+ * Use of this macro is deprecated.
+ */
+ */
+
+
+/* REGNO_MODE_CODE_OK_FRO_BASE_P(N,M,AS,OC,IC) ... A C expression which is
+/* REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) ... A C expression which is
+ * nonzero if a register number N is suitable for use as a base register in
+ * nonzero if a register number N is suitable for use as a base register in
+ * operand addresses, accessing memory in mode M in address space AS.  This is
+ * operand addresses, accessing memory in mode M in address space AS.  This is
+ * similar to REGNO_MODE_OK_FOR_BASE_P, except that the expression may examine
+ * similar to REGNO_MODE_OK_FOR_BASE_P, except that the expression may examine
+ * the context in which the register appears in the memory reference.
+ * the context in which the register appears in the memory reference.
+ *
+ *
Line 3849... Line 4107...
+#define        REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) REGNO_OK_FOR_BASE_P(N)
+#define        REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) REGNO_OK_FOR_BASE_P(N)
+
+
+/* REGNO_OK_FOR_INDEX_P(REGNO) ... A C expression which is nonzero if register
+/* REGNO_OK_FOR_INDEX_P(REGNO) ... A C expression which is nonzero if register
+ * num is suitable for use as an index register in opernad addressess.  It may
+ * num is suitable for use as an index register in opernad addressess.  It may
+ * be either a suitable hard register or a pseudo register that has been
+ * be either a suitable hard register or a pseudo register that has been
+ * allocated usch as a hard register.
+ * allocated such as a hard register.
+ *
+ *
+ * ZipCPU has no index registers, therefore we declare this to be zero.
+ * ZipCPU has no index registers, therefore we declare this to be zero.
+ */
+ */
+#undef REGNO_OK_FOR_INDEX_P
+#undef REGNO_OK_FOR_INDEX_P
+#define        REGNO_OK_FOR_INDEX_P(REGNO)     0
+#define        REGNO_OK_FOR_INDEX_P(REGNO)     0
Line 3884... Line 4142...
+ * value X into a register in class CLASS.  On many machines, the following
+ * value X into a register in class CLASS.  On many machines, the following
+ * definition is safe: PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
+ * definition is safe: PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
+ * Sometimes returning a more restrictive class makes better code.  For example,
+ * Sometimes returning a more restrictive class makes better code.  For example,
+ * on the 68k, when x is an integer constant that is in range for a moveq
+ * on the 68k, when x is an integer constant that is in range for a moveq
+ * instruction, the value of this macro is always DATA_REGS as long as CLASS
+ * instruction, the value of this macro is always DATA_REGS as long as CLASS
+ * includes the data registers.  Requiring a Ddata register guarantees that a
+ * includes the data registers.  Requiring a data register guarantees that a
+ * 'moveq' will be used.
+ * 'moveq' will be used.
+ *
+ *
+ * ZipCPU --- you can't load certain values into all members of ALL_REGS.  For
+ * ZipCPU --- you can't load certain values into all members of ALL_REGS.  For
+ * example, loading (sleep and !gie) into the CC register could halt the CPU.
+ * example, loading (sleep and !gie) into the CC register could halt the CPU.
+ * Hence, we only allow loads into the GENERAL_REG class.
+ * Hence, we only allow loads into the GENERAL_REG class.
Line 3938... Line 4196...
+/* TARRGET_LRA_P
+/* TARRGET_LRA_P
+ * Default looks good.
+ * Default looks good.
+ */
+ */
+
+
+/* TARGET_REGISTER_PRIORITY(INT) ... A target hook which returns the register
+/* TARGET_REGISTER_PRIORITY(INT) ... A target hook which returns the register
+ * priority number to which the register HARD_REGNO belongs to.  THe bigger the
+ * priority number to which the register HARD_REGNO belongs to.  The bigger the
+ * number
+ * number
+ *
+ *
+ * The default version of this target hook returns always zero---good enough for
+ * The default version of this target hook returns always zero---good enough for
+ * the ZipCPU.
+ * the ZipCPU.
+ */
+ */
Line 4904... Line 5162...
+ */
+ */
+
+
+
+
+/* 17.09.10 Caller-Saves Register Allocation */
+/* 17.09.10 Caller-Saves Register Allocation */
+/* 17.09.11 Function Entry and Exit */
+/* 17.09.11 Function Entry and Exit */
 
+// TARGET_ASM_FUNCTION_PROLOGUE
 
+// TARGET_ASM_FUNCTION_END_PROLOGUE
 
+// TARGET_ASM_FUNCCTION_BEGIN_EPILOGUE
 
+// TARGET_ASM_FUNCTION_EPILOGUE
 
+/* EXIT_IGNORE_STACK ... Define this macro as a C expression that is nonzero
 
+ * if the return instruction or the function epilogue ignores the value of the
 
+ * stack pointer; in other words, if it is safe to delete an instruction to
 
+ * adjust the stack pointer before a return from the function.
 
+ *
 
+ * The default is 0.
 
+ *
 
+ * Note that this macro's value is relevant only for functions for which frame
 
+ * pointers are maintained.  It is never safe to delete a final stack adjustment
 
+ * in a function that has no frame pointer, and the compiler knows this
 
+ * regardless of EXIT_IGNORE_STACK.
 
+ *
 
+ * ZipCPU -- Thanks to the example of the m68k, and a careful selection of what
 
+ * our options otherwise could have been, our epilogue code does not use the
 
+ * stack register at all, but rather starts by moving the frame register into
 
+ * the stack register.
 
+ */
 
+#define EXIT_IGNORE_STACK      1
 
+// EPILOGUE_USES(regno)
 
+// EH_USES(regno)
 
+// TARGET_ASM_OUTPUT_MI_THUNK
 
+// TARGET_ASM_CAN_OUTPUT_MI_THUNK
 
+
+/* 17.09.12 Generating code for profiling */
+/* 17.09.12 Generating code for profiling */
 
+// FUNCTION_PROFILER
 
+// PROFILE_HOOK
 
+// NO_PROFILE_COUNTERS
 
+// PROFILE_BEFORE_PROLOGUE
 
+// TARGET_KEEP_LEAF_WHEN_PROFILED
 
+
+/* 17.09.13 Permitting tail calls*/
+/* 17.09.13 Permitting tail calls*/
 
+
 
+/* TARGET_FUNCTION_OK_FOR_SIBCALL(DECL,EXP) ... True if it is OK to do sibling
 
+ * call optimizations for the specified call expression EXP.  DECL will be the
 
+ * called function, or NULL if this is an indirect call.
 
+ *
 
+ * It is not uncommon for limitations of calling conventions to prevent tail
 
+ * calls to functions outside the current unit of translation, or during PIC
 
+ * compilation.  The hook is used to enforce these restrictions, as the sibcall
 
+ * md pattern can not fail, or fall over to a 'normal' call.  The criteria for
 
+ * successful sibling call optimization may vary greatly between different
 
+ * architectures.
 
+ *
 
+ * ?? What's a sibling call?
 
+ */
 
+
 
+// TARGET_EXTRA_LIVE_ON_ENTRY
 
+// TARGET_SET_UP_BY_PROLOGUE
 
+// TARGET_WARN_FUNC_RETURN
 
+
+/* 17.09.14 Stack smashing protection */
+/* 17.09.14 Stack smashing protection */
 
+// TARGET_STACK_PROTECT_GUARD
 
+// TARGET_STACK_PROTECT_FAIL
 
+// TARGET_SUPPORTS_SPLIT_STACK
 
+
+/* 17.09.15 Miscellaneous register hooks */
+/* 17.09.15 Miscellaneous register hooks */
+
+
 
+// TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
 
+
+/* TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
+/* TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
+ * ZipCPU --- default is good enough for us.
+ * ZipCPU --- default is good enough for us.
+ */
+ */
+
+
+/* 17.10 Implementing VARARGS MACROS */
+/* 17.10 Implementing VARARGS MACROS */
Line 5001... Line 5317...
+ *
+ *
+ * ZipCPU --- Ouch!  We have no way to do this (yet)!
+ * ZipCPU --- Ouch!  We have no way to do this (yet)!
+ */
+ */
+
+
+/* TRANSFER_FROM_TRAMPOLINE ... Define this macro is trampolines need a special
+/* TRANSFER_FROM_TRAMPOLINE ... Define this macro is trampolines need a special
+ * subroutine to do their work.  THe macro should expand to a series of asm
+ * subroutine to do their work.  The macro should expand to a series of asm
+ * statements which will be compiled with GCC.  They go in a library function
+ * statements which will be compiled with GCC.  They go in a library function
+ * named __transfer_from_trampoline.
+ * named __transfer_from_trampoline.
+ *
+ *
+ * We may need to rethink trampolines on ZipCPU.
+ * We may need to rethink trampolines on ZipCPU.
+ */
+ */
Line 5124... Line 5440...
+ * they are also constant addresses.  Hence, we leave this at its default.
+ * they are also constant addresses.  Hence, we leave this at its default.
+ */
+ */
+// #undef      CONSTANT_ADDRESS_P
+// #undef      CONSTANT_ADDRESS_P
+// #define     CONSTANT_ADDRESS_P(X)   (0)
+// #define     CONSTANT_ADDRESS_P(X)   (0)
+
+
+/* CONSTANT_P(X) ... CONSTANT_P, which is defined by target-independent code, accepts integer values expressions whose values are not explicitly known, such as symbol_ref, label_ref, and high expressions and const arithmetic expressions, in addition to const_int and const_double expressions.
+/* CONSTANT_P(X) ... CONSTANT_P, which is defined by target-independent code,
 
+ * accepts integer values expressions whose values are not explicitly known,
 
+ * such as symbol_ref, label_ref, and high expressions and const arithmetic
 
+ * expressions, in addition to const_int and const_double expressions.
+ *
+ *
+ * Huh???
+ * Huh???
+ */
+ */
+// #define CONSTANT_P(X) ???
+// #define CONSTANT_P(X) ???
+
+
+/* A number, the maximum number of registers that can appear in a valid memory
+/* MAX_REGS_PER_ADDRESS ... A number, the maximum number of registers that can
+ * address.
+ * appear in a valid memory address.  Note that it is up to you to specify a
 
+ * value equal to the maximum number that TARGET_LEGITIMATE_ADDRESS_P would
 
+ * ever accept.
+ */
+ */
+#define        MAX_REGS_PER_ADDRESS    1
+#define        MAX_REGS_PER_ADDRESS    1
+
+
+/* TARGET_LEGITIMATE_ADDRESS_P(MODE,RTX,STRICT) ... A function that returns
+/* TARGET_LEGITIMATE_ADDRESS_P(MODE,RTX,STRICT) ... A function that returns
+ * whether RTX is a legitimate memory address on the target machine for a
+ * whether RTX is a legitimate memory address on the target machine for a
+ * memory operation of mode MODE.
+ * memory operation of mode MODE.
+ */
+ */
+#undef TARGET_LEGITIMATE_ADDRESS_P
+#undef TARGET_LEGITIMATE_ADDRESS_P
+#define TARGET_LEGITIMATE_ADDRESS_P    zip_legitimate_address_p
+#define TARGET_LEGITIMATE_ADDRESS_P    zip_legitimate_address_p
+
+
+/* ECO32 suggested we do something like ... */
 
+#ifdef IGNORE_THIS_FOR_NOW
 
+#define        TARGET_LEGITIMATE_ADDRESS_P(MODE,X,STRICT)                      \
 
+       do {                                                    \
 
+               if (GET_CODE(X) == PLUS) {                      \
 
+                       rtx     op1, op2;                       \
 
+                       op1 = XEXP(X, 0); op2 = XEXP(X, 1);     \
 
+                       if ((GET_CODE(op1) == REG)              \
 
+                               &&(CONSTANT_ADDRESS_P(op2))     \
 
+                               &&(REGNO_OK_FOR_BASE_P(REGNO(op1))))    \
 
+                               goto LABEL;                     \
 
+               } if ((REG_P(X))&&(REGNO_OK_FOR_BASE_P(REGNO(X)))) \
 
+                       goto LABEL;                             \
 
+               if ((GET_CODE(X) == SYMBOL_REF)                 \
 
+                       ||(GET_CODE(X) == LABEL_REF)            \
 
+                       ||(GET_CODE(X) == CONST))               \
 
+                       goto LABEL;                             \
 
+       } while(0)
 
+#endif
 
+
 
+
 
+/* TARGET_MEM_CONSTRAINT ... A single character to be used instead of the
+/* TARGET_MEM_CONSTRAINT ... A single character to be used instead of the
+ * default 'm' character for general memory addresses.  This defines the
+ * default 'm' character for general memory addresses.  This defines the
+ * constraint letter which matches the memory addresses accepted by
+ * constraint letter which matches the memory addresses accepted by
+ * TARGET_LEGITIMATE_ADDRESS_P.  Define this macro if you want to support new
+ * TARGET_LEGITIMATE_ADDRESS_P.  Define this macro if you want to support new
+ * address format in your back end without changing the semantics of the 'm'
+ * address format in your back end without changing the semantics of the 'm'
Line 5191... Line 5491...
+ * memory address RTX for an operand of mode MODE and should try to return a
+ * memory address RTX for an operand of mode MODE and should try to return a
+ * valid memory address.  RTX will always be the result of a call to
+ * valid memory address.  RTX will always be the result of a call to
+ * break_out_memory_refs, and OLD will be the operand that was given to that
+ * break_out_memory_refs, and OLD will be the operand that was given to that
+ * function to produce RTX.
+ * function to produce RTX.
+ *
+ *
+ * ZipCPU -- this may be worth coming back to.
+ * ZipCPU --
+ */
+ */
+// #undef      TARGET_LEGITIMIZE_ADDRESS
+#undef TARGET_LEGITIMIZE_ADDRESS
+// #define     TARGET_LEGITIMIZE_ADDRESS       zip_legitimize_address
+#define        TARGET_LEGITIMIZE_ADDRESS       zip_legitimize_address
+
+
+/* LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OP,TYPE,IND,WIN) ... A C compound statement
+/* LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OP,TYPE,IND,WIN) ... A C compound statement
+ * that attempts to replace X, which is an address that needs reloading, with
+ * that attempts to replace X, which is an address that needs reloading, with
+ * a valid memory address for an operand of mode MODE.  WIN will be a C
+ * a valid memory address for an operand of mode MODE.  WIN will be a C
+ * statement label elsewhere in the code.  It is not necessary to define this
+ * statement label elsewhere in the code.  It is not necessary to define this
Line 5217... Line 5517...
+ * the address is valid for some modes but not others.
+ * the address is valid for some modes but not others.
+ */
+ */
+#undef TARGET_MODE_DEPENDENT_ADDRESS_P
+#undef TARGET_MODE_DEPENDENT_ADDRESS_P
+#define        TARGET_MODE_DEPENDENT_ADDRESS_P         zip_mode_dependent_address_p
+#define        TARGET_MODE_DEPENDENT_ADDRESS_P         zip_mode_dependent_address_p
+
+
+/* TARGET_LEGITIMATE_CONSTANT_P
+/* TARGET_LEGITIMATE_CONSTANT_P(MODE,RTX) ... This hook returns true if x is a
 
+ * legitimate constant for a MODE-mode immediate operand on the target machine.
 
+ * You can assume the RTX satisfies CONSTANT_P, so you need not check this.
 
+ *
 
+ * The default definition returns true.
+ */
+ */
+
+
+/* TARGET_DELIGITIMIZE_ADDRESS(RTX)
+/* TARGET_DELIGITIMIZE_ADDRESS(RTX)
+ */
+ */
+
+
Line 5231... Line 5535...
+
+
+/* TARGET_CANNOT_FORCE_CONST_MEM(MODE,RTX) ... This hook should return true if
+/* TARGET_CANNOT_FORCE_CONST_MEM(MODE,RTX) ... This hook should return true if
+ * RTX is a form that cannot (or should not) be spilled to the constant pool.
+ * RTX is a form that cannot (or should not) be spilled to the constant pool.
+ * MODE is the mode of X.  The default version returns false.
+ * MODE is the mode of X.  The default version returns false.
+ */
+ */
 
+// #define     TARGET_CANNOT_FORCE_CONST_MEM   hook_bool_mode_rtx_false
+
+
+/* TARGET_USE_BLOCKS_FOR_CONSTANT_P(MODE,RTX) ... This hook should return true
+/* TARGET_USE_BLOCKS_FOR_CONSTANT_P(MODE,RTX) ... This hook should return true
+ * if pool entries for constant RTX can be placed in an object_block structure.
+ * if pool entries for constant RTX can be placed in an object_block structure.
+ * MODE is the mode of X.  The default version returns false for all constants.
+ * MODE is the mode of X.  The default version returns false for all constants.
+ *
+ *
Line 5415... Line 5720...
+ * moves, so let's make certain this is defined.
+ * moves, so let's make certain this is defined.
+ */
+ */
+#define        TARGET_MEMORY_MOVE_COST zip_memory_move_cost
+#define        TARGET_MEMORY_MOVE_COST zip_memory_move_cost
+
+
+// #warning "This needs to be double checked, and annotated"
+// #warning "This needs to be double checked, and annotated"
+#define        BRANCH_COST(SPEED,PREDICTABLE)          ((SPEED)?2:5)
+#define        BRANCH_COST(SPEED,PREDICTABLE)          ((PREDICTABLE)?2:5)
+
+
+/* Define this macro as a C expression which is nonzero if accessing less than
+/* Define this macro as a C expression which is nonzero if accessing less than
+ * a word of memory (i.e. a 'char' or a 'short') is no faster than accessing
+ * a word of memory (i.e. a 'char' or a 'short') is no faster than accessing
+ * a word of memory.
+ * a word of memory.
+ */
+ */
Line 5454... Line 5759...
+ * can be optimized into a single cycle delay.  Register jumps will always
+ * can be optimized into a single cycle delay.  Register jumps will always
+ * stall the whole (5-stage) pipeline.
+ * stall the whole (5-stage) pipeline.
+ */
+ */
+#define        NO_FUNCTION_CSE
+#define        NO_FUNCTION_CSE
+
+
+/* TARGET_ADDRESS_COST ... This hook computes the cost of an addressing mode
+/* TARGET_RTX_COSTS(X,CODE,OUTER,OPNO,TOTAL,SPD) ... This target hook describes
+ * that contains address.  If not defined, the cost is computed from the
+ * the relative costs of RTL expressions.
+ * address expression and the TARGET_RTX_COST hook.
+ *
 
+ * The cost may depend on the precise form of the expression, which is avaialble
 
+ * for examination in X, and the fact that X appears as operand OPNO of an
 
+ * expression with rtx code OUTER.  That is, the hook can assume that there is
 
+ * some RTX Y such that GET_CODE(Y)==OUTER and such that either (a) XEXP(Y,OPNO)
 
+ * == X or (b) XVEC(Y,OPNO) contains X.
 
+ *
 
+ * ...
 
+ * The hook returns true when all subexpressions of x have been processed and
 
+ * false when rtx_cost should recurse.
+ */
+ */
+// We should define this for ZIP ... we're just not there yet
+
+// int TARGET_ADDRESS_COST(rtx address, machine_mode mode, addr_space_t as, bool speed)
 
+/* TARGET_ADDRESS_COST(ADDR,MODE,AS, SPD) ... This hook computes the cost of an
+/* TARGET_ADDRESS_COST(ADDR,MODE,AS, SPD) ... This hook computes the cost of an
+ * addressing mode that contains ADDR.  If not defined, the cost is computed
+ * addressing mode that contains ADDR.  If not defined, the cost is computed
+ * from the ADDR expression and the TARGET_RTX_COST hook.  In cases where more
+ * from the ADDR expression and the TARGET_RTX_COST hook.  In cases where more
+ * than one form of an address is known, the form with the lowest cost will be
+ * than one form of an address is known, the form with the lowest cost will be
+ * used.  If multiple forms have the same, lowest, cost, the one that is the
+ * used.  If multiple forms have the same, lowest, cost, the one that is the
Line 5691... Line 6004...
+
+
+
+
+
+
+/* 17.21 Controlling Debugging Information Format */
+/* 17.21 Controlling Debugging Information Format */
+/* 17.22 Cross Compilation and Floating Point */
+/* 17.22 Cross Compilation and Floating Point */
 
+
 
+// REAL_VALUE_TYPE
 
+// REAL_VALUES_EQUAL
 
+// REAL_VALUES_LESS ... Tess whether x is less than y
 
+/* REAL_VALUE_FIX ... Truncates x to an unsigned integer, rouding toward zero.
 
+ * If x is negative, returns zero.
 
+ */
 
+// REAL_VALUE_ATOF
 
+// REAL_VALUE_NEGATIVE
 
+// REAL_VALUE_ISINF
 
+// REAL_VALUE_ISNAN
 
+/* REAL_ARITHMETIC(OUT,CODE,X,Y) ... (Macro) Calculates an arithmetic operation
 
+ * on two floating point values X and Y, storing the result in OUT (which must
 
+ * be a variable).
 
+ *
 
+ * The operation to be performed is specified by CODE.  Only the following
 
+ * codes are supported: PLUS_EXPR, MINUS_EXPR, MULT_EXPR, RDIV_EXPR, MAX_EXPR,
 
+ * MIN_EXPR.
 
+ *
 
+ * If REAL_ARITHMETIC is asked to evaluate division by zero and the target's
 
+ * floating point format cannot represent infinity, it will call abort().
 
+ * Callers shoudl check for this situation first, using MODE_HAS_INFINITIES.
 
+ */
 
+/* REAL_VALUE_NEGATE(X) ... [Macro] Returns the negative of the floating point
 
+ * value X.
 
+ */
 
+/* REAL_VALUE_ABS(X) ... [Macro] Returns the absolute value of X.
 
+ */
+/* 17.23 Mode switching instructions */
+/* 17.23 Mode switching instructions */
+/* 17.24 Defining target-specific uses of __attribute__ */
+/* 17.24 Defining target-specific uses of __attribute__ */
+#undef TARGET_OPTION_OVERRIDE
+#undef TARGET_OPTION_OVERRIDE
+#define        TARGET_OPTION_OVERRIDE  zip_override_options
+#define        TARGET_OPTION_OVERRIDE  zip_override_options
+
+
Line 6539... Line 6880...
+// extern bool zip_load_address_sto(rtx, rtx);
+// extern bool zip_load_address_sto(rtx, rtx);
+// extern void zip_print_operand(FILE *fp, rtx x, int code);
+// extern void zip_print_operand(FILE *fp, rtx x, int code);
+// extern void zip_print_operand_address(FILE *fp, rtx x);
+// extern void zip_print_operand_address(FILE *fp, rtx x);
+// extern bool zip_use_return_insn(void);
+// extern bool zip_use_return_insn(void);
+
+
 
+#define        UQQmode USQmode
 
+#define        UHQmode USQmode
 
+#define        UHAmode USAmode
 
+#define        QQmode  SQmode
 
+#define        HQmode  SQmode
+#define        QImode  SImode
+#define        QImode  SImode
+#define        HImode  SImode
+#define        HImode  SImode
 
+#define        QAmode  SAmode
 
+#define        HAmode  SAmode
+
+
+#include "insn-modes.h"
+#include "insn-modes.h"
+#include "zip-protos.h"
+#include "zip-protos.h"
+
+
+#endif /* GCC_ZIP_H */
+#endif /* GCC_ZIP_H */
+
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
--- gcc-5.3.0-original/gcc/config/zip/zip.md    1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip.md    1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-03-07 18:21:44.060561458 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-03-24 21:23:15.776993706 -0400
@@ -0,0 +1,1736 @@
@@ -0,0 +1,1963 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;;
+;; Filename:   zip.md
+;; Filename:   zip.md
+;;
+;;
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
Line 6592... Line 6940...
+;;     'M'     -2^12 ... 2^12-1, or -4096 ... 4095             (MOV offset)
+;;     'M'     -2^12 ... 2^12-1, or -4096 ... 4095             (MOV offset)
+;;     'N'     -2^14 ... 2^14-1, or -16384 ... 16383           (OpB offset)
+;;     'N'     -2^14 ... 2^14-1, or -16384 ... 16383           (OpB offset)
+;;     'O'     -2^17 ... 2^17-1, or -131072 ... 131071         (OpB Immediate)
+;;     'O'     -2^17 ... 2^17-1, or -131072 ... 131071         (OpB Immediate)
+;;     'R'     0...31                                          (Shift value)
+;;     'R'     0...31                                          (Shift value)
+;; - Memory constraints
+;; - Memory constraints
+;;     'Q'     Op-B capable references to memory
+;;     "Q"     Op-B capable references to memory
+;;     'S'     References to constant memory
+;;     "S"     References to constant memory
+;; - Address constraints
+;; - Address constraints
+;;     'P'     Op-B capable references to memory
+;;     "U"     Op-B capable address that references to memory
+;;     'T'     Constant memory addresses
+;;     "T"     Constant memory addresses
+(define_constraint "M"
+(define_constraint "M"
+  "An 13-bit signed immediate such as a MOV instruction can handle"
+  "An 13-bit signed immediate such as a MOV instruction can handle"
+  (and (match_code "const_int")
+  (and (match_code "const_int")
+       (match_test "(ival < 0x1000) && (ival >= -0x1000)")))
+       (match_test "(ival < 0x1000) && (ival >= -0x1000)")))
+(define_constraint "N"
+(define_constraint "N"
Line 6656... Line 7004...
+})
+})
+
+
+(define_predicate "zip_address_operand_p"
+(define_predicate "zip_address_operand_p"
+       (match_code "reg,plus")
+       (match_code "reg,plus")
+{
+{
+       return zip_pd_address_operand(op);
+       return zip_pd_opb_operand(op);
 
+})
 
+
 
+(define_predicate "zip_opb_operand_p"
 
+       (match_code "reg,plus,const_int")
 
+{
 
+       return zip_pd_opb_operand(op);
 
+})
 
+
 
+(define_predicate "zip_opb_single_operand_p"
 
+       (match_code "reg,const_int")
 
+{
 
+       return zip_pd_opb_operand(op);
+})
+})
+
+
+(define_predicate "zip_mov_operand_p"
+(define_predicate "zip_mov_operand_p"
+       (match_code "reg,plus")
+       (match_code "reg,plus")
+{
+{
Line 6668... Line 7028...
+})
+})
+
+
+(define_predicate "zip_memory_operand_p"
+(define_predicate "zip_memory_operand_p"
+       (match_code "mem")
+       (match_code "mem")
+{
+{
+       return zip_pd_address_operand(XEXP(op,0));
+       return zip_pd_opb_operand(XEXP(op,0));
 
+})
 
+
 
+(define_predicate "zip_imm_operand_p"
 
+       (match_code "const_int")
 
+{
 
+       return zip_pd_imm_operand(op);
 
+})
 
+
 
+(define_predicate "zip_mvimm_operand_p"
 
+       (match_code "const_int")
 
+{
 
+       return zip_pd_mvimm_operand(op);
 
+})
 
+
 
+(define_predicate "zip_movdst_operand_p"
 
+       (match_code "mem,reg,subreg")
 
+{
 
+       if (MEM_P(op)) // Check for valid store address
 
+               return zip_pd_opb_operand(XEXP(op,0));
 
+       return 1;
 
+})
 
+
 
+(define_predicate "zip_movsrc_operand_p"
 
+       (match_code "mem,reg,subreg,const_int,const,symbol_ref,label_ref,code_label")
 
+{
 
+       if (MEM_P(op))
 
+               return zip_pd_opb_operand(XEXP(op,0));
 
+       else if (GET_CODE(op)==PLUS)
 
+               return zip_pd_opb_operand(op);
 
+       return 1;
+})
+})
+
+
+;; Constraints
+;; Constraints
+;
+;
+(define_memory_constraint "S"
+(define_memory_constraint "S"
Line 6748... Line 7138...
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+;
+;
+;
+;
+;
+(define_expand "mov<mode>"
+(define_expand "mov<mode>"
+       [(set (match_operand:ZI 0 "nonimmediate_operand" "") ; =r,Q,r,r")
+       [(set (match_operand:ZI 0 "nonimmediate_operand" "")
+               (match_operand:ZI 1 "general_operand" ""))] ; r,r,Q,i"))]
+               (match_operand:ZI 1 "general_operand" ""))]
+       ""
+       ""
+       {/* Everything except mem=const or mem=mem can be done easily */
+       {//; Everything except mem=const or mem=mem can be done easily
+       if (zip_gen_move_rtl(operands[0], operands[1]))
+       //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
+               DONE;
+       //; fprintf(stderr, "ZIP-GEN-MOVE\n");
+       else internal_error("%s", "Zip/No usable movsi expansion\n");
+       //; zip_debug_rtx_pfx("FROM: ", operands[1]);
 
+       //; zip_debug_rtx_pfx("TO  : ", operands[0]);
 
+
 
+       //; Need to load into a register between memory slots
 
+       if ((MEM_P(operands[0]))&&(MEM_P(operands[1]))) {
 
+               //; fprintf(stderr, "GEN-MOVSI: MEM -> MEM\n");
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
 
+                       emit_insn(gen_movsi(tmp,operands[1]));
 
+                       operands[1] = tmp;
 
+               }
 
+       }
 
+
 
+       //; Op[0] has a bad address, need to legitimize it
 
+       if ((MEM_P(operands[0]))&&
 
+               ((zip_const_address_operand(XEXP(operands[0],0)))
 
+               ||(!zip_pd_opb_operand(XEXP(operands[0],0))))
 
+               )
 
+               {
 
+               //; fprintf(stderr, "GEN-MOVSI: Not to a MEM(REG)\n");
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(Pmode);
 
+                       //; Load the address into a register
 
+                       emit_insn(gen_movsi(tmp,XEXP(operands[0],0)));
 
+                       XEXP(operands[0],0) = tmp;
 
+                       mark_reg_pointer(tmp,1);
 
+               }
 
+       }
 
+       //; Op[1] is a constant.  Need to load into a register before we can
 
+       //; place it into memory.
 
+       if ((MEM_P(operands[0]))&&
 
+               ((CONSTANT_P(operands[1]))
 
+               ||(CONST_INT_P(operands[1])))) {
 
+               //; fprintf(stderr, "GEN-MOVSI: CONST -> MEM\n");
 
+               //; zip_debug_rtx_pfx("MEM  : ", operands[0]);
 
+               //; zip_debug_rtx_pfx("CONST: ", operands[1]);
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(GET_MODE(operands[0]));
 
+                       emit_insn(gen_movsi(tmp,operands[1]));
 
+                       operands[1] = tmp;
+       }
+       }
 
+       }
 
+       //; Op[1] has a bad address, need to legitimize it
 
+       if ((MEM_P(operands[1]))&&
 
+               //; (!REG_P(XEXP(operands[1],0)))
 
+               ((zip_const_address_operand(XEXP(operands[1],0)))
 
+               ||(!zip_pd_opb_operand(XEXP(operands[1],0))))
 
+               )
 
+               {
 
+               //; fprintf(stderr, "GEN-MOVSI: Not from a MEM(REG)\n");
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(Pmode);
 
+                       emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
 
+                       XEXP(operands[1],0) = tmp;
 
+               } else if (REG_P(operands[0])) { //; Can we steal Op[0]'s reg?
 
+                       rtx tmp = operands[0];
 
+                       emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
 
+                       XEXP(operands[1],0) = tmp;
 
+               }
 
+       }
 
+       }
 
+       [(set_attr "ccresult" "unchanged")])
 
+(define_insn "movsi_raw"
 
+       [(set (match_operand:SI 0 "zip_movdst_operand_p" "=r,Q,r,r")
 
+               (match_operand:SI 1 "zip_movsrc_operand_p" "r,r,Q,i"))]
 
+       "(REG_P(operands[0]))||(REG_P(operands[1]))"
 
+       "@
 
+       MOV\t%1,%0
 
+       STO\t%1,%0
 
+       LOD\t%1,%0
 
+       LDI\t%1,%0"
+       [(set_attr "ccresult" "unchanged")])
+       [(set_attr "ccresult" "unchanged")])
+(define_insn "mov<mode>_reg"   ; Register to register move
+(define_insn "mov<mode>_reg"   ; Register to register move
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (match_operand:ZI 1 "register_operand" "r"))]
+               (match_operand:ZI 1 "register_operand" "r"))]
+       ""
+       ""
+       "MOV    %1,%0"
+       "MOV    %1,%0"
+       [(set_attr "ccresult" "unchanged")])
+       [(set_attr "ccresult" "unchanged")])
+(define_insn "mov<mode>_reg_off"       ; Register to register move
+(define_insn "mov<mode>_reg_off"       ; Register to register move
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (plus:ZI (match_operand:ZI 1 "register_operand" "r")
+               (plus:ZI (match_operand:ZI 1 "register_operand" "r")
+                       (match_operand:ZI 2 "const_int_operand" "M")))]
+                       (match_operand:ZI 2 "zip_mvimm_operand_p" "M")))
 
+               ]
+       ""
+       ""
+       "MOV    %2(%1),%0"
+       "MOV    %2(%1),%0"
+       [(set_attr "ccresult" "unchanged")])
+       [(set_attr "ccresult" "unchanged")])
+;(define_insn "mov<mode>_lod"  ; Load from memory
+;(define_insn "mov<mode>_lod"  ; Load from memory
+;      [(set (match_operand:ZI 0 "register_operand" "=r")
+;      [(set (match_operand:ZI 0 "register_operand" "=r")
Line 6788... Line 7248...
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
+               (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
+       "")
+       "")
+(define_insn "*movsi_lod"
+(define_insn "*movsi_lod"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+               (mem:SI (match_operand:SI 1 "register_operand" "r")))]
+               (match_operand:SI 1 "zip_memory_operand_p" ""))]
+       ""
+       ""
+       "LOD\t%1,%0"
+       "LOD\t%1,%0"
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+(define_insn "*movsi_lod_off"
+;(define_insn "*movsi_lod_off"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       ;[(set (match_operand:SI 0 "register_operand" "=r")
+               (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
+               ;(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
+                       (match_operand:SI 2 "const_int_operand" "N"))))]
+                       ;(match_operand:SI 2 "const_int_operand" "N"))))]
+       ""
+       ;""
+       "LOD\t%2(%1),%0"
+       ;"LOD\t%2(%1),%0"
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+       ;[(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+(define_expand "mov<mode>_sto" ; Store into memory
+(define_expand "mov<mode>_sto" ; Store into memory
+       [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
+       [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
+               (match_operand:ZI 1 "register_operand" "r"))]
+               (match_operand:ZI 1 "register_operand" "r"))]
+       "")
+       "")
+(define_insn "*movsi_sto"
+(define_insn "*movsi_sto"
+       [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
+               (match_operand:SI 1 "register_operand" "r"))]
+               (match_operand:SI 1 "register_operand" "r"))]
+       ""
+       ""
+       "STO\t%1,(%0)"
+       "STO\t%1,%0"
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
 
+(define_insn "*movsi_sto_off"
 
+       [(set (mem:SI (plus:SI
 
+                       (match_operand:SI 0 "register_operand" "r")
 
+                       (match_operand:SI 1 "const_int_operand" "N")))
 
+               (match_operand:SI 2 "register_operand" "r"))]
 
+       ""
 
+       "STO\t%2,%1(%0)"
 
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
 
+;(define_insn "*movsi_sto_off"
 
+       ;[(set (mem:SI (plus:SI
 
+                       ;(match_operand:SI 0 "register_operand" "r")
 
+                       ;(match_operand:SI 1 "const_int_operand" "N")))
 
+               ;(match_operand:SI 2 "register_operand" "r"))]
 
+       ;""
 
+       ;"STO\t%2,%1(%0)"
 
+       ;[(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+(define_insn "mov<mode>_ldi"   ; Load immediate
+(define_insn "mov<mode>_ldi"   ; Load immediate
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (match_operand:ZI 1 "immediate_operand" "ipU"))]
+               (match_operand:ZI 1 "immediate_operand" "ipU"))]
+       ""
+       ""
+       "LDI    %1,%0"
+       "LDI    %1,%0"
Line 6855... Line 7315...
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+;
+;
+;
+;
+;
+;
+;
+(define_insn "add<mode>3" ; Fastest/best instruction always goes first
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
 
+(define_insn "*addsi3_reg" ; Fastest/best instruction always goes first
 
+       [(set (match_operand:ZI 0 "register_operand" "=r")
 
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
 
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
+       ]
+       ]
+       ""
+       ""
+       "ADD    %2,%0"
+       "ADD    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "add<mode>3_off" ; Fastest/best instruction always goes first
+(define_insn "add<mode>3_off" ; Fastest/best instruction always goes first
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                               (match_operand:ZI 3 "const_int_operand" "N"))))
+                               (match_operand:ZI 3 "const_int_operand" "N"))))]
+       ]
 
+       ""
+       ""
+       "ADD    %3+%2,%0"
+       "ADD    %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;
+;
+;
+;
+;
+;
+(define_expand "sub<mode>3"
+(define_expand "sub<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "nonmemory_operand" "")))
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
+       ])
+       ])
+(define_insn "*subsi3"
+(define_insn "sub<mode>3_reg"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
+       ]
+       ]
+       ""
+       ""
+       "SUB    %2,%0"
+       "SUB    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "sub<mode>3_off"
+(define_insn "sub<mode>3_off"
Line 6920... Line 7383...
+       ROL     16,%3
+       ROL     16,%3
+       AND     0x0ffff,%3
+       AND     0x0ffff,%3
+       ADD     %3,%0"
+       ADD     %3,%0"
+       [(set_attr "ccresult" "unknown")])
+       [(set_attr "ccresult" "unknown")])
+
+
+(define_insn "div<mode>3"
+(define_expand "div<mode>3"
 
+       [(set (match_operand:ZI 0 "register_operand" "=r")
 
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
 
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))]
 
+       "(ZIP_DIVIDE)")
 
+(define_insn "div<mode>3_reg"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))]
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))]
+       ""
+       "(ZIP_DIVIDE)"
+       "DIVS   %2,%0"
+       "DIVS   %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "div<mode>3_off"
+(define_insn "div<mode>3_off"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                               (match_operand:ZI 3 "const_int_operand" "N"))))]
+                               (match_operand:ZI 3 "const_int_operand" "N"))))]
+       ""
+       "(ZIP_DIVIDE)"
+       "DIVS   %3+%2,%0"
+       "DIVS   %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "udiv<mode>3"
+(define_expand "udiv<mode>3"
 
+       [(set (match_operand:ZI 0 "register_operand" "=r")
 
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
 
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))]
 
+       "(ZIP_DIVIDE)")
 
+(define_insn "udiv<mode>3_reg"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))]
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))]
+       ""
+       "(ZIP_DIVIDE)"
+       "DIVU   %2,%0"
+       "DIVU   %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "udiv<mode>3_off"
+(define_insn "udiv<mode>3_off"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                               (match_operand:ZI 3 "const_int_operand" "N"))))]
+                               (match_operand:ZI 3 "const_int_operand" "N"))))]
+       ""
+       "(ZIP_DIVIDE)"
+       "DIVU   %3+%2,%0"
+       "DIVU   %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;;
+;;
+;; modsi3
+;; modsi3
+;; umodsi3
+;; umodsi3
Line 6990... Line 7463...
+       ]
+       ]
+       ""
+       ""
+       "CMP    %0,%2
+       "CMP    %0,%2
+       MOV.LT  %2,%0"
+       MOV.LT  %2,%0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "and<mode>3"
+(define_expand "and<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+       ]
+(define_insn "and<mode>3_reg"
 
+       [(set (match_operand:ZI 0 "register_operand" "=r")
 
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
 
+                       (match_operand:ZI 2 "zip_opb_operand_p" "rO")))]
+       ""
+       ""
+       "AND    %2,%0"
+       "AND    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "and<mode>3_off"
+(define_insn "and<mode>3_off"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
Line 7007... Line 7483...
+                               (match_operand:ZI 3 "const_int_operand" "N"))))
+                               (match_operand:ZI 3 "const_int_operand" "N"))))
+       ]
+       ]
+       ""
+       ""
+       "AND    %3+%2,%0"
+       "AND    %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "ior<mode>3"
+(define_expand "ior<mode>3"
 
+       [(set (match_operand:ZI 0 "register_operand" "=r")
 
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
 
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
 
+(define_insn "ior<mode>3_reg"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))
+       ]
+       ]
+       ""
+       ""
Line 7024... Line 7504...
+                               (match_operand:ZI 3 "nonmemory_operand" "N"))))
+                               (match_operand:ZI 3 "nonmemory_operand" "N"))))
+       ]
+       ]
+       ""
+       ""
+       "OR     %3+%2,%0"
+       "OR     %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "xor<mode>3"
+(define_expand "xor<mode>3"
 
+       [(set (match_operand:ZI 0 "register_operand" "=r")
 
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
 
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
 
+(define_insn "xor<mode>3_reg"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))
+       ]
+       ]
+       ""
+       ""
Line 7076... Line 7560...
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rR")))]
+                       (match_operand:ZI 2 "nonmemory_operand" "rR")))]
+       ""
+       ""
+       "ASR    %2,%0"
+       "ASR    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
 
+(define_insn "ashl<mode>3"
 
+       [(set (match_operand:ZI 0 "register_operand" "=r")
 
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
 
+                       (match_operand:ZI 2 "nonmemory_operand" "rR")))]
 
+       ""
 
+       "ASR    %2,%0"
 
+       [(set_attr "ccresult" "set")])
+(define_insn "lshr<mode>3"
+(define_insn "lshr<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "register_operand" "rR")))]
+                       (match_operand:ZI 2 "register_operand" "rR")))]
+       ""
+       ""
Line 7137... Line 7628...
+;;
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+;
+;
+;
+;
+;
 
+(define_expand "movdi3"
 
+       [(set (match_operand:DI 0 "nonimmediate_operand" "")
 
+               (match_operand:DI 1 "general_operand" ""))])
 
+(define_insn "movdi_lod"
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "r")))]
 
+       ""
 
+       {
 
+               if (REG_P(operands[0]))
 
+                       return "LOD\t(%1),%H0\n\tLOD\t1(%1),%L0";
 
+               else if (GET_CODE(operands[0])==PLUS) {
 
+                       if ((REG_P(XEXP(operands[0],0)))
 
+                               &&(CONST_INT_P(XEXP(operands[0],1)))) {
 
+                               static  char    buf[64];
 
+                               sprintf(buf,
 
+                                       "LOD\t%ld(%%1),%%H0\n\tLOD\t%ld(%%1),%%L0",
 
+                                       INTVAL(XEXP(operands[0],1)),
 
+                                       INTVAL(XEXP(operands[0],1)+1));
 
+                               return buf;
 
+                       }
 
+               } else return "BREAK";
 
+       }
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
 
+(define_insn "movdi_sto"
 
+       [(set (mem:DI (match_operand:SI 0 "zip_opb_operand_p" ""))
 
+               (match_operand:DI 1 "register_operand" "r"))]
 
+       ""
 
+       {
 
+               if (REG_P(operands[0]))
 
+                       return "STO\t%H0,(%1)\n\tSTO\t%L0,1(%1)";
 
+               else if (GET_CODE(operands[0])==PLUS) {
 
+                       if ((REG_P(XEXP(operands[0],0)))
 
+                               &&(CONST_INT_P(XEXP(operands[0],1)))) {
 
+                               static  char    buf[64];
 
+                               sprintf(buf,
 
+                                       "STO\t%%H0,%ld(%%1)\n\tSTO\t%%L0,%ld(%%1)",
 
+                                       INTVAL(XEXP(operands[0],1)),
 
+                                       INTVAL(XEXP(operands[0],1)+1));
 
+                               return buf;
 
+                       }
 
+               } else return "BREAK";
 
+       }
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
 
+(define_insn "movdi_ldi"
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (match_operand:DI 1 "immediate_operand" "i"))]
 
+       ""
 
+       "LDI\t%H1,%H0\n\tLDI\t%L1,%L0"
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_insn "adddi3" ; Fastest/best instruction always goes first
+(define_insn "adddi3" ; Fastest/best instruction always goes first
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (plus:DI (match_operand:DI 1 "register_operand" "0")
+               (plus:DI (match_operand:DI 1 "register_operand" "0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
+       ]
+       ]
Line 7621... Line 8161...
+                               &&(INTVAL(operands[2])>(1<<17)-2)) {
+                               &&(INTVAL(operands[2])>(1<<17)-2)) {
+                       // fprintf(stderr, "CBRANCH:(LE,?,#,?)\n");
+                       // fprintf(stderr, "CBRANCH:(LE,?,#,?)\n");
+                       emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx,
+                       emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx,
+                               gen_rtx_COMPARE(VOIDmode, operands[1],
+                               gen_rtx_COMPARE(VOIDmode, operands[1],
+                                       GEN_INT(INTVAL(operands[2])+1))));
+                                       GEN_INT(INTVAL(operands[2])+1))));
+                       emit_insn(gen_cbranch_jmp_lt(operands[3]));
+                       emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
+                       DONE;
+                       DONE;
+               } else if ((GET_CODE(operands[0])==LEU)
+               } else if ((GET_CODE(operands[0])==LEU)
+                               &&(CONST_INT_P(operands[2]))
+                               &&(CONST_INT_P(operands[2]))
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
+                       // fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n");
+                       // fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n");
+                       emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx,
+                       emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx,
+                               gen_rtx_COMPARE(VOIDmode, operands[1],
+                               gen_rtx_COMPARE(VOIDmode, operands[1],
+                                       GEN_INT(INTVAL(operands[2])+1))));
+                                       GEN_INT(INTVAL(operands[2])+1))));
+                       emit_insn(gen_cbranch_jmp_ltu(operands[3]));
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+                       DONE;
+                       DONE;
+               }
+               }
+       })
+       })
+(define_insn "cbranch_jmp_eq"
+(define_insn "cbranch_jmp_eq"
+       [(set (pc) (if_then_else (eq (cc0) (const_int 0))
+       [(set (pc) (if_then_else (eq (cc0) (const_int 0))
Line 7840... Line 8380...
+; I'll probably bastardize a means of getting a new codelabel that GCC doesn't
+; I'll probably bastardize a means of getting a new codelabel that GCC doesn't
+; recognize as such, but for now we'll use .Lcall# as our label.
+; recognize as such, but for now we'll use .Lcall# as our label.
+;
+;
+(define_insn "void_call_const"
+(define_insn "void_call_const"
+       [(parallel [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
+       [(parallel [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
+                       (match_operand 1 "" ""))
+                       (match_operand 1 "const_int_operand" "n"))
+               (clobber (reg:SI RTN_REG))])]
+               (clobber (reg:SI RTN_REG))])]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;(define_insn "void_call_label"
 
+;      [(parallel [(call (mem:SI (label_ref (match_operand 0 "" "")))
 
+;                      (match_operand 1 "" ""))
 
+;              (clobber (reg:SI RTN_REG))])]
 
+;      ""
 
+;      "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
 
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+(define_insn "void_call_mem"
+(define_insn "void_call_mem"
+       [(parallel [(call (mem:SI (mem:SI (match_operand:SI 0 "zip_address_operand_p" "")))
+       [(parallel [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
+                       (match_operand 1 "" ""))
+                       (match_operand 1 "const_int_operand" "n"))
+               (clobber (reg:SI RTN_REG))])]
+               (clobber (reg:SI RTN_REG))])]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:"
+       "MOV    .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
+(define_insn "void_call_var"
+(define_insn "void_call_var"
+       [(parallel [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
+       [(parallel [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
+                       (match_operand 1 "" ""))
+                       (match_operand 1 "const_int_operand" "n"))
+               (clobber (reg:SI RTN_REG))])]
+               (clobber (reg:SI RTN_REG))])]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:"
+       "MOV    .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:"
+       ; emit_move_insn(??)
 
+       ;       emit_jump(where);
 
+       ;       emit_label(return_address);
 
+       ;
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_expand "call_value"
+(define_expand "call_value"
+       [(set (reg:SI RTNV_REG)
+       [(set (reg:SI RTNV_REG)
+               (call (match_operand:SI 1 "" "")
+               (call (match_operand:SI 1 "" "")
+                       (match_operand 2 "" "")))
+                       (match_operand 2 "const_int_operand" "n")))
+       (set (match_operand:SI 0 "register_operand" "=r") (reg:SI RTNV_REG))]
+       (set (match_operand:SI 0 "register_operand" "=r") (reg:SI RTNV_REG))]
+       ""
+       ""
+       {
+       {
+               // extern void zip_debug_rtx(const_rtx);
+               // extern void zip_debug_rtx(const_rtx);
+               // fprintf(stderr, "ZIP.MD::CALL-VALUE()\n");
+               // fprintf(stderr, "ZIP.MD::CALL-VALUE()\n");
Line 7903... Line 8432...
+               }
+               }
+       })
+       })
+(define_insn "reg_call_const"
+(define_insn "reg_call_const"
+       [(parallel [(set (reg:SI RTNV_REG)
+       [(parallel [(set (reg:SI RTNV_REG)
+               (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
+               (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
+                       (match_operand 1 "" "")))
+                       (match_operand 1 "const_int_operand" "n")))
+               (clobber (reg:SI RTN_REG))])]
+               (clobber (reg:SI RTN_REG))])]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;(define_insn "reg_call_label"
 
+;      [(parallel [(set (reg:SI RTNV_REG)
 
+;              (call (mem:SI (match_operand 0 "" ""))
 
+;                      (match_operand 1 "" "")))
 
+;              (clobber (reg:SI RTN_REG))])]
 
+;      ""
 
+;      "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
 
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+(define_insn "reg_call_mem"
+(define_insn "reg_call_mem"
+       [(set (reg:SI RTNV_REG)
+       [(set (reg:SI RTNV_REG)
+               (call (mem:SI (mem:SI (match_operand:SI 0 "zip_address_operand_p" "")))
+               (call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
+                       (match_operand 1 "" "")))
+                       (match_operand 1 "const_int_operand" "n")))
+               (clobber (reg:SI RTN_REG))]
+               (clobber (reg:SI RTN_REG))]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:" ; emit_label(return_lbl);
+       "MOV    .Lcall%=(PC),R0\n\tLOD\t%0,PC\n.Lcall%=:"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
+(define_insn "reg_call_var"
+(define_insn "reg_call_var"
+       [(parallel [(set (reg:SI RTNV_REG)
+       [(parallel [(set (reg:SI RTNV_REG)
+               (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
+               (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
+                       (match_operand 1 "" "")))
+                       (match_operand 1 "const_int_operand" "n")))
+               (clobber (reg:SI RTN_REG))])]
+               (clobber (reg:SI RTN_REG))])]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:"
+       "MOV    .Lcall%=(PC),R0\n\tJMP\t%0\n.Lcall%=:"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+;
+;
+;
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Line 8110... Line 8632...
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+               (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
+               (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
+       ""
+       ""
+       "MOV\tCC,%0"
+       "MOV\tCC,%0"
+       [(set_attr "ccresult" "unchanged")])
+       [(set_attr "ccresult" "unchanged")])
 
+(define_insn "zip_cc_sto"
 
+       [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
 
+               (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
 
+       ""
 
+       "STO\tCC,(%0)"
 
+       [(set_attr "ccresult" "unchanged")])
 
+(define_insn "zip_cc_sto_off"
 
+       [(set (mem:SI (plus:SI
 
+                       (match_operand:SI 0 "register_operand" "r")
 
+                       (match_operand:SI 1 "const_int_operand" "N")))
 
+               (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
 
+       ""
 
+       "STO\tCC,%1(%0)"
 
+       [(set_attr "ccresult" "unchanged")])
+(define_insn "ldilo"
+(define_insn "ldilo"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+               (unspec:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_LDILO))]
+               (unspec:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_LDILO))]
+       ""
+       ""
+       "LDILO  %1,%0"
+       "LDILO  %1,%0"
Line 8156... Line 8692...
+               (div:SF (match_operand:SF 1 "register_operand" "0")
+               (div:SF (match_operand:SF 1 "register_operand" "0")
+                       (match_operand:SF 2 "register_operand" "r")))]
+                       (match_operand:SF 2 "register_operand" "r")))]
+       "(ZIP_FPU)"
+       "(ZIP_FPU)"
+       "FPDIV  %2,%0"
+       "FPDIV  %2,%0"
+       [(set_attr "ccresult" "unknown")])
+       [(set_attr "ccresult" "unknown")])
+
+(define_expand "negsf2"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (neg:SF (match_operand:SF 1 "register_operand" "0")))
 
+       ]
 
+       ""
 
+       {
 
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(SImode);
 
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
 
+                       emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_XOR(SImode, operands[0], tmp)));
 
+                       DONE;
 
+               } else {
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_IOR(SImode, operands[0],gen_int_mode(1,SImode))));
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       DONE;
 
+               }
 
+       })
 
+(define_expand "abssf2"
 
+       [(set (match_operand:ZI 0 "register_operand" "=r")
 
+               (abs:ZI (match_operand:ZI 1 "register_operand" "0")))
 
+       ]
 
+       ""
 
+       {
 
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(SImode);
 
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
 
+                       emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_AND(SImode, operands[0], tmp)));
 
+                       DONE;
 
+               } else {
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       emit_insn(gen_rtx_SET(SImode, operands[0],
 
+                               gen_rtx_AND(SImode, operands[0],
 
+                               gen_int_mode(-2,SImode))));
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       DONE;
 
+               }
 
+       })
+;
+;
+;
+;
+;
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;;
Line 8289... Line 8864...
+;      cmove   ... the conditional move, created from a
+;      cmove   ... the conditional move, created from a
+;      (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))
+;      (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))
+;      pattern
+;      pattern
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-modes.def gcc-5.3.0-zip/gcc/config/zip/zip-modes.def
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-modes.def gcc-5.3.0-zip/gcc/config/zip/zip-modes.def
--- gcc-5.3.0-original/gcc/config/zip/zip-modes.def     1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip-modes.def     1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip-modes.def  2016-03-04 17:13:26.438204784 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip-modes.def  2016-03-08 12:10:21.982586940 -0500
@@ -0,0 +1,21 @@
@@ -0,0 +1,23 @@
+/*
+/*
+ * Commends in C-long comment form
+ * Commends in C-long comment form
+ * class
+ * class
+ *     Mode = "SI"
+ *     Mode = "SI"
+ *     PRECISION, BYTESIZE, COUNT ??
+ *     PRECISION, BYTESIZE, COUNT ??
+ *     FORMAT
+ *     FORMAT
+ *     EXPR
+ *     EXPR
 
+ *
 
+ * The manual says I need to define BITS_PER_UNIT here.
+ */
+ */
+// INT_MODE(QI, 1);
+// INT_MODE(QI, 1);
+// INT_MODE(HI, 1);
+// INT_MODE(HI, 1);
+// INT_MODE(SI, 1);
+// INT_MODE(SI, 1);
+// INT_MODE(DI, 2);
+// INT_MODE(DI, 2);
Line 8314... Line 8891...
+// change needed to be made in machmodes.def.  Hence, here is a target
+// change needed to be made in machmodes.def.  Hence, here is a target
+// configuration change--in machmodes.def--that properly belonged in the
+// configuration change--in machmodes.def--that properly belonged in the
+// config directory.
+// config directory.
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h      1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h      1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h   2016-03-02 10:35:53.661426308 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h   2016-03-12 17:39:02.331344108 -0500
@@ -0,0 +1,69 @@
@@ -0,0 +1,70 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   zip-protos.h
+// Filename:   zip-protos.h
+//
+//
+// Project:    Zip CPU backend for the GNU Compiler Collection
+// Project:    Zip CPU backend for the GNU Compiler Collection
Line 8375... Line 8952...
+extern bool    zip_use_return_insn(void);
+extern bool    zip_use_return_insn(void);
+extern const char *zip_set_zero_or_one(rtx, rtx);
+extern const char *zip_set_zero_or_one(rtx, rtx);
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+
+
+extern int     zip_ct_address_operand(rtx op);
+extern int     zip_ct_address_operand(rtx op);
+extern int     zip_pd_address_operand(rtx op);
+extern int     zip_pd_opb_operand(rtx op);
+extern int     zip_pd_mov_operand(rtx op);
+extern int     zip_pd_mov_operand(rtx op);
 
+extern int     zip_pd_imm_operand(rtx op);
 
+extern int     zip_pd_mvimm_operand(rtx op);
+extern int     zip_ct_const_address_operand(rtx op);
+extern int     zip_ct_const_address_operand(rtx op);
+extern int     zip_pd_const_address_operand(rtx op);
+extern int     zip_pd_const_address_operand(rtx op);
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+extern const char *zip_addsicc(rtx, rtx, rtx, rtx);
+extern const char *zip_addsicc(rtx, rtx, rtx, rtx);
+// extern      void    zip_canonicalize_comparison(int *, rtx *, rtx *, bool);
 
+
+
+#endif
+#endif
+
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config.gcc gcc-5.3.0-zip/gcc/config.gcc
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config.gcc gcc-5.3.0-zip/gcc/config.gcc
--- gcc-5.3.0-original/gcc/config.gcc   2015-09-10 10:17:53.000000000 -0400
--- gcc-5.3.0-original/gcc/config.gcc   2015-09-10 10:17:53.000000000 -0400
Line 8417... Line 8995...
 *)
 *)
        echo "*** Configuration ${target} not supported" 1>&2
        echo "*** Configuration ${target} not supported" 1>&2
        exit 1
        exit 1
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cse.c gcc-5.3.0-zip/gcc/cse.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cse.c gcc-5.3.0-zip/gcc/cse.c
--- gcc-5.3.0-original/gcc/cse.c        2015-02-03 15:41:38.000000000 -0500
--- gcc-5.3.0-original/gcc/cse.c        2015-02-03 15:41:38.000000000 -0500
+++ gcc-5.3.0-zip/gcc/cse.c     2016-03-05 20:34:50.226907590 -0500
+++ gcc-5.3.0-zip/gcc/cse.c     2016-03-19 12:28:45.584701098 -0400
@@ -634,6 +634,14 @@
@@ -634,6 +634,15 @@
 
 
 /* Nonzero if X has the form (PLUS frame-pointer integer).  */
 /* Nonzero if X has the form (PLUS frame-pointer integer).  */
 
 
 
+// #define     DO_ZIP_DEBUGS
+#ifdef DO_ZIP_DEBUGS
+#ifdef DO_ZIP_DEBUGS
+#include <stdio.h>
+#include <stdio.h>
+extern void zip_debug_rtx(const_rtx);
+extern void zip_debug_rtx(const_rtx);
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s\n", STR); zip_debug_rtx(RTX); } while(0)
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s\n", STR); zip_debug_rtx(RTX); } while(0)
+#else
+#else
Line 8433... Line 9012...
+#endif
+#endif
+
+
 static bool
 static bool
 fixed_base_plus_p (rtx x)
 fixed_base_plus_p (rtx x)
 {
 {
@@ -2843,6 +2851,7 @@
 
   enum rtx_code code;
 
   const char *fmt;
 
 
 
+       ZIP_DEBUG_LINE("CANON-REG", insn);
 
   if (x == 0)
 
     return x;
 
 
 
@@ -2898,6 +2907,7 @@
@@ -2898,6 +2907,7 @@
          validate_canon_reg (&XVECEXP (x, i, j), insn);
          validate_canon_reg (&XVECEXP (x, i, j), insn);
     }
     }
 
 
+       ZIP_DEBUG_LINE("CANON-REG-RTN", x);
+       ZIP_DEBUG_LINE("CANON-REG-RTN", x);
Line 8775... Line 9346...
+#include "print-tree.h"
+#include "print-tree.h"
+
+
 rtx
 rtx
 expand_expr_real (tree exp, rtx target, machine_mode tmode,
 expand_expr_real (tree exp, rtx target, machine_mode tmode,
                  enum expand_modifier modifier, rtx *alt_rtl,
                  enum expand_modifier modifier, rtx *alt_rtl,
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c
 
--- gcc-5.3.0-original/gcc/final.c      2015-01-15 08:28:42.000000000 -0500
 
+++ gcc-5.3.0-zip/gcc/final.c   2016-03-24 22:12:00.263845620 -0400
 
@@ -109,6 +109,14 @@
 
 #include "wide-int-print.h"
 
 #include "rtl-iter.h"
 
 
 
+
 
+#ifdef DO_ZIP_DEBUGS
 
+extern void zip_debug_rtx(const_rtx);
 
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
 
+#else
 
+#define        ZIP_DEBUG_LINE(STR,RTX)
 
+#endif
 
+
 
 #ifdef XCOFF_DEBUGGING_INFO
 
 #include "xcoffout.h"          /* Needed for external data
 
                                   declarations for e.g. AIX 4.x.  */
 
@@ -2071,6 +2079,8 @@
 
   /* Output the insns.  */
 
   for (insn = first; insn;)
 
     {
 
+       ZIP_DEBUG_LINE("final()\n", insn);
 
+
 
       if (HAVE_ATTR_length)
 
        {
 
          if ((unsigned) INSN_UID (insn) >= INSN_ADDRESSES_SIZE ())
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/genmodes.c gcc-5.3.0-zip/gcc/genmodes.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/genmodes.c gcc-5.3.0-zip/gcc/genmodes.c
--- gcc-5.3.0-original/gcc/genmodes.c   2015-01-05 07:33:28.000000000 -0500
--- gcc-5.3.0-original/gcc/genmodes.c   2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/genmodes.c        2016-03-04 21:27:49.669147699 -0500
+++ gcc-5.3.0-zip/gcc/genmodes.c        2016-03-04 21:27:49.669147699 -0500
@@ -330,7 +330,8 @@
@@ -330,7 +330,8 @@
         the size of a CC mode is four units.  */
         the size of a CC mode is four units.  */
Line 8859... Line 9457...
 
 
   print_closer ();
   print_closer ();
 }
 }
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/machmode.def gcc-5.3.0-zip/gcc/machmode.def
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/machmode.def gcc-5.3.0-zip/gcc/machmode.def
--- gcc-5.3.0-original/gcc/machmode.def 2015-01-05 07:33:28.000000000 -0500
--- gcc-5.3.0-original/gcc/machmode.def 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/machmode.def      2016-03-04 22:47:59.406632941 -0500
+++ gcc-5.3.0-zip/gcc/machmode.def      2016-03-08 11:56:45.375491523 -0500
@@ -184,11 +184,11 @@
@@ -184,11 +184,11 @@
    larger types, then corresponding modes must be added here.  The
    larger types, then corresponding modes must be added here.  The
    name OI is reserved for a 256-bit type (needed by some back ends).
    name OI is reserved for a 256-bit type (needed by some back ends).
     */
     */
-INT_MODE (QI, 1);
-INT_MODE (QI, 1);
Line 8877... Line 9475...
+INT_MODE (DI, 2);
+INT_MODE (DI, 2);
+INT_MODE (TI, 4);
+INT_MODE (TI, 4);
 
 
 /* No partial integer modes are defined by default.  */
 /* No partial integer modes are defined by default.  */
 
 
@@ -206,8 +206,8 @@
@@ -206,35 +206,35 @@
    These are the IEEE mappings.  They can be overridden with
    These are the IEEE mappings.  They can be overridden with
    RESET_FLOAT_FORMAT or at runtime (in TARGET_OPTION_OVERRIDE).  */
    RESET_FLOAT_FORMAT or at runtime (in TARGET_OPTION_OVERRIDE).  */
 
 
-FLOAT_MODE (SF, 4, ieee_single_format);
-FLOAT_MODE (SF, 4, ieee_single_format);
-FLOAT_MODE (DF, 8, ieee_double_format);
-FLOAT_MODE (DF, 8, ieee_double_format);
+FLOAT_MODE (SF, 1, ieee_single_format);
+FLOAT_MODE (SF, 1, ieee_single_format);
+FLOAT_MODE (DF, 2, ieee_double_format);
+FLOAT_MODE (DF, 2, ieee_double_format);
 
 
 /* Basic CC modes.
 /* Basic CC modes.
    FIXME define this only for targets that need it.  */
    FIXME define this only for targets that need it.  */
@@ -215,16 +215,16 @@
 CC_MODE (CC);
 
 
 /* Fixed-point modes.  */
 /* Fixed-point modes.  */
 FRACT_MODE (QQ, 1, 7); /* s.7 */
-FRACT_MODE (QQ, 1, 7); /* s.7 */
-FRACT_MODE (HQ, 2, 15); /* s.15 */
-FRACT_MODE (HQ, 2, 15); /* s.15 */
-FRACT_MODE (SQ, 4, 31); /* s.31 */
-FRACT_MODE (SQ, 4, 31); /* s.31 */
-FRACT_MODE (DQ, 8, 63); /* s.63 */
-FRACT_MODE (DQ, 8, 63); /* s.63 */
-FRACT_MODE (TQ, 16, 127); /* s.127 */
-FRACT_MODE (TQ, 16, 127); /* s.127 */
+FRACT_MODE (HQ, 1, 15); /* s.15 */
-
+FRACT_MODE (SQ, 1, 31); /* s.31 */
-UFRACT_MODE (UQQ, 1, 8); /* .8 */
+FRACT_MODE (DQ, 2, 63); /* s.63 */
 
+FRACT_MODE (TQ, 4, 127); /* s.127 */
 
 
 
 UFRACT_MODE (UQQ, 1, 8); /* .8 */
 
-UFRACT_MODE (UHQ, 2, 16); /* .16 */
-UFRACT_MODE (UHQ, 2, 16); /* .16 */
-UFRACT_MODE (USQ, 4, 32); /* .32 */
-UFRACT_MODE (USQ, 4, 32); /* .32 */
-UFRACT_MODE (UDQ, 8, 64); /* .64 */
-UFRACT_MODE (UDQ, 8, 64); /* .64 */
-UFRACT_MODE (UTQ, 16, 128); /* .128 */
-UFRACT_MODE (UTQ, 16, 128); /* .128 */
+UFRACT_MODE (UHQ, 1, 16); /* .16 */
-
 
-ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
 
-ACCUM_MODE (SA, 4, 16, 15); /* s16.15 */
 
-ACCUM_MODE (DA, 8, 32, 31); /* s32.31 */
 
-ACCUM_MODE (TA, 16, 64, 63); /* s64.63 */
 
-
 
-UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
 
-UACCUM_MODE (USA, 4, 16, 16); /* 16.16 */
 
-UACCUM_MODE (UDA, 8, 32, 32); /* 32.32 */
 
-UACCUM_MODE (UTA, 16, 64, 64); /* 64.64 */
 
+/* FRACT_MODE (QQ, 1, 7); /* s.7 */
 
+/* FRACT_MODE (HQ, 1, 15); /* s.15 */
 
+FRACT_MODE (SQ, 1, 31); /* s.31 */
 
+FRACT_MODE (DQ, 2, 63); /* s.63 */
 
+FRACT_MODE (TQ, 4, 127); /* s.127 */
 
+
 
+/* UFRACT_MODE (UQQ, 1, 8); /* .8 */
 
+/* UFRACT_MODE (UHQ, 1, 16); /* .16 */
+UFRACT_MODE (USQ, 1, 32); /* .32 */
+UFRACT_MODE (USQ, 1, 32); /* .32 */
+UFRACT_MODE (UDQ, 2, 64); /* .64 */
+UFRACT_MODE (UDQ, 2, 64); /* .64 */
+UFRACT_MODE (UTQ, 4, 128); /* .128 */
+UFRACT_MODE (UTQ, 4, 128); /* .128 */
 
+
 
+/* ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
 
+ACCUM_MODE (SA, 1, 16, 15); /* s16.15 */
 
+ACCUM_MODE (DA, 2, 32, 31); /* s32.31 */
 
+ACCUM_MODE (TA, 4, 64, 63); /* s64.63 */
 
+
 
+/* UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
 
+UACCUM_MODE (USA, 1, 16, 16); /* 16.16 */
 
+UACCUM_MODE (UDA, 2, 32, 32); /* 32.32 */
 
+UACCUM_MODE (UTA, 4, 64, 64); /* 64.64 */
 
 
 ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
 /* Allow the target to specify additional modes of various kinds.  */
 ACCUM_MODE (SA, 4, 16, 15); /* s16.15 */
 #if HAVE_EXTRA_MODES
@@ -246,9 +246,9 @@
@@ -246,9 +246,9 @@
 COMPLEX_MODES (FLOAT);
 COMPLEX_MODES (FLOAT);
 
 
 /* Decimal floating point modes.  */
 /* Decimal floating point modes.  */
-DECIMAL_FLOAT_MODE (SD, 4, decimal_single_format);
-DECIMAL_FLOAT_MODE (SD, 4, decimal_single_format);
Line 8978... Line 9599...
            case SImode:
            case SImode:
              {
              {
                if (type == long_integer_type_node)
                if (type == long_integer_type_node)
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/postreload.c gcc-5.3.0-zip/gcc/postreload.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/postreload.c gcc-5.3.0-zip/gcc/postreload.c
--- gcc-5.3.0-original/gcc/postreload.c 2015-07-17 09:50:38.000000000 -0400
--- gcc-5.3.0-original/gcc/postreload.c 2015-07-17 09:50:38.000000000 -0400
+++ gcc-5.3.0-zip/gcc/postreload.c      2016-03-07 18:24:22.263499116 -0500
+++ gcc-5.3.0-zip/gcc/postreload.c      2016-03-24 21:30:23.402590035 -0400
@@ -71,6 +71,13 @@
@@ -71,6 +71,14 @@
 #include "df.h"
 #include "df.h"
 #include "dbgcnt.h"
 #include "dbgcnt.h"
 
 
 
+// #define     DO_ZIP_DEBUGS
+#ifdef DO_ZIP_DEBUGS
+#ifdef DO_ZIP_DEBUGS
+extern void zip_debug_rtx(const_rtx);
+extern void zip_debug_rtx(const_rtx);
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
+#else
+#else
+#define        ZIP_DEBUG_LINE(STR,RTX)
+#define        ZIP_DEBUG_LINE(STR,RTX)
+#endif
+#endif
+
+
 static int reload_cse_noop_set_p (rtx);
 static int reload_cse_noop_set_p (rtx);
 static bool reload_cse_simplify (rtx_insn *, rtx);
 static bool reload_cse_simplify (rtx_insn *, rtx);
 static void reload_cse_regs_1 (void);
 static void reload_cse_regs_1 (void);
@@ -120,6 +127,8 @@
@@ -120,6 +128,8 @@
   basic_block insn_bb = BLOCK_FOR_INSN (insn);
   basic_block insn_bb = BLOCK_FOR_INSN (insn);
   unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
   unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
 
 
+       ZIP_DEBUG_LINE("RELOAD-CSE-SIMPLIFY:",insn);
+       ZIP_DEBUG_LINE("RELOAD-CSE-SIMPLIFY:",insn);
+
+
   if (GET_CODE (body) == SET)
   if (GET_CODE (body) == SET)
     {
     {
       int count = 0;
       int count = 0;
@@ -147,6 +156,7 @@
@@ -147,6 +157,7 @@
        apply_change_group ();
        apply_change_group ();
       else
       else
        reload_cse_simplify_operands (insn, testreg);
        reload_cse_simplify_operands (insn, testreg);
+       ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
+       ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
     }
     }
   else if (GET_CODE (body) == PARALLEL)
   else if (GET_CODE (body) == PARALLEL)
     {
     {
@@ -205,6 +215,7 @@
@@ -205,6 +216,7 @@
        apply_change_group ();
        apply_change_group ();
       else
       else
        reload_cse_simplify_operands (insn, testreg);
        reload_cse_simplify_operands (insn, testreg);
+       ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
+       ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
     }
     }
 
 
 done:
 done:
@@ -246,6 +257,7 @@
@@ -246,6 +258,7 @@
          cfg_changed |= reload_cse_simplify (insn, testreg);
          cfg_changed |= reload_cse_simplify (insn, testreg);
 
 
        cselib_process_insn (insn);
        cselib_process_insn (insn);
+       ZIP_DEBUG_LINE("End-CSE-REGS-1:",insn);
+       ZIP_DEBUG_LINE("End-CSE-REGS-1:",insn);
       }
       }
 
 
   /* Clean up.  */
   /* Clean up.  */
@@ -276,6 +288,8 @@
@@ -276,6 +289,8 @@
 #endif
 #endif
   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
 
 
+
+
+       ZIP_DEBUG_LINE("RELOAD:Attempting to simplify set",set);
+       ZIP_DEBUG_LINE("RELOAD:Attempting to simplify set",set);
   dreg = true_regnum (SET_DEST (set));
   dreg = true_regnum (SET_DEST (set));
   if (dreg < 0)
   if (dreg < 0)
     return 0;
     return 0;
@@ -427,6 +441,7 @@
@@ -427,6 +442,7 @@
   /* Array of alternatives, sorted in order of decreasing desirability.  */
   /* Array of alternatives, sorted in order of decreasing desirability.  */
   int *alternative_order;
   int *alternative_order;
 
 
+       ZIP_DEBUG_LINE("Simplify-Operands", insn);
+       ZIP_DEBUG_LINE("Simplify-Operands", insn);
   extract_constrain_insn (insn);
   extract_constrain_insn (insn);
 
 
   if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
   if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
@@ -519,6 +534,7 @@
@@ -519,6 +535,7 @@
          SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
          SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
     }
     }
 
 
+       ZIP_DEBUG_LINE("Simplify-Operands - A", insn);
+       ZIP_DEBUG_LINE("Simplify-Operands - A", insn);
   alternative_mask preferred = get_preferred_alternatives (insn);
   alternative_mask preferred = get_preferred_alternatives (insn);
   for (i = 0; i < recog_data.n_operands; i++)
   for (i = 0; i < recog_data.n_operands; i++)
     {
     {
@@ -617,6 +633,7 @@
@@ -617,6 +634,7 @@
            }
            }
        }
        }
     }
     }
+       ZIP_DEBUG_LINE("Simplify-Operands - B", insn);
+       ZIP_DEBUG_LINE("Simplify-Operands - B", insn);
 
 
   /* Record all alternatives which are better or equal to the currently
   /* Record all alternatives which are better or equal to the currently
      matching one in the alternative_order array.  */
      matching one in the alternative_order array.  */
@@ -666,6 +683,7 @@
@@ -666,6 +684,7 @@
       validate_change (insn, recog_data.operand_loc[i],
       validate_change (insn, recog_data.operand_loc[i],
                       gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
                       gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
     }
     }
+       ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
+       ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
 
 
   for (i = recog_data.n_dups - 1; i >= 0; i--)
   for (i = recog_data.n_dups - 1; i >= 0; i--)
     {
     {
@@ -679,6 +697,7 @@
@@ -679,6 +698,7 @@
                       gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
                       gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
     }
     }
 
 
+       ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
+       ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
   return apply_change_group ();
   return apply_change_group ();
 }
 }
 
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c
--- gcc-5.3.0-original/gcc/reload1.c    2015-01-15 08:28:42.000000000 -0500
--- gcc-5.3.0-original/gcc/reload1.c    2015-01-15 08:28:42.000000000 -0500
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-03-07 18:25:12.311162959 -0500
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-03-19 12:27:20.657324554 -0400
@@ -2271,11 +2271,11 @@
@@ -785,6 +785,7 @@
 
    stream and a DCE pass should be run to elimiante them.  Else the
 
    return value is FALSE.  */
 
 
 
+extern void zip_debug_rtx(const_rtx);
 
 bool
 
 reload (rtx_insn *first, int global)
 
 {
 
@@ -2271,11 +2272,11 @@
               && spill_stack_slot_width[from_reg] >= total_size
               && spill_stack_slot_width[from_reg] >= total_size
               && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
               && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
                   >= inherent_size)
                   >= inherent_size)
-              && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
-              && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
+              && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align) {
+              && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align) {
Line 9092... Line 9722...
-      else
-      else
+      } else
+      } else
        {
        {
          /* Compute maximum size needed, both for inherent size
          /* Compute maximum size needed, both for inherent size
             and for total size.  */
             and for total size.  */
@@ -3477,11 +3477,14 @@
@@ -3477,11 +3478,14 @@
   /* Eliminate all eliminable registers occurring in operands that
   /* Eliminate all eliminable registers occurring in operands that
      can be handled by reload.  */
      can be handled by reload.  */
   extract_insn (insn);
   extract_insn (insn);
+
+
   for (i = 0; i < recog_data.n_operands; i++)
   for (i = 0; i < recog_data.n_operands; i++)
Line 9109... Line 9739...
       /* For an asm statement, every operand is eliminable.  */
       /* For an asm statement, every operand is eliminable.  */
       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
        {
        {
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload.c gcc-5.3.0-zip/gcc/reload.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload.c gcc-5.3.0-zip/gcc/reload.c
--- gcc-5.3.0-original/gcc/reload.c     2015-01-15 08:28:42.000000000 -0500
--- gcc-5.3.0-original/gcc/reload.c     2015-01-15 08:28:42.000000000 -0500
+++ gcc-5.3.0-zip/gcc/reload.c  2016-02-19 08:15:17.546189655 -0500
+++ gcc-5.3.0-zip/gcc/reload.c  2016-03-19 12:28:30.592811127 -0400
@@ -2707,8 +2707,17 @@
@@ -2707,8 +2707,17 @@
     no_output_reloads = 1;
     no_output_reloads = 1;
 
 
 #ifdef HAVE_cc0
 #ifdef HAVE_cc0
+  // If the instruction depends upon cc0, such as a branch, if_then_else, or
+  // If the instruction depends upon cc0, such as a branch, if_then_else, or
Line 9242... Line 9872...
       cmpxchg >>= (64 / BITS_PER_MARKER - n->range) * BITS_PER_MARKER;
       cmpxchg >>= (64 / BITS_PER_MARKER - n->range) * BITS_PER_MARKER;
       cmpnop &= mask;
       cmpnop &= mask;
     }
     }
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/var-tracking.c gcc-5.3.0-zip/gcc/var-tracking.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/var-tracking.c gcc-5.3.0-zip/gcc/var-tracking.c
--- gcc-5.3.0-original/gcc/var-tracking.c       2015-03-26 09:19:00.000000000 -0400
--- gcc-5.3.0-original/gcc/var-tracking.c       2015-03-26 09:19:00.000000000 -0400
+++ gcc-5.3.0-zip/gcc/var-tracking.c    2016-03-05 20:43:22.535221161 -0500
+++ gcc-5.3.0-zip/gcc/var-tracking.c    2016-03-19 09:31:12.636242911 -0400
@@ -143,6 +143,13 @@
@@ -143,6 +143,13 @@
 #include "rtl-iter.h"
 #include "rtl-iter.h"
 #include "fibonacci_heap.h"
 #include "fibonacci_heap.h"
 
 
+#ifdef DO_ZIP_DEBUG
+#ifdef DO_ZIP_DEBUG

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