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Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [zasm/] [test.S] - Diff between revs 26 and 34

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Rev 26	Rev 34
Line 81...	Line 81...
`#define CARRY_TEST`	`#define CARRY_TEST`
`#define LOOP_TEST`	`#define LOOP_TEST`
`#define SHIFT_TEST`	`#define SHIFT_TEST`
`#define TRAP_TEST`	`#define TRAP_TEST`
`#define MPY_TEST`	`#define MPY_TEST`
`// #define PUSH_TEST`	`#define PUSH_TEST`
`test:`	`test:`
`#ifdef DO_TEST_ASSEMBLER`	`#ifdef DO_TEST_ASSEMBLER`
`; We start out by testing our assembler. We give it some instructions, which`	`; We start out by testing our assembler. We give it some instructions, which`
`; are then manually checked by disassembling/dumping the result and making`	`; are then manually checked by disassembling/dumping the result and making`
`; certain they match. This is not an automated test, but it is an important`	`; certain they match. This is not an automated test, but it is an important`
Line 163...	Line 163...
`mov dead_beef.base(pc),r10 ; Now, let's get the address`	`mov dead_beef.base(pc),r10 ; Now, let's get the address`
`lod dead_beef.values(r10),r10 ; r10 now equals 0xdeadbeef`	`lod dead_beef.values(r10),r10 ; r10 now equals 0xdeadbeef`
`cmp r10,r9`	`cmp r10,r9`
`bnz test_failure`	`bnz test_failure`

	`; Test whether or not our operator precedence rules work`
	`ldi 5+3*8,r0`
	`ldi 3*8+5,r1`
	`cmp r0,r1`
	`bnz test_failure`
	`ldi (5+3)*8,r0`
	`ldi 8*(3+5),r1`
	`cmp r0,r1`
	`bnz test_failure`

`; Test whether or not we can properly decode OCTAL values`	`; Test whether or not we can properly decode OCTAL values`
`clr r0 ; Re-clear our register set first`	`clr r0 ; Re-clear our register set first`
`clr r1`	`clr r1`
`clr r2`	`clr r2`
`clr r3`	`clr r3`
Line 265...	Line 275...
`testbench:`	`testbench:`
`// Let's build a software test bench.`	`// Let's build a software test bench.`
`ldi $c0000000h,r12 ; Set R12 to point to our peripheral address`	`ldi $c0000000h,r12 ; Set R12 to point to our peripheral address`
`mov r12,ur12`	`mov r12,ur12`
`mov test_start(pc),upc`	`mov test_start(pc),upc`
	`mov stack(pc),usp`
`ldi 0x8000ffff,r0 ; Clear interrupts, turn all vectors off`	`ldi 0x8000ffff,r0 ; Clear interrupts, turn all vectors off`
`sto r0,(r12)`	`sto r0,(r12)`
`rtu`	`rtu`
`mov ucc,r0`	`mov ucc,r0`
`cmp sys.cctrap,r0`	`cmp sys.cctrap,r0`
Line 492...	Line 503...
`ldi 0x40000000,r1`	`ldi 0x40000000,r1`
`cmp r0,r1`	`cmp r0,r1`
`trap.ne r11`	`trap.ne r11`
`#endif`	`#endif`

	`#ifdef PUSH_TEST`
	`ldi $0x0e000,r11 // Mark our test`
	`ldi 0x01248cab,r0`
	`ldi 0xd5312480,r1 // Let's see if we can preserve this as well`
	`mov r1,r7`
	`JSR(reverse_bit_order,R4); // *SP = 0x010013d`
	`cmp r0,r1`
	`trap.ne r11`
	`cmp r0,r7`
	`trap.ne r11`
	`#endif`
`// Return success / Test the trap interrupt`	`// Return success / Test the trap interrupt`
`clr r11`	`clr r11`
`trap r11`	`trap r11`
`noop`	`noop`
`noop`	`noop`
Line 510...	Line 532...
`reverse_bit_order:`	`reverse_bit_order:`
`PUSH(R1,SP)`	`PUSH(R1,SP)`
`PUSH(R2,SP)`	`PUSH(R2,SP)`
`LDI 32,R1`	`LDI 32,R1`
`CLR R2`	`CLR R2`
	`reverse_bit_order_loop:`
`LSL 1,R2`	`LSL 1,R2`
`LSR 1,R0`	`LSR 1,R0`
`OR.C 1,R2`	`OR.C 1,R2`
`SUB 1,R1`	`SUB 1,R1`
`BNZ reverse_bit_order_loop`	`BNZ reverse_bit_order_loop`
Line 521...	Line 544...
`POP(R2,SP)`	`POP(R2,SP)`
`POP(R1,SP)`	`POP(R1,SP)`
`RET`	`RET`
`#endif`	`#endif`
`fill 512,0`	`fill 512,0`
`stack:`	`stack: // Must point to a valid word initially`
`word 0`	`word 0`

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[/] [zipcpu/] [trunk/] [sw/] [zasm/] [test.S] - Diff between revs 26 and 34